Comparator and successive approximation analog-to-digital converter

Abstract

The comparator and successive approximation analog-digital converter can input the first output signal and the second output signal output by the input stage circuit and the third output signal and the fourth output signal output by the noise shaping input stage circuit into the latch stage circuit after respectively carrying out noise isolation, so that the output ends of the input stage circuit and the noise shaping input stage circuit are independent of each other, the kickback noise caused by the shared output ends of the input stage circuit and the noise shaping input stage circuit can be avoided, and the performance of the four-input comparator can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit, in particular to a comparator and successive approximation analog-to-digital converter. BACKGROUND

[0002] An analog-to-digital converter (ADC) is a device that converts a continuous analog signal acquisition into a discrete digital signal for digital analysis and processing. A successive approximation analog-to-digital converter (SAR ADC) is a method of finding by bisection, through an integrated digital-to-analog converter (DAC) to generate a new analog voltage approximation of the original input analog signal, and the integrated digital-to-analog converter (DAC) corresponding to the number of input as the output of the ADC.

[0003] A noise-shaping successive approximation analog-to-digital converter is a kind of successive approximation analog-to-digital converter, which combines oversampling and noise shaping with successive approximation analog-to-digital converter to improve the accuracy of successive approximation analog-to-digital converter under the condition of ensuring speed and power consumption. In order to realize this function, four-input comparators are often used in noise-shaping successive approximation analog-to-digital converters.

[0004] However, there is a lot of noise in the existing four-input comparators, which affects the performance of the comparator. SUMMARY

[0005] The problem solved by the present application is to provide a comparator and successive approximation analog-to-digital converter to improve the performance of the comparator.

[0006] To solve the above problems, the present application provides a comparator, the comparator has a sampling phase and a comparison phase, and the comparator comprises:

[0007] An input stage circuit is adapted to amplify the received first input signal and second input signal respectively in the comparison phase, generate corresponding first output signal and second output signal and transmit to the isolation transmission circuit;

[0008] A noise-shaping input stage circuit is adapted to amplify the received third input signal and fourth input signal respectively in the comparison phase, generate corresponding third output signal and fourth output signal and transmit to the isolation transmission circuit;

[0009] The isolation transmission circuit is adapted to isolate the received first output signal, second output signal, third output signal and fourth output signal respectively in the comparison phase, generate first noise isolation signal, second noise isolation signal, third noise isolation signal and fourth noise isolation signal and input to the latch stage circuit;

[0010] The latch stage circuit is adapted to compare a first superimposed level signal of the received first noise isolation signal and the third noise isolation signal with a second superimposed level signal of the second noise isolation signal and the fourth noise isolation signal, generate a corresponding comparison result and output.

[0011] Optionally, the input stage circuit comprises a first input amplification unit and a second input amplification unit.

[0012] The first input amplification unit is adapted to amplify the first input signal to generate the first output signal.

[0013] The second input amplification unit is adapted to amplify the second input signal to generate the second output signal.

[0014] Optionally, the first input amplification unit comprises a first PMOS tube.

[0015] The gate end of the first PMOS tube is used to receive the first input signal, the source end of the first PMOS tube is coupled with a power supply voltage, and the drain end of the first PMOS tube serves as or is coupled with a first output end of the input stage circuit.

[0016] Optionally, the second input amplification unit comprises a second PMOS tube.

[0017] The gate end of the second PMOS tube is used to receive the second input signal, the source end of the second PMOS tube is coupled with a power supply voltage, and the drain end of the second PMOS tube serves as or is coupled with a second output end of the input stage circuit.

[0018] Optionally, the input stage circuit further comprises:

[0019] The first latch unit has a first latch node and a second latch node, and is adapted to latch the first output signal and the second output signal to the first latch node and the second latch node respectively and input to the isolation transmission circuit.

[0020] Optionally, the first latch unit comprises a first NMOS tube and a second NMOS tube.

[0021] The gate end of the first NMOS tube is coupled with the drain end of the second NMOS tube, and serves as or is coupled with the second latch node, the source end of the first NMOS tube and the source end of the second NMOS tube are both coupled with a ground voltage, the drain end of the first NMOS tube is coupled with the gate end of the second NMOS tube, and serves as or is coupled with the first latch node.

[0022] Optionally, the input stage circuit further comprises a first gain improving unit and a second gain improving unit;

[0023] The first gain improving unit is adapted to improve the output gain of the first input amplification unit.

[0024] The second gain improving unit is adapted to improve the output gain of the second input amplification unit.

[0025] Optionally, the first gain improving unit comprises a third NMOS transistor.

[0026] The gate terminal and the drain terminal of the third NMOS transistor are coupled with the output terminal of the first input amplification unit, and the source terminal of the third NMOS transistor is coupled with a ground voltage.

[0027] Optionally, the second gain improving unit comprises a fourth NMOS transistor.

[0028] The gate terminal and the drain terminal of the fourth NMOS transistor are coupled with the output terminal of the second input amplification unit, and the source terminal of the fourth NMOS transistor is coupled with a ground voltage.

[0029] Optionally, the noise shaping input stage circuit comprises a first noise shaping amplification unit and a second noise shaping amplification unit.

[0030] The first noise shaping amplification unit is adapted to amplify the received third input signal to generate the third output signal.

[0031] The second noise shaping amplification unit is adapted to amplify the received fourth input signal to generate the fourth output signal.

[0032] Optionally, the first noise shaping amplification unit comprises a third PMOS transistor.

[0033] The gate terminal of the third PMOS transistor is used to receive the third input signal, the source terminal of the third PMOS transistor is coupled with a power supply voltage, and the drain terminal of the third PMOS transistor serves as or is coupled with a first output terminal of the noise shaping amplification unit.

[0034] Optionally, the second noise shaping amplification unit comprises a fourth PMOS transistor.

[0035] The gate terminal of the fourth PMOS transistor is used to receive the fourth input signal, the source terminal of the fourth PMOS transistor is coupled with a power supply voltage, and the drain terminal of the fourth PMOS transistor serves as or is coupled with a second output terminal of the noise shaping amplification unit.

[0036] Optionally, the noise shaping input stage circuit further comprises:

[0037] a second latch unit having a third latch node and a fourth latch node, and adapted to latch the third output signal and the fourth output signal to the third latch node and the fourth latch node respectively and input to the isolation transmission circuit.

[0038] Optionally, the second latch unit comprises a fifth NMOS transistor and a sixth NMOS transistor;

[0039] a gate terminal of the fifth NMOS transistor is coupled with a drain terminal of the sixth NMOS transistor and serves as or is coupled with the fourth latch node, a source terminal of the fifth NMOS transistor and a source terminal of the sixth NMOS transistor are both coupled with a ground voltage, a drain terminal of the fifth NMOS transistor is coupled with a gate terminal of the sixth NMOS transistor and serves as or is coupled with the third latch node.

[0040] Optionally, the noise shaping input stage further comprises a third gain improving unit and a fourth gain improving unit;

[0041] the third gain improving unit is adapted to improve an output gain of the first noise shaping amplification unit;

[0042] the fourth gain improving unit is adapted to improve an output gain of the second noise shaping amplification unit.

[0043] Optionally, the third gain improving unit comprises a seventh NMOS transistor;

[0044] a gate terminal and a drain terminal of the seventh NMOS transistor are coupled with each other and coupled with an output terminal of the first noise shaping amplification unit, and a source terminal of the seventh NMOS transistor is coupled with a ground voltage.

[0045] Optionally, the fourth gain improving unit comprises an eighth NMOS transistor;

[0046] a gate terminal and a drain terminal of the eighth NMOS transistor are coupled with each other and coupled with an output terminal of the second noise shaping amplification unit, and a source terminal of the eighth NMOS transistor is coupled with a ground voltage.

[0047] Optionally, the isolation transmission circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor;

[0048] a first terminal of the first capacitor is coupled with a first output terminal of the input stage circuit, and a second terminal of the first capacitor is coupled with a first input terminal of the latch stage circuit;

[0049] A first end of the second capacitor is coupled to a second output end of the input stage circuit, and a second end of the second capacitor is coupled to a second input end of the latch stage circuit.

[0050] A first end of the third capacitor is coupled to a first output end of the noise shaping input stage circuit, and a second end of the third capacitor is coupled to a first input end of the latch stage circuit.

[0051] A first end of the fourth capacitor is coupled to a second output end of the noise shaping input stage circuit, and a second end of the fourth capacitor is coupled to a second input end of the latch stage circuit.

[0052] Optionally, the latch stage circuit comprises a switch unit, a first latch amplification unit, a second latch amplification unit, and a third latch unit.

[0053] The switch unit is adapted to be turned on during the comparison phase.

[0054] The first latch amplification unit is adapted to amplify a first superimposed level signal of the first output signal and the third output signal when the switch unit is turned on.

[0055] The second latch amplification unit is adapted to amplify a second superimposed level signal of the received second output signal and the fourth output signal when the switch unit is turned on.

[0056] The third latch unit is adapted to latch and compare the amplified first superimposed level signal and the amplified second superimposed level signal, and output a corresponding comparison result.

[0057] Optionally, the switch unit comprises a ninth NMOS transistor.

[0058] A gate end of the ninth NMOS transistor is used to receive a first clock control signal, a source end of the ninth NMOS transistor is coupled to a ground voltage, and a drain end of the ninth NMOS transistor is coupled to the first latch amplification unit and the second latch amplification unit, respectively.

[0059] Optionally, the first latch amplification unit comprises a tenth NMOS transistor.

[0060] A gate end of the tenth NMOS transistor is used as or coupled to a first input end of the latch stage circuit, a source end of the tenth NMOS transistor is coupled to the switch unit, and a drain end of the tenth NMOS transistor is coupled to the third latch unit.

[0061] Optionally, the second latch amplification unit comprises an eleventh NMOS transistor.

[0062] The gate terminal of the eleventh NMOS transistor is coupled to or serves as a second input terminal of the latch stage circuit, the source terminal of the eleventh NMOS transistor is coupled to the switch unit, and the drain terminal of the eleventh NMOS transistor is coupled to the third latch unit.

[0063] Optionally, the third latch unit comprises a fifth PMOS transistor, a twelfth NMOS transistor, a sixth PMOS transistor and a thirteenth NMOS transistor.

[0064] The gate terminal of the fifth PMOS transistor is coupled to the gate terminal of the twelfth NMOS transistor and coupled to the drain terminal of the sixth PMOS transistor and the drain terminal of the thirteenth NMOS transistor, and serves as or is coupled to an inverting output terminal of the comparator; the drain terminal of the fifth PMOS transistor is coupled to the drain terminal of the twelfth NMOS transistor and coupled to the gate terminal of the sixth PMOS transistor and the gate terminal of the thirteenth NMOS transistor, and serves as or is coupled to a non-inverting output terminal of the comparator; the source terminal of the fifth PMOS transistor and the source terminal of the sixth PMOS transistor are coupled to a power supply voltage; the source terminal of the twelfth NMOS transistor is coupled to the first latch amplifier unit; and the source terminal of the thirteenth NMOS transistor is coupled to the second latch amplifier unit.

[0065] Optionally, the comparator further comprises at least one of:

[0066] a first biasing circuit adapted to provide a biasing current for the input stage circuit;

[0067] a second biasing circuit adapted to provide a biasing current for the noise shaping input stage circuit.

[0068] Optionally, the first biasing circuit comprises a seventh PMOS transistor.

[0069] The gate terminal of the seventh PMOS transistor is coupled to a biasing voltage, the source terminal of the seventh PMOS transistor is coupled to a power supply voltage, and the drain terminal of the seventh PMOS transistor is coupled to the input stage circuit.

[0070] Optionally, the second biasing circuit comprises an eighth PMOS transistor.

[0071] The gate terminal of the eighth PMOS transistor is coupled to a biasing voltage, the source terminal of the eighth PMOS transistor is coupled to a power supply voltage, and the drain terminal of the eighth PMOS transistor is coupled to the noise shaping input stage circuit.

[0072] Optionally, the comparator further comprises at least one of:

[0073] a first output reset circuit adapted to reset the non-inverting output terminal of the comparator to the power supply voltage during the sampling phase;

[0074] a first output reset circuit adapted to reset an inverting output terminal of the comparator to a power supply voltage at the sampling phase.

[0075] Optionally, the first output reset circuit comprises a ninth PMOS transistor.

[0076] a gate terminal of the ninth PMOS transistor is configured to receive a first clock control signal, a source terminal of the ninth PMOS transistor is coupled to the power supply voltage, and a drain terminal of the ninth PMOS transistor is coupled to a non-inverting output terminal of the comparator.

[0077] Optionally, the second output reset circuit comprises a tenth PMOS transistor.

[0078] a gate terminal of the tenth PMOS transistor is configured to receive the first clock control signal, a source terminal of the tenth PMOS transistor is coupled to the power supply voltage, and a drain terminal of the tenth PMOS transistor is coupled to the inverting output terminal of the comparator.

[0079] Optionally, the comparator further comprises at least one of:

[0080] a first input reset circuit adapted to reset a first input terminal of the input stage circuit to a preset common mode voltage at the sampling phase;

[0081] a second input reset circuit adapted to reset a second input terminal of the input stage circuit to the common mode voltage at the sampling phase;

[0082] a third input reset circuit adapted to reset a first input terminal of the noise shaping input stage circuit to the common mode voltage at the sampling phase;

[0083] a fourth input reset circuit adapted to reset a second input terminal of the noise shaping input stage circuit to the common mode voltage at the sampling phase;

[0084] a fifth input reset circuit adapted to reset a first input terminal of the latch stage circuit to the common mode voltage at the sampling phase;

[0085] a sixth input reset circuit adapted to reset a second input terminal of the latch stage circuit to the common mode voltage at the sampling phase.

[0086] Optionally, the first input reset circuit comprises a first switch.

[0087] a control terminal of the first switch is configured to receive a second clock control signal, a first conduction terminal of the first switch is configured to receive the common mode voltage, and a second conduction terminal of the first switch is coupled to the first input terminal of the input stage circuit.

[0088] Optionally, the second input reset circuit comprises a second switch.

[0089] The control end of the second switch is configured to receive the second clock control signal, the first conduction end of the second switch is configured to receive the common-mode voltage, and the second conduction end of the second switch is coupled with the second input end of the input stage circuit.

[0090] Optionally, the third input reset circuit comprises a third switch.

[0091] The control end of the third switch is configured to receive the second clock control signal, the first conduction end of the third switch is configured to receive the common-mode voltage, and the second conduction end of the third switch is coupled with the first input end of the noise shaping input stage circuit.

[0092] Optionally, the fourth input reset circuit comprises a fourth switch.

[0093] The control end of the fourth switch is configured to receive the second clock control signal, the first conduction end of the fourth switch is configured to receive the common-mode voltage, and the second conduction end of the fourth switch is coupled with the second input end of the noise shaping input stage circuit.

[0094] Optionally, the fifth input reset circuit comprises a fifth switch.

[0095] The control end of the fifth switch is configured to receive the second clock control signal, the first conduction end of the fifth switch is configured to receive the common-mode voltage, and the second conduction end of the fifth switch is coupled with the first input end of the latch stage circuit.

[0096] Optionally, the sixth input reset circuit comprises a sixth switch.

[0097] The control end of the sixth switch is configured to receive the second clock control signal, the first conduction end of the sixth switch is configured to receive the common-mode voltage, and the second conduction end of the sixth switch is coupled with the second input end of the latch stage circuit.

[0098] Correspondingly, the embodiment of the present application also provides an asynchronous successive approximation analog-to-digital converter, comprising the comparator of any one of the above.

[0099] Compared with the prior art, the technical scheme of the present application has the following advantages:

[0100] The scheme can realize noise isolation of the first output signal and the second output signal output by the input stage circuit and the third output signal and the fourth output signal output by the noise shaping input stage circuit, and input the signals to the latch stage circuit, so that the output ends of the input stage circuit and the noise shaping input stage circuit are independent, the kickback noise caused by the shared output ends of the input stage circuit and the noise shaping input stage circuit can be avoided, and the performance of the four-input comparator can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0101] Figure 1 Fig. 1 is a structural schematic diagram of a four-input comparator according to the present application;

[0102] Figure 2 Fig. 2 is a frame structure schematic diagram of a comparator according to the present application;

[0103] Figure 3 Fig. 3 is a structural schematic diagram of an input stage circuit according to the present application;

[0104] Figure 4 Fig. 4 is a structural schematic diagram of a noise shaping input stage circuit according to the present application;

[0105] Figure 5 Fig. 5 is a structural schematic diagram of an isolation transmission circuit according to the present application;

[0106] Figure 6 Fig. 6 is a structural schematic diagram of a latch stage circuit according to the present application;

[0107] Figure 7 Fig. 7 is a timing schematic diagram of related pulse signals of a comparator according to the present application. DETAILED DESCRIPTION

[0108] As known from the background, the four-input comparator for the successive approximation analog-to-digital converter has the problem of poor performance.

[0109] Referring to Figure 1 A four-input comparator for a successive approximation analog-to-digital converter, specifically comprising a pre-amplification input stage circuit 11, a noise shaping input stage circuit 12 and a latch stage circuit 13.

[0110] The first input end and the second input end of the pre-amplification input stage circuit 11 are used for receiving a first input signal Inp and a second input signal Inn respectively, and the first output signal and the second output signal generated after amplification are transmitted to the first input end and the second input end of the latch stage 13.

[0111] The first output signal output by the first input end of the pre-amplification input stage circuit 11 and the third input signal output by the first input end of the noise shaping input stage 12 are superimposed as a first input signal xp, and the second output signal output by the first output end of the noise shaping input stage 12 and the fourth input signal output by the second input end of the noise shaping input stage 12 are superimposed as a second input signal xn, and the latch stage circuit 13 outputs the corresponding comparison result according to the size of the received first input signal xp and second input signal xn.

[0112] In the above four-input comparator, the output ends of the input stage circuit 11 and the noise shaping input stage circuit 12 are shared, and there will be a large kickback noise, which seriously affects the performance of the four-input comparator.

[0113] To solve the above problems, the technical scheme in the embodiment of the present application sets an isolation transmission circuit between the input stage circuit, the noise shaping input stage circuit and the latch stage circuit, so that the first output signal and the second output signal output by the input stage circuit and the third output signal and the fourth output signal output by the noise shaping input stage circuit are respectively input to the latch stage circuit after noise isolation, so that the output ends of the input stage circuit and the noise shaping input stage circuit are independent of each other, and the kickback noise caused by the sharing of the output ends of the input stage circuit and the noise shaping input stage circuit can be avoided, so that the performance of the four-input comparator can be improved.

[0114] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0115] Figure 2 The structure schematic diagram of a comparator in the embodiment of the present application is shown. Figure 2 The comparator in the embodiment of the present application can include an input stage circuit 21, a noise shaping input stage circuit 22 and a latch stage circuit 24.

[0116] The comparator has a first pair of input terminals (not shown), a second pair of input terminals (not shown), a non-inverted output terminal (not shown), and an inverted output terminal (not shown); the first pair of input terminals includes a first input terminal (not shown) and a second input terminal (not shown), and the second pair of input terminals includes a third input terminal (not shown) and a fourth input terminal (not shown).

[0117] Referring to Figure 3 The input stage circuit 21 has a first input terminal and a second input terminal. The first input terminal of the input stage circuit 21 serves as or is coupled with the first input terminal of the comparator to receive a first input signal Inp, and the second input terminal of the input stage circuit 21 serves as or is coupled with the second input terminal of the comparator to receive a second input signal Inn. The input stage circuit 21 can amplify the first input signal Inp received by the first input terminal and the second input signal Inn received by the second input terminal respectively to generate corresponding first and second output signals Inp-out and Inn-out when the comparison is performed, and transmit the first and second output signals Inp-out and Inn-out to the isolation transmission circuit respectively. Wherein,

[0118] Referring to Figure 3 In an embodiment of the present application, the input stage circuit 21 includes a first input amplification unit (not shown) and a second input amplification unit (not shown). Wherein:

[0119] The first input amplification unit has an input terminal and an output terminal. The input terminal of the first input amplification unit serves as or is coupled with the first input terminal of the input stage circuit 21 to receive the first input signal Inp, and the output terminal of the first input amplification unit serves as or is coupled with the second output terminal of the input stage circuit 21 to output the first output signal Inp-out. The first input amplification unit can amplify the received first input signal Inp to generate the first output signal Inp-out.

[0120] Specifically, the first input amplification unit includes a first PMOS tube PM1. Wherein, the gate terminal of the first PMOS tube PM1 is used to receive the first input signal Inp, the source terminal of the first PMOS tube PM1 is coupled with a power supply voltage avdd, and the drain terminal of the first PMOS tube PM1 serves as or is coupled with the first output terminal of the input stage circuit 21.

[0121] The second input amplification unit has an input end and an output end. The input end of the second input amplification unit is used as or coupled with the second input end of the input stage circuit 21 to receive the second input signal Inn, and the output end of the second input amplification unit is used as or coupled with the second output end of the input stage circuit 21 to output the second output signal Inn-out. The second input amplification unit can amplify the received second input signal Inn to generate the second output signal Inn-out.

[0122] Specifically, the second input amplification unit includes a second PMOS tube PM2. The gate end of the second PMOS tube PM2 is used to receive the second input signal Inn, the source end of the second PMOS tube PM2 is coupled with the power supply voltage avdd, and the drain end of the second PMOS tube PM2 is used as or coupled with the second output end of the input stage circuit 21.

[0123] In another embodiment of the present application, the input stage circuit 21 further includes a first latch unit (not shown).

[0124] The first latch unit has a first latch node N1 and a second latch node N2. The first latch unit can latch the first output signal Inn-out to the first latch node N1 and input to the first input end of the isolation transmission circuit, and latch the second output signal Inn-out to the second latch node N2 and input to the second input end of the isolation transmission circuit 23.

[0125] Specifically, the first latch unit includes a first NMOS tube NM1 and a second NMOS tube NM2. The gate end of the first NMOS tube NM1 is coupled with the drain end of the second NMOS tube NM2 and used as or coupled with the second latch node N2, the source end of the first NMOS tube NM1 and the source end of the second NMOS tube NM2 are both coupled with the ground voltage avss, the drain end of the first NMOS tube NM1 is coupled with the gate end of the second NMOS tube NM2 and used as or coupled with the first latch node N1.

[0126] In yet another embodiment of the present application, the input stage circuit 21 further includes a first gain improvement unit (not shown) and a second gain improvement unit (not shown). Wherein:

[0127] The first gain improving unit can improve the output gain of the first input amplifying unit. Specifically, the first gain improving unit comprises a third NMOS tube NM3. The gate end and the drain end of the third NMOS tube NM3 are coupled with the output end of the first input amplifying unit, and the source end of the third NMOS tube NM3 is coupled with the ground voltage avss.

[0128] The second gain improving unit can improve the output gain of the second input amplifying unit. Specifically, the second gain improving unit comprises a fourth NMOS tube NM4. The gate end and the drain end of the fourth NMOS tube NM4 are coupled with the output end of the second input amplifying unit, and the source end of the fourth NMOS tube NM4 is coupled with the ground voltage avss.

[0129] Please refer to Figure 4 The noise shaping input stage circuit 22 has a first input end and a second input end, a first output end and a second output end. The first input end of the noise shaping input stage circuit 22 serves as or is coupled with the third input end of the comparator, and is used to receive the third input signal Inp-ns; the second input end of the noise shaping input stage circuit 22 serves as or is coupled with the fourth input end of the comparator, and is used to receive the fourth input signal Inn-ns. When the comparator is in the comparison phase, the noise shaping input stage circuit 22 can respectively amplify the third input signal Inp-ns received by the first input end and the fourth input signal Inn-ns received by the second input end, to generate the corresponding third output signal Inp-ns-out and the fourth output signal Inn-ns-out.

[0130] In an embodiment of the present application, the noise shaping input stage circuit 22 comprises a first noise shaping amplifying unit (not labeled) and a second noise shaping amplifying unit (not labeled). Wherein:

[0131] The first noise shaping amplifying unit has an input end and an output end. The input end of the first noise shaping amplifying unit serves as or is coupled with the first input end of the noise shaping input stage circuit 22, and is used to receive the third input signal Inp-ns. The first noise shaping amplifying unit can amplify the received third input signal Inp-ns to generate the third output signal Inp-ns-out.

[0132] Specifically, the first noise shaping amplification unit includes a third PMOS tube PM3. The gate end of the third PMOS tube PM3 is configured to receive the third input signal Inp-ns, the source end of the third PMOS tube PM3 is coupled with a power supply voltage avdd, and the drain end of the third PMOS tube PM3 serves as or is coupled with the first output end of the noise shaping input stage circuit 22.

[0133] The second noise shaping amplification unit has an input end and an output end. The input end of the second noise shaping amplification unit serves as or is coupled with the second input end of the noise shaping input stage circuit 22 and is configured to receive a fourth input signal Inn-ns. The first noise shaping amplification unit can amplify the received fourth input signal Inn-ns to generate a fourth output signal Inn-ns-out.

[0134] Specifically, the second noise shaping amplification unit includes a fourth PMOS tube PM4. The gate end of the fourth PMOS tube PM4 is coupled with the fourth input signal Inn-ns, the source end of the fourth PMOS tube PM4 is coupled with the power supply voltage avdd, and the drain end of the fourth PMOS tube PM4 serves as or is coupled with the second output end of the noise shaping input stage circuit 22.

[0135] In an embodiment of the present application, the noise shaping input stage circuit 22 can further include a second latch unit (not shown).

[0136] The second latch unit has a third latch node N3 and a fourth latch node N4. The second latch unit can latch the third output signal Inp-ns-out to the third latch node N3 and input to the third input end of the isolation transmission circuit, and latch the fourth output signal Inn-ns-out to the fourth latch node N4 and input to the fourth input end of the isolation transmission circuit.

[0137] Specifically, the second latch unit includes a fifth NMOS tube NM5 and a sixth NMOS tube NM6. The gate end of the fifth NMOS tube NM5 is coupled with the drain end of the sixth NMOS tube NM6 and serves as or is coupled with the fourth latch node N4, the source end of the fifth NMOS tube NM5 and the source end of the sixth NMOS tube NM6 are both coupled with a ground voltage avss, the drain end of the fifth NMOS tube NM5 is coupled with the gate end of the sixth NMOS tube NM6 and serves as or is coupled with the third latch node N3.

[0138] In another embodiment of the present application, the noise shaping input stage 22 further comprises a third gain increasing unit (not shown) and a fourth gain increasing unit (not shown).

[0139] The third gain increasing unit can increase the output gain of the first noise shaping amplification unit. Specifically, the third gain increasing unit comprises a seventh NMOS transistor NM7. The gate terminal and the drain terminal of the seventh NMOS transistor NM7 are coupled with the output terminal of the first noise shaping amplification unit, and the source terminal of the seventh NMOS transistor NM7 is coupled with the ground voltage avss.

[0140] The fourth gain increasing unit can increase the output gain of the second noise shaping amplification unit. Specifically, the fourth gain increasing unit comprises an eighth NMOS transistor NM8. The gate terminal and the drain terminal of the eighth NMOS transistor NM8 are coupled with the output terminal of the second noise shaping amplification unit, and the source terminal of the eighth NMOS transistor NM8 is coupled with the ground voltage avss.

[0141] Please refer to Figure 5 In a specific implementation, the isolation transmission circuit 23 has a first input terminal, a second input terminal, a third input terminal and a fourth input terminal, and has a first output terminal, a second output terminal, a third output terminal and a fourth output terminal. The first input terminal of the isolation transmission circuit 23 is coupled with the first output terminal of the input stage circuit 21, the second input terminal of the isolation transmission circuit 23 is coupled with the second output terminal of the input stage circuit 21, the third input terminal of the isolation transmission circuit 23 is coupled with the first output terminal of the noise shaping input stage circuit 21, and the fourth input terminal of the isolation transmission circuit 23 is coupled with the second output terminal of the noise shaping input stage circuit 21. When the comparator is in the comparison phase, the isolation transmission circuit 23 can perform noise isolation on the first output signal Inp-out received by the first input terminal, the second output signal Inn-out received by the second input terminal, the third output signal Inp-ns-out received by the third input terminal and the fourth output signal Inn-ns-out received by the fourth input terminal, respectively, to generate a first noise isolation signal, a second noise isolation signal, a third noise isolation signal and a fourth noise isolation signal, and input them to the latch stage circuit.

[0142] Specifically, the isolation transmission circuit 23 comprises a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. Wherein, the first end of the first capacitor C1 is coupled with the first output end of the input stage circuit, and the second end of the first capacitor C1 is coupled with the first input end (N5 node) of the latch stage circuit; the first end of the second capacitor C2 is coupled with the second output end of the input stage circuit, and the second end of the second capacitor C2 is coupled with the second input end (N6 node) of the latch stage circuit; the first end of the third capacitor C3 is coupled with the first output end of the noise shaping input stage circuit, and the second end of the third capacitor C3 is coupled with the first input end of the latch stage circuit; the first end of the fourth capacitor C4 is coupled with the second output end of the noise shaping input stage circuit, and the second end of the fourth capacitor C4 is coupled with the second input end of the latch stage circuit.

[0143] Please refer to Figure 6 In a specific implementation, the latch stage circuit 24 has a first input end and a second input end, a non-inverted output end and an inverted output end. Wherein, the first input end of the latch stage circuit 24 is coupled with the first output end and the third output end of the isolation transmission circuit respectively, and the second input end of the latch stage circuit 24 is coupled with the second output end and the fourth output end of the isolation transmission circuit respectively. The latch stage circuit 24 can receive the first superimposed level signal of the first noise isolation signal and the third noise isolation signal and the second superimposed level signal of the second noise isolation signal and the fourth noise isolation signal for comparison, generate a corresponding comparison result and output through the non-inverted output end and the inverted output end respectively.

[0144] In an embodiment of the present application, the latch stage circuit 24 comprises a switch unit (not marked), a first latch amplification unit (not marked), a second latch amplification unit (not marked) and a third latch unit (not marked). Wherein:

[0145] The switch unit has a control end, a first conduction end and a second conduction end. Wherein, the control end of the switch unit is used for receiving the first clock control signal clk1, the first conduction end of the switch unit is coupled with the first latch amplification unit and the second latch amplification unit respectively, and the second conduction end of the switch unit is coupled with the ground voltage avss. The switch unit can be turned on when the comparator is in comparison phase.

[0146] Specifically, the switch unit includes a ninth NMOS transistor NM9. The gate terminal of the ninth NMOS transistor NM9 is coupled to or serves as the control terminal of the switch unit and is configured to receive a first clock control signal clk1. The source terminal of the ninth NMOS transistor NM9 is coupled to or serves as the first conduction terminal of the switch unit and is coupled to a ground voltage avss. The drain terminal of the ninth NMOS transistor NM9 is coupled to or serves as the second conduction terminal of the switch unit and is coupled to the first latch amplification unit and the second latch amplification unit, respectively.

[0147] The first latch amplification unit has a control terminal, a first conduction terminal, and a second conduction terminal. The control terminal of the first latch amplification unit is coupled to or serves as the first input terminal of the latch stage circuit 24. The first conduction terminal of the first latch amplification unit is coupled to the third latch unit. The second conduction terminal of the first latch amplification unit is coupled to the switch unit. The first latch amplification unit can amplify a first superimposed level signal of the received first noise isolation signal and the third noise isolation signal when the switch unit is turned on.

[0148] Specifically, the first latch amplification unit includes a tenth NMOS transistor NM10. The gate terminal of the tenth NMOS transistor NM10 is coupled to or serves as the first input terminal of the latch stage circuit 24. The source terminal of the tenth NMOS transistor NM10 is coupled to the switch unit. The drain terminal of the tenth NMOS transistor NM10 is coupled to the third latch unit.

[0149] The second latch amplification unit has a control terminal, a first conduction terminal, and a second conduction terminal. The control terminal of the second latch amplification unit is coupled to or serves as the second input terminal of the latch stage circuit 24. The first conduction terminal of the second latch amplification unit is coupled to the third latch unit. The second conduction terminal of the second latch amplification unit is coupled to the switch unit. The second latch amplification unit can amplify a second superimposed level signal of the received second noise isolation signal and the fourth noise isolation signal when the switch unit is turned on.

[0150] Specifically, the second latch amplification unit includes an eleventh NMOS transistor NM11. The gate terminal of the eleventh NMOS transistor NM11 is coupled to or serves as the second input terminal of the latch stage circuit 24. The source terminal of the eleventh NMOS transistor NM11 is coupled to the switch unit. The drain terminal of the eleventh NMOS transistor NM11 is coupled to the third latch unit.

[0151] The third latch unit has a first input end, a second input end, a first output end and a second output end. The first input end of the third latch unit is coupled with the first latch amplification unit, the second input end of the third latch unit is coupled with the second latch amplification unit, the first output end of the third latch unit is used as or coupled with the non-inverting output end of the comparator, and the second output end of the third latch unit is used as or coupled with the inverting output end of the comparator. The third latch unit can latch and compare the amplified first superposition level signal and the amplified second superposition level signal, output the corresponding comparison result, and output through the first output end and the second output end respectively.

[0152] Specifically, the third latch unit includes a fifth PMOS tube PM5, a twelfth NMOS tube NM12, a sixth PMOS tube PM6 and a thirteenth NMOS tube NM13. The gate end of the fifth PMOS tube PM5 is coupled with the gate end of the twelfth NMOS tube NM12 and the drain end of the sixth PMOS tube PM6 and the drain end of the thirteenth NMOS tube NM13, and is used as or coupled with the inverting output end of the comparator. The drain end of the fifth PMOS tube PM5 is coupled with the drain end of the twelfth NMOS tube NM12 and the gate end of the sixth PMOS tube PM6 and the gate end of the thirteenth NMOS tube NM13, and is used as or coupled with the non-inverting output end of the comparator. The source end of the fifth PMOS tube PM5 and the source end of the sixth PMOS tube PM6 are coupled with the power supply voltage avdd. The source end of the twelfth NMOS tube NM12 is coupled with the first latch amplification unit, and the source end of the thirteenth NMOS tube NM13 is coupled with the second latch amplification unit.

[0153] Please continue to see Figure 3 In an embodiment of the present application, the comparator further includes a first bias circuit 25.

[0154] The first bias circuit 25 has a control end, a first conduction end and a second conduction end. The control end of the first bias circuit 25 is used to receive a preset bias voltage vbias. The first conduction end of the first bias circuit is coupled with the power supply voltage avdd, and the second conduction end of the first bias circuit is coupled with the input stage circuit 21. The first bias circuit 25 can provide a bias current for the input stage circuit 21.

[0155] Specifically, the first bias circuit 25 includes a seventh PMOS transistor PM7. The gate terminal of the seventh PMOS transistor PM7 is coupled to or serves as the control terminal of the first bias circuit 25, and is configured to receive the bias voltage Vbias. The source terminal of the seventh PMOS transistor PM7 is coupled to or serves as the first conduction terminal of the first bias circuit 25, and is coupled to the power supply voltage avdd. The drain terminal of the seventh PMOS transistor PM7 is coupled to the input stage circuit 21.

[0156] Please continue to see Figure 4 In an embodiment of the present application, the comparator further includes a second bias circuit 26.

[0157] The second bias circuit 26 has a control terminal, a first conduction terminal and a second conduction terminal. The control terminal of the second bias circuit 26 is configured to receive the bias voltage Vbias. The first conduction terminal of the second bias circuit 26 is coupled to the power supply voltage avdd. The second conduction terminal of the second bias circuit 26 is coupled to the noise shaping input stage circuit 22. The second bias circuit 26 can provide a bias current for the noise shaping input stage circuit 22.

[0158] Specifically, the second bias circuit 26 includes an eighth PMOS transistor PM8. The gate terminal of the eighth PMOS transistor PM8 is coupled to the bias voltage Vbias. The source terminal of the eighth PMOS transistor PM8 is coupled to the power supply voltage avdd. The drain terminal of the eighth PMOS transistor PM8 is coupled to the noise shaping input stage circuit 23.

[0159] Please continue to see Figure 6 In another embodiment of the present application, the comparator further includes a first output reset circuit 27.

[0160] The first output reset circuit 27 has a control terminal, a first conduction terminal and a second conduction terminal. The control terminal of the first output reset circuit 27 is configured to receive the first clock control signal clk1. The first conduction terminal of the first output reset circuit 27 is coupled to the power supply voltage avdd. The second conduction terminal of the first output reset circuit 27 is coupled to the positive output terminal of the comparator. The first output reset circuit 27 can reset the positive output terminal of the comparator to the power supply voltage avdd during the sampling phase.

[0161] Specifically, the first output reset circuit 27 includes a ninth PMOS transistor PM9. The gate of the ninth PMOS transistor PM9 is configured to receive the first clock control signal clk1, the source of the ninth PMOS transistor PM9 is coupled to the power supply voltage avdd, and the drain of the ninth PMOS transistor PM9 is coupled to the non-inverting output of the comparator.

[0162] Please continue to see Figure 6 In another embodiment of the present application, the comparator further includes a second output reset circuit 28.

[0163] The second output reset circuit 28 has a control terminal, a first conduction terminal and a second conduction terminal. The control terminal of the second output reset circuit 28 is configured to receive the first clock control signal clk1, the first conduction terminal of the second output reset circuit 28 is coupled to the power supply voltage avdd, and the second conduction terminal of the second output reset circuit 28 is coupled to the inverting output of the comparator. The second output reset circuit 28 can reset the inverting output of the comparator to the power supply voltage avdd during the sampling phase.

[0164] Specifically, the second output reset circuit 28 includes a tenth PMOS transistor PM10. The gate of the tenth PMOS transistor PM10 is configured to receive the first clock control signal clk1, the source of the tenth PMOS transistor PM10 is coupled to the power supply voltage avdd, and the drain of the tenth PMOS transistor PM10 is coupled to the inverting output of the comparator.

[0165] Please continue to see Figure 3 In yet another embodiment of the present application, the comparator further includes a first input stage reset circuit 29 and a second input stage reset circuit 30. Wherein:

[0166] The first input stage reset circuit 29 has a control terminal, a first conduction terminal and a second conduction terminal. The control terminal of the first input stage reset circuit 29 is configured to receive a preset second clock control signal clk2, the first conduction terminal of the first input stage reset circuit 29 is configured to receive a common mode voltage vcm, and the second conduction terminal of the first input stage reset circuit 29 is coupled to the first input terminal of the input stage circuit. The first input stage reset circuit 29 can reset the first input terminal of the input stage circuit to the common mode voltage vcm during the sampling phase.

[0167] Specifically, the first input stage reset circuit 29 comprises a first switch S1. The control end of the first switch S1 is configured to receive the second clock control signal clk2. The first conduction end of the first switch S1 is configured to receive the common-mode voltage vcm. The second conduction end of the first switch S1 is coupled to the first input end of the input stage circuit 21.

[0168] The second input stage reset circuit 30 has a control end, a first conduction end, and a second conduction end. The control end of the second input stage reset circuit 30 is configured to receive the second clock control signal clk2. The first conduction end of the second input stage reset circuit 30 is configured to receive the common-mode voltage vcm. The second conduction end of the second input stage reset circuit 30 is coupled to the second input end of the input stage circuit 21. The second input stage reset circuit 30 can reset the second input end of the input stage circuit 21 to the common-mode voltage vcm at the sampling phase.

[0169] Specifically, the second input stage reset circuit 30 comprises a second switch S2. The control end of the second switch S2 is configured to receive the second clock control signal clk2. The first conduction end of the second switch S2 is configured to receive the common-mode voltage vcm. The second conduction end of the second switch S2 is coupled to the second input end of the input stage circuit 21.

[0170] Please continue to see Figure 4 In another embodiment of the present application, the comparator further comprises a first noise shaping input stage reset circuit 31 and a second noise shaping input stage reset circuit 32. Wherein:

[0171] The first noise shaping input stage reset circuit 31 has a control end, a first conduction end, and a second conduction end. The control end of the first noise shaping input stage reset circuit 31 is configured to receive the second clock control signal clk2. The first conduction end of the first noise shaping input stage reset circuit 31 is configured to receive the common-mode voltage vcm. The second conduction end of the first noise shaping input stage reset circuit 31 is coupled to the first input end of the noise shaping input stage circuit 22. The first noise shaping input stage reset circuit 31 can reset the first input end of the noise shaping input stage circuit 22 to the common-mode voltage vcm at the sampling phase.

[0172] Specifically, the first noise shaping input stage reset circuit 31 comprises a third switch S3. The control end of the third switch S3 is configured to receive the second clock control signal clk2. The first conduction end of the third switch S3 is configured to receive the common-mode voltage vcm. The second conduction end of the third switch S3 is coupled to the first input end of the noise shaping input stage circuit 22.

[0173] The second noise shaping input stage reset circuit 32 has a control end, a first conduction end and a second conduction end. The control end of the second noise shaping input stage reset circuit 32 is configured to receive the second clock control signal clk2, the first conduction end of the second noise shaping input stage reset circuit 32 is configured to receive the common-mode voltage vcm, and the second conduction end of the second noise shaping input stage reset circuit 32 is coupled to the second input end of the noise shaping input stage circuit 22. The second noise shaping input stage reset circuit 32 can reset the second input end of the noise shaping input stage circuit 22 to the common-mode voltage vcm during the sampling phase.

[0174] Specifically, the second noise shaping input stage reset circuit 32 includes a fourth switch S4. The control end of the fourth switch S4 is configured to receive the second clock control signal clk2, the first conduction end of the fourth switch S4 is configured to receive the common-mode voltage vcm, and the second conduction end of the fourth switch S4 is coupled to the first input end of the noise shaping input stage circuit.

[0175] Please continue to see Figure 6 In another embodiment of the present application, the comparator further includes a first latch stage reset circuit 33 and a second latch stage reset circuit 34. Wherein:

[0176] The first latch stage reset circuit 33 has a control end, a first conduction end and a second conduction end. The control end of the first latch stage reset circuit 33 is configured to receive the second clock control signal clk2, the first conduction end of the first latch stage reset circuit 33 is configured to receive the common-mode voltage vcm, and the second conduction end of the first latch stage reset circuit 33 is coupled to the first input end of the latch stage circuit 24. The first latch stage reset circuit 33 can reset the first input end of the latch stage circuit 24 to the common-mode voltage vcm during the sampling phase.

[0177] Specifically, the first latch stage reset circuit 33 includes a fifth switch S5. The control end of the fifth switch S5 is configured to receive the second clock control signal clk2, the first conduction end of the fifth switch S5 is configured to receive the common-mode voltage vcm, and the second conduction end of the fifth switch S5 is coupled to the first input end of the noise shaping input stage circuit 22.

[0178] The second latch stage reset circuit 34 has a control end, a first conduction end and a second conduction end. The control end of the second latch stage reset circuit 34 is configured to receive the second clock control signal clk2, the first conduction end of the second latch stage reset circuit 34 is configured to receive the common-mode voltage vcm, and the second conduction end of the second latch stage reset circuit 34 is coupled to the second input end of the latch stage circuit 24. The second latch stage reset circuit 34 can reset the second input end of the latch stage circuit 24 to the common-mode voltage vcm at the sampling phase.

[0179] Specifically, the second latch stage reset circuit 34 includes a sixth switch S6. The control end of the sixth switch S6 is configured to receive the second clock control signal clk2, the first conduction end of the sixth switch S6 is configured to receive the common-mode voltage vcm, and the second conduction end of the sixth switch S6 is coupled to the first input end of the latch stage circuit 24.

[0180] The structure of the comparator in the embodiment of the application is described above, and the working method of the comparator in the embodiment of the application will be introduced below.

[0181] Please refer to Figure 7 , and combine Figures 2 to 6 When the second clock control signal clk2 is at a high level, the comparator is at the sampling phase.

[0182] At this time, the first output reset circuit 27 and the second output reset circuit 28 reset the non-inverting output end and the inverting output end of the comparator to the power supply voltage avdd under the control of the first clock control signal clk1.

[0183] Specifically, the first clock control signal clk1 is at a logic low level, the ninth PMOS tube PM9 and the tenth PMOS tube PM10 are both turned on, and the power supply voltage avdd is transmitted to the non-inverting output end and the inverting output end of the comparator through the ninth PMOS tube PM9 and the tenth PMOS tube PM10, so as to pull up the non-inverting output end and the inverting output end of the comparator to the power supply voltage avdd.

[0184] At the same time, the first input stage reset circuit 29, the second input stage reset circuit 30, the third noise shaping input stage reset circuit 31, the second noise shaping input stage reset circuit 32, the first latch stage reset circuit 33 and the second latch stage reset circuit 34 reset the first input end and the second input end of the input stage circuit 21 and the first input end and the second input end of the noise shaping input stage circuit 22 and the first input end and the second input end of the latch stage circuit 24 to the common-mode voltage vcm, respectively.

[0185] Specifically, when the second clock control signal clk2 is high, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5 and the sixth switch S6 are all turned on, and the common mode voltage vcm is transmitted to the first input terminal and the second input terminal of the input stage circuit 21, the first input terminal and the second input terminal of the noise shaping input stage circuit 22 and the first input terminal and the second input terminal of the latch stage circuit 24, so as to reset the first input terminal and the second input terminal of the input stage circuit 21, the first input terminal and the second input terminal of the noise shaping input stage circuit 22 and the first input terminal and the second input terminal of the latch stage circuit 24 to the common mode voltage vcm respectively.

[0186] After that, when the second clock control signal CLK2 is low, the comparator is in the comparison phase.

[0187] At this time, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5 and the sixth switch S6 are all turned off, and the common mode voltage vcm is disconnected with the first input terminal and the second input terminal of the input stage circuit 21, the first input terminal and the second input terminal of the noise shaping input stage circuit 22 and the first input terminal and the second input terminal of the latch stage circuit 24.

[0188] At the same time, the first input signal Inp and the second input signal Inn are input to the comparator through the first input terminal and the second input terminal of the input stage circuit 21 respectively, and the third input signal Inp-ns and the fourth input signal Inn-ns are input to the comparator through the first input terminal and the second input terminal of the noise shaping input stage circuit 22 respectively.

[0189] When the falling edge of the first clock control signal clk1 comes, the first input signal Inp, the second input signal Inn and the third input signal Inp-ns and the fourth input signal Inn-ns reach a stable state after half a period of logic low voltage time in the sampling phase.

[0190] In this process, the input stage circuit 21 amplifies the first input signal Inp and the second input signal Inn respectively to generate the first output signal Inp-out and the second output signal Inn-out.

[0191] When the first input signal Inp is greater than the second input signal Inn, the voltage difference between the gate and source of the first PMOS PM1 in the first input amplification unit will be less than the voltage difference between the gate and source of the second PMOS PM2 in the second input amplification unit, so the conduction current of the first PMOS PM1 is less than that of the second PMOS PM2, thereby the charging speed of the drain of the first PMOS PM1 is slower than that of the first PMOS PM2, and then the voltage of the drain of the first PMOS PM1 is less than that of the second PMOS PM2, that is, the voltage of the first latch node N1 is less than that of the second latch node N2. Meanwhile, the existence of the first NMOS NM1 and the second NMOS NM2 in the first latch unit will make the voltage of the first latch node N1 maintain in the state of being less than the voltage of the second latch node N2. Conversely, when the first input signal Inp is less than the second input signal Inn, the voltage of the first latch node N1 is greater than that of the second latch node N2.

[0192] Similarly, the noise shaping input stage circuit 22 amplifies the third input signal Inp-ns and the fourth input signal Inn-ns respectively to generate the corresponding third output signal Inp-ns-out and the fourth output signal Inn-ns-out respectively.

[0193] Specifically, when the third input signal Inp-ns is greater than the fourth input signal Inn-ns, the voltage difference between the gate and source of the third PMOS PM3 in the first noise shaping amplification unit will be less than the voltage difference between the gate and source of the fourth PMOS PM4 in the second noise shaping amplification unit, so the conduction current of the third PMOS PM3 is less than that of the fourth PMOS PM4, thereby the pull-up speed of the drain of the third PMOS PM3 is slower than that of the fourth PMOS PM4, and then the voltage of the drain of the third PMOS PM3 is less than that of the fourth PMOS PM4, that is, the voltage of the third latch node N3 is less than that of the fourth latch node N4. Meanwhile, the existence of the third NMOS NM3 and the fourth NMOS NM4 in the second latch unit will make the voltage of the third latch node N3 maintain in the state of being less than the voltage of the fourth latch node N4. Conversely, when the third input signal Inp-ns is less than the fourth input signal Inn-ns, the voltage of the third latch node N3 is greater than that of the fourth latch node N4.

[0194] The first output signal Inp-out and the second output signal Inn-out outputted by the input stage circuit 21, and the third output signal Inp-ns-out and the fourth output signal Inn-ns-out outputted by the noise shaping input stage circuit 23, are transmitted to the first input terminal and the second input terminal of the latch stage circuit 24 respectively after being noise-isolated by the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 in the isolation transmission circuit 23.

[0195] Specifically, when the first differential input voltage Inp is greater than the second differential input voltage Inn, and the third differential input voltage Inp-ns is greater than the fourth differential input voltage Inn-ns, the voltage of the first latch node N1 is less than the voltage of the second latch node N2, and the voltage of the third latch node N3 is less than the voltage of the fourth latch node N4, the relationship between the voltages inputted to the first input terminal and the second input terminal of the latch stage circuit 24 can be equivalent to the relationship between the sum of the first differential input voltage Inp and the third differential input voltage Inp-ns and the sum of the second differential input voltage Inn and the fourth differential input voltage Inn-ns, i.e. the voltage of the node N5 is less than the voltage of the node N6. Conversely, when the first differential input voltage Inp is less than the second differential input voltage Inn, and the third differential input voltage Inp-ns is less than the fourth differential input voltage Inn-ns, the voltage of the node N5 will be greater than the voltage of the node N6.

[0196] Subsequently, when the rising edge of the first clock control signal clk1 arrives, the latch stage circuit 24 compares the voltages received by its first input terminal and second input terminal, i.e. compares the voltages of the node N5 and the node N6.

[0197] Specifically, when the first clock control signal clk1 is high, the ninth NMOS transistor NM9 in the switch unit of the latch stage circuit 24 is turned on. When the ninth NMOS transistor NM9 is turned on, the source end of the ninth NMOS transistor NM9 is connected to the ground voltage avss, and the gate end of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 is connected to the power supply voltage avdd before the comparator is in the sampling phase. Therefore, when the voltage of the node N5 is less than the voltage of the node N6, i.e., the voltage received by the first input end of the latch stage circuit 24 is less than the voltage received by the second input end, the drain end of the tenth NMOS transistor NM10 is pulled down to the ground voltage avss by the ninth NMOS transistor NM9 before the drain end of the eleventh NMOS transistor NM11, so that the voltage difference between the gate end and the source end of the twelfth NMOS transistor NM12 is greater than the voltage difference between the gate end and the source end of the thirteenth NMOS transistor NM13, and then the gate end of the twelfth NMOS transistor NM12 is greater than the gate end of the thirteenth NMOS transistor NM13, i.e., the voltage outp of the positive phase output end of the comparator is greater than the voltage outn of the inverting output end. Conversely, when the voltage received by the first input end of the latch stage circuit 24 is greater than the voltage received by the second input end, i.e., the voltage of the node N5 is greater than the voltage of the node N6, the voltage outp of the positive phase output end of the comparator is less than the voltage outn of the inverting output end.

[0198] Meanwhile, the cross-coupled positive feedback structure composed of the fifth PMOS transistor PM5, the twelfth NMOS transistor NM12, the sixth PMOS transistor PM6 and the thirteenth NMOS transistor NM13 in the third latch unit makes the voltage outp of the positive phase output end of the comparator maintain in a state greater than or less than the voltage outn of the inverting output end of the comparator.

[0199] In one aspect, due to the existence of the isolation transmission circuit 23, the first output signal Inp-out and the second output signal Inn-out outputted by the first output end and the second output end of the input stage circuit 21 are coupled to the first input end and the second input end of the latch stage circuit 24 through the first capacitor C1 and the second capacitor C2 respectively, and the third output signal Inp-ns-out and the fourth output signal Inn-ns-out outputted by the first output end and the second output end of the noise shaping input stage circuit 22 are coupled to the first input end and the second input end of the latch stage circuit 24 through the third capacitor C3 and the fourth capacitor C4 respectively, so that the output ends of the input stage circuit 21 and the noise shaping input stage circuit 22 are independent of each other. Therefore, when the first output end and the second output end of the input stage circuit 21 and the first output end and the second output end of the noise shaping input stage circuit 22 are directly connected to the first input end and the second input end of the latch stage circuit 24, the coupling effect on the input stage circuit 21 and the noise shaping input stage circuit 22 caused by the change of the output voltage of the non-inverting output end and the inverting output end of the latch stage from the power supply voltage avdd in the sampling phase to outp and outn in the comparison phase can be avoided, so that the isolation and kickback noise reduction effects can be achieved.

[0200] In another aspect, when the comparator is in the sampling phase, the input offset voltage of the comparator is stored on the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 in the isolation transmission circuit 23 after being amplified by the input stage circuit 21 and the noise shaping input stage circuit. At this time, the stored voltage on the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 is equivalent to the output offset voltage of the comparator, denoted as (Av*Voffset), wherein Av represents the gain of the input stage circuit or the noise shaping input stage circuit, and Voffset represents the input offset voltage. Then, when the comparator is in the comparison phase, i.e., the second clock control signal clk2 is low, the first input signal Inp and the second input signal Inn and the third input signal Inp-ns and the fourth output signal Inn-ns are connected to the input stage circuit 21 and the noise shaping input stage circuit 22 respectively, and the output voltage is denoted as (Av*(VIn+Voffset)) after being amplified by the input stage circuit 21 and the noise shaping input stage circuit 22. Before being transmitted to the latch stage circuit 24, the input offset voltage (Av*Voffset) in the output voltage (Av*(VIn+Voffset)) is offset by the output offset voltage (Av*Voffset) stored on the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 in the isolation transmission circuit 23 respectively, and the output value becomes (Av*VIn), so that the offset voltage can be eliminated, and the precision of the comparator in the embodiment of the present application can be improved.

[0201] In addition, the seventh PMOS PM7 in the first bias circuit and the eighth PMOS PM8 in the second bias circuit provide bias currents for the input stage circuit 21 and the noise shaping input stage circuit 22 respectively, so that the noise generated when the input signal is connected instantaneously can be avoided, and thus the performance of the comparator in the embodiment of the application can be improved.

[0202] Correspondingly, the embodiment of the application further provides a successive approximation analog-to-digital converter comprising the comparator. Details of the comparator are described in the foregoing part, and thus will not be described herein.

[0203] The above-described embodiments of the application are combinations of elements and features of the application. Unless otherwise mentioned, the elements or features can be considered selective. Each element or feature can be practiced without being combined with other elements or features. In addition, embodiments of the application can be constructed by combining some elements and / or features. The order of the operations described in the embodiments of the application can be rearranged. Some configurations of any embodiment can be included in another embodiment, and can be replaced with corresponding configurations of another embodiment. It is obvious to those skilled in the art that the claims which have no explicit citation relationship with each other in the appended claims can be combined into embodiments of the application, or can be included as new claims in the amendment after the submission of the application.

[0204] Embodiments of the application can be realized by various means, for example, hardware, firmware, software, or a combination thereof. In a hardware configuration, the method according to the exemplary embodiments of the application can be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, or the like.

[0205] In a firmware or software configuration, the embodiments of the application can be implemented in the form of modules, procedures, functions, and the like. Software code can be stored in a memory unit and executed by a processor. The memory unit is located at the interior or exterior of the processor and can deliver data to and receive data from the processor via various means.

[0206] The above description of disclosed embodiments of the application allows a person skilled in the art to implement or use the application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the application will not be limited to the embodiments shown herein, but is consistent with the widest scope consistent with the principles and novel features disclosed herein.

[0207] Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. It will be apparent to those skilled in the art that various modifications and changes can be made thereto without departing from the spirit and scope of the application. The scope of the application should be limited only by the appended claims.

Claims

1. A comparator having a sampling phase and a comparison phase, characterized in that, The input stage circuit is adapted to amplify the received first input signal and second input signal respectively to generate corresponding first output signal and second output signal and transmit to the isolation transmission circuit during the comparison phase. The noise shaping input stage circuit is adapted to amplify the received third input signal and fourth input signal respectively to generate corresponding third output signal and fourth output signal and transmit to the isolation transmission circuit during the comparison phase. The isolation transmission circuit is adapted to isolate the received first output signal, second output signal, third output signal and fourth output signal respectively to generate first noise isolation signal, second noise isolation signal, third noise isolation signal and fourth noise isolation signal and input to the latch stage circuit during the comparison phase. The latch stage circuit is adapted to compare the first superimposed level signal of the received first noise isolation signal and third noise isolation signal with the second superimposed level signal of the second noise isolation signal and fourth noise isolation signal to generate corresponding comparison result and output. The input stage circuit comprises a first input amplification unit and a second input amplification unit.

2. The comparator of claim 1, wherein, The first input amplification unit is adapted to amplify the first input signal to generate the first output signal. The second input amplification unit is adapted to amplify the second input signal to generate the second output signal. The first input amplification unit comprises a first PMOS transistor.

3. The comparator of claim 2, wherein, The gate terminal of the first PMOS transistor is used to receive the first input signal, the source terminal of the first PMOS transistor is coupled with a power supply voltage, and the drain terminal of the first PMOS transistor is used as or coupled with the first output terminal of the input stage circuit. The second input amplification unit comprises a second PMOS transistor.

4. The comparator of claim 2, wherein, The gate terminal of the second PMOS transistor is used to receive the second input signal, the source terminal of the second PMOS transistor is coupled with a power supply voltage, and the drain terminal of the second PMOS transistor is used as or coupled with the second output terminal of the input stage circuit. The input stage circuit further comprises:

5. Comparator according to any one of claims 2 to 4, characterized in that A first latch unit having a first latch node and a second latch node, and adapted to latch the first output signal and the second output signal to the first latch node and the second latch node respectively and input to the isolation transmission circuit. The first latch unit comprises a first NMOS transistor and a second NMOS transistor.

6. The comparator of claim 5, wherein, The gate terminal of the first NMOS transistor is coupled with the drain terminal of the second NMOS transistor and used as or coupled with the second latch node, the source terminal of the first NMOS transistor is coupled with the source terminal of the second NMOS transistor and with a ground voltage, the drain terminal of the first NMOS transistor is coupled with the gate terminal of the second NMOS transistor and used as or coupled with the first latch node. The input stage circuit further comprises a first gain improvement unit and a second gain improvement unit.

7. The comparator of claim 2, wherein, The first gain improvement unit is adapted to improve the output gain of the first input amplification unit. The second gain improvement unit is adapted to improve the output gain of the second input amplification unit. The second gain improving unit is adapted to improve the output gain of the second input amplifying unit.

8. The comparator of claim 7, wherein, The first gain improving unit comprises a third NMOS transistor; The gate terminal and the drain terminal of the third NMOS transistor are coupled and connected to the output terminal of the first input amplifying unit, and the source terminal of the third NMOS transistor is coupled to the ground voltage.

9. The comparator of claim 7, wherein, The second gain improving unit comprises a fourth NMOS transistor; The gate terminal and the drain terminal of the fourth NMOS transistor are coupled and connected to the output terminal of the second input amplifying unit, and the source terminal of the fourth NMOS transistor is coupled to the ground voltage.

10. The comparator of claim 1, wherein, The noise shaping input stage circuit comprises a first noise shaping amplifying unit and a second noise shaping amplifying unit; The first noise shaping amplifying unit is adapted to amplify the received third input signal to generate the third output signal; The second noise shaping amplifying unit is adapted to amplify the received fourth input signal to generate the fourth output signal.

11. The comparator of claim 10, wherein, The first noise shaping amplifying unit comprises a third PMOS transistor; The gate terminal of the third PMOS transistor is used to receive the third input signal, the source terminal of the third PMOS transistor is coupled to the power supply voltage, and the drain terminal of the third PMOS transistor is used as or coupled to the first output terminal of the noise shaping amplifying unit.

12. The comparator of claim 10, wherein, The second noise shaping amplifying unit comprises a fourth PMOS transistor; The gate terminal of the fourth PMOS transistor is used to receive the fourth input signal, the source terminal of the fourth PMOS transistor is coupled to the power supply voltage, and the drain terminal of the fourth PMOS transistor is used as or coupled to the second output terminal of the noise shaping amplifying unit.

13. Comparator according to any one of claims 10 to 12, characterized in that The noise shaping input stage circuit further comprises: A second latch unit having a third latch node and a fourth latch node, and adapted to latch the third output signal and the fourth output signal to the third latch node and the fourth latch node respectively and input to the isolation transmission circuit.

14. The comparator of claim 13, wherein, The second latch unit comprises a fifth NMOS transistor and a sixth NMOS transistor; The gate terminal of the fifth NMOS transistor is coupled to the drain terminal of the sixth NMOS transistor, and is used as or coupled to the fourth latch node, the source terminal of the fifth NMOS transistor and the source terminal of the sixth NMOS transistor are both coupled to the ground voltage, the drain terminal of the fifth NMOS transistor is coupled to the gate terminal of the sixth NMOS transistor, and is used as or coupled to the third latch node.

15. The comparator of claim 13, wherein, The noise shaping input stage further comprises a third gain improving unit and a fourth gain improving unit; The third gain improving unit is adapted to improve the output gain of the first noise shaping amplifying unit; The fourth gain improving unit is adapted to improve the output gain of the second noise shaping amplifying unit.

16. The comparator of claim 15, wherein, The third gain improving unit comprises a seventh NMOS transistor; The gate terminal and the drain terminal of the seventh NMOS transistor are coupled and connected to the output terminal of the first noise shaping amplifying unit, and the source terminal of the seventh NMOS transistor is coupled to the ground voltage.

17. The comparator of claim 15, wherein, The fourth gain improving unit comprises an eighth NMOS transistor; The gate end of the eighth NMOS tube is coupled with the drain end and the output end of the second noise shaping amplification unit, and the source end of the eighth NMOS tube is coupled with the ground voltage.

18. The comparator of claim 1, wherein, The isolation transmission circuit comprises a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; The first end of the first capacitor is coupled with the first output end of the input stage circuit, and the second end of the first capacitor is coupled with the first input end of the latch stage circuit; The first end of the second capacitor is coupled with the second output end of the input stage circuit, and the second end of the second capacitor is coupled with the second input end of the latch stage circuit; The first end of the third capacitor is coupled with the first output end of the noise shaping input stage circuit, and the second end of the third capacitor is coupled with the first input end of the latch stage circuit; The first end of the fourth capacitor is coupled with the second output end of the noise shaping input stage circuit, and the second end of the fourth capacitor is coupled with the second input end of the latch stage circuit.

19. The comparator of claim 18, wherein, The latch stage circuit comprises a switch unit, a first latch amplification unit, a second latch amplification unit and a third latch unit; The switch unit is adapted to be turned on during the comparison phase. The first latch amplification unit is adapted to amplify the first superimposed level signal of the first output signal and the third output signal when the switch unit is turned on. The second latch amplification unit is adapted to amplify the second superimposed level signal of the received second output signal and the fourth output signal when the switch unit is turned on. The third latch unit is adapted to latch and compare the amplified first superimposed level signal and the amplified second superimposed level signal, and output the corresponding comparison result.

20. The comparator of claim 19, wherein, The switch unit comprises a ninth NMOS tube. The gate end of the ninth NMOS tube is used to receive a first clock control signal, the source end of the ninth NMOS tube is coupled with the ground voltage, and the drain end of the ninth NMOS tube is coupled with the first latch amplification unit and the second latch amplification unit, respectively.

21. The comparator of claim 19, wherein, The first latch amplification unit comprises a tenth NMOS tube. The gate end of the tenth NMOS tube serves as or is coupled with the first input end of the latch stage circuit, the source end of the tenth NMOS tube is coupled with the switch unit, and the drain end of the tenth NMOS tube is coupled with the third latch unit.

22. The comparator of claim 19, wherein, The second latch amplification unit comprises an eleventh NMOS tube. The gate end of the eleventh NMOS tube serves as or is coupled with the second input end of the latch stage circuit, the source end of the eleventh NMOS tube is coupled with the switch unit, and the drain end of the eleventh NMOS tube is coupled with the third latch unit.

23. The comparator of claim 19, wherein, The third latch unit comprises a fifth PMOS tube, a twelfth NMOS tube, a sixth PMOS tube and a thirteenth NMOS tube. a gate terminal of the fifth PMOS transistor is coupled with a gate terminal of the twelfth NMOS transistor and coupled with a drain terminal of a sixth PMOS transistor and a drain terminal of a thirteenth NMOS transistor, and serves as or is coupled with an inverting output terminal of the comparator, a drain terminal of the fifth PMOS transistor is coupled with a drain terminal of the twelfth NMOS transistor and coupled with a gate terminal of the sixth PMOS transistor and a gate terminal of the thirteenth NMOS transistor, and serves as or is coupled with a non-inverting output terminal of the comparator, a source terminal of the fifth PMOS transistor and a source terminal of the sixth PMOS transistor are coupled with a power supply voltage, a source terminal of the twelfth NMOS transistor is coupled with the first latch amplifier unit, and a source terminal of the thirteenth NMOS transistor is coupled with the second latch amplifier unit.

24. The comparator of claim 1, wherein, Further comprising at least one of: a first biasing circuit adapted to provide a bias current for the input stage circuit; a second biasing circuit adapted to provide a bias current for the noise shaping input stage circuit.

25. The comparator of claim 24, wherein, the first biasing circuit comprises a seventh PMOS transistor; a gate terminal of the seventh PMOS transistor is coupled with a bias voltage, a source terminal of the seventh PMOS transistor is coupled with a power supply voltage, and a drain terminal of the seventh PMOS transistor is coupled with the input stage circuit.

26. The comparator of claim 24, wherein, the second biasing circuit comprises an eighth PMOS transistor; a gate terminal of the eighth PMOS transistor is coupled with a bias voltage, a source terminal of the eighth PMOS transistor is coupled with a power supply voltage, and a drain terminal of the eighth PMOS transistor is coupled with the noise shaping input stage circuit.

27. The comparator of claim 1, wherein, Further comprising at least one of: a first output reset circuit adapted to reset a potential of the non-inverting output terminal of the comparator to the power supply voltage at the sampling phase; a second output reset circuit adapted to reset a potential of the inverting output terminal of the comparator to the power supply voltage at the sampling phase.

28. The comparator of claim 27, wherein, the first output reset circuit comprises a ninth PMOS transistor; a gate terminal of the ninth PMOS transistor is configured to receive a first clock control signal, a source terminal of the ninth PMOS transistor is coupled with a power supply voltage, and a drain terminal of the ninth PMOS transistor is coupled with the non-inverting output terminal of the comparator.

29. The comparator of claim 27, wherein, the second output reset circuit comprises a tenth PMOS transistor; a gate terminal of the tenth PMOS transistor is configured to receive the first clock control signal, a source terminal of the tenth PMOS transistor is coupled with a power supply voltage, and a drain terminal of the tenth PMOS transistor is coupled with the inverting output terminal of the comparator.

30. The comparator of claim 1, wherein, Further comprising at least one of: a first input reset circuit adapted to reset a potential of a first input terminal of the input stage circuit to a preset common mode voltage at the sampling phase; a second input reset circuit adapted to reset a potential of a second input terminal of the input stage circuit to the common mode voltage at the sampling phase; a third input reset circuit adapted to reset a potential of a first input terminal of the noise shaping input stage circuit to the common mode voltage at the sampling phase; a fourth input reset circuit adapted to reset a potential of a second input terminal of the noise shaping input stage circuit to the common mode voltage at the sampling phase; a fifth input reset circuit adapted to reset the potential of the first input terminal of the latch stage circuit to the common mode voltage at the sampling phase; a sixth input reset circuit adapted to reset the potential of the second input terminal of the latch stage circuit to the common mode voltage at the sampling phase.

31. The comparator of claim 30, wherein, The first input reset circuit comprises a first switch; a control terminal of the first switch is configured to receive a second clock control signal, a first conduction terminal of the first switch is configured to receive the common mode voltage, and a second conduction terminal of the first switch is coupled to the first input terminal of the input stage circuit.

32. The comparator of claim 30, wherein, The second input reset circuit comprises a second switch; a control terminal of the second switch is configured to receive the second clock control signal, a first conduction terminal of the second switch is configured to receive the common mode voltage, and a second conduction terminal of the second switch is coupled to the second input terminal of the input stage circuit.

33. The comparator of claim 30, wherein, The third input reset circuit comprises a third switch; a control terminal of the third switch is configured to receive the second clock control signal, a first conduction terminal of the third switch is configured to receive the common mode voltage, and a second conduction terminal of the third switch is coupled to the first input terminal of the noise shaping input stage circuit.

34. The comparator of claim 30, wherein, The fourth input reset circuit comprises a fourth switch; a control terminal of the fourth switch is configured to receive the second clock control signal, a first conduction terminal of the fourth switch is configured to receive the common mode voltage, and a second conduction terminal of the fourth switch is coupled to the second input terminal of the noise shaping input stage circuit.

35. The comparator of claim 30, wherein, The fifth input reset circuit comprises a fifth switch; a control terminal of the fifth switch is configured to receive the second clock control signal, a first conduction terminal of the fifth switch is configured to receive the common mode voltage, and a second conduction terminal of the fifth switch is coupled to the first input terminal of the latch stage circuit.

36. The comparator of claim 30, wherein, The sixth input reset circuit comprises a sixth switch; a control terminal of the sixth switch is configured to receive the second clock control signal, a first conduction terminal of the sixth switch is configured to receive the common mode voltage, and a second conduction terminal of the sixth switch is coupled to the second input terminal of the latch stage circuit.

37. A successive approximation analog-to-digital converter, comprising: The comparator comprises any one of claims 1-36.

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