Plasma etched catalytic laminate with traces and vias

Abstract

The present application relates to plasma etched catalytic laminates with traces and through holes. The circuit board is formed from a catalytic laminate having a resin-rich surface in which catalytic particles are dispersed below the surface exclusion depth. The catalytic laminate is subjected to drilling and blanket surface plasma etching operations to expose the catalytic particles, followed by an electroless plating operation that deposits a thin layer of conductive material on the surface. A photomask step then defines the circuit traces, after which electroplating deposition occurs, followed by a resist stripping operation and flash etching to remove the electroless copper previously covered by the photoresist.

Description

[0001] This application is a divisional application of an application filed on August 16, 2017, with application number 201780064641.5 and invention name “Plasma Etched Catalytic Laminate with Traces and Through Holes”. Field of the Invention

[0002] The present invention relates to catalytic laminates and their use in circuit board manufacturing. In particular, the laminates have properties that provide fine pitch circuit interconnects that can be formed on the surface of the catalytic laminate or in grooves to form a circuit board layer having a flat surface with embedded surface conductors or having surface conductors. Background of the Invention

[0003] Prior art printed circuit boards (PCBs) are formed using conductive metal interconnects (referred to as "traces") formed on a dielectric substrate, where each surface carrying a conductor is referred to as a "layer". Each dielectric core has traces formed on one surface or on both surfaces, and by stacking several such dielectric cores (having traces formed therein interspersed with bare dielectric layers) and laminating them together under temperature and pressure, a multilayer printed circuit can be formed. The dielectric substrate comprises an epoxy resin embedded in a fiber matrix (such as fiberglass woven into a cloth). In one prior art manufacturing method, copper is laminated onto the outer surface of the dielectric layer, the copper surface is patterned (such as with a photoresist or photosensitive film) to produce masked and unmasked areas, and then etched to form a conductive trace layer on one or both sides of the core dielectric. The stack of dielectric cores with conductive traces can then be laminated together to form a multilayer board and any layer interconnects made with through-holes, which are drilled holes that are plated with copper to form an annular ring that provides a connection from one layer to another.

[0004] Printed circuit boards (PCBs) are commonly used to provide conductive traces between various electronic components mounted on the PCB. A through-hole device that mounts one type of electronic component on a PCB is one that positions the leads to pass through one or more holes in the PCB, wherein the PCB holes include conductive annular ring pads on each trace connection layer, and the component leads are soldered to the annular ring pads of the PCB holes. Through-hole components have leads that are often difficult to align with the associated PCB mounting holes, but surface mount technology (SMT) provides a preferred mounting system, wherein the component leads are simply placed on the surface of the PCB pads and soldered, which is preferred for PCB assembly due to higher density and ease of mechanized assembly. Surface mount components only require surface mount pads on the outer finished PCB layer. In a two-layer or multi-layer PCB, through-holes are used to achieve interconnection of conductive traces from one layer to another, wherein the conductive traces on one trace layer lead to holes that are usually drilled through one or more dielectric layers of the PCB and plated with copper or other conductive metals to complete the trace layer connection. Holes drilled through all dielectric layers are called thru-vias, holes drilled through only outer layers (usually as part of the fabrication of a separate layer) are called micro-vias, and holes drilled through one or more inner layers are called blind vias. For any of these via types, the via is patterned to include an annular ring conductor area on the opposing trace layer of the PCB, and the drilled hole is lined with a conductive material that connects the annular ring conductor on either side of the laminate or PCB.

[0005] Electroplating can be used to increase the thickness of copper before or after patterning on a printed circuit board laminate, where the PCB or dielectric layer with traces is placed in an electrolytic cell and a DC source is connected between a sacrificial anode conductor (such as a copper rod) and the existing conductive layer of the PCB. In the case where there is no pre-existing conductive copper layer on the PCB that is convenient for electroplating (such as the case of bare dielectric material or drilled through holes), a seed layer of copper must first be deposited. This is done using an electroless plating process, which is chemically plated with the help of a "seed" catalytic material (which enhances the deposition of a specific conductive material) deposited on the surface of the dielectric, and then the board is placed in an electroless plating solution. For a catalyst (such as an electroless plating solution of copper and palladium), copper ions in solution are deposited on the palladium until the surface is fully covered to provide uniform conductivity, and the copper deposited using the electroless plating process thereafter provides a conductive support for the subsequent addition of materials using an electroplating process. Electroplating is preferred for completing the electroplating operation because it has a faster deposition rate than an electroless plating process.

[0006] As electronic assemblies increase in complexity, it is desirable to increase component density on PCB assemblies, such as by using smaller trace widths (referred to as fine pitch traces) in conjunction with increasingly dense integrated circuit (IC) lead patterns. One problem with prior art surface mount PCB manufacturing and assembly methods is that because the traces are formed on the surface of the dielectric, the adhesion between the copper traces and the underlying laminate is reduced for narrower conductor line widths (referred to as fine pitch traces), causing the fine pitch traces and component pads to separate (lift) during component replacement operations, destroying the entire circuit board assembly and the expensive components thereon. Another problem with fine pitch surface traces is that when manufacturing multi-layer circuit boards, the individual trace layers are laminated together under pressure in a high temperature environment. During lamination, the fine pitch traces tend to migrate laterally across the surface of the dielectric. In high speed circuit design, it is desirable to maintain a fixed impedance between traces, especially for differential pair (edge ​​coupled) transmission lines. This lateral migration of the traces during lamination causes the transmission line impedance of the finished PCB differential pair to vary with the length of the traces, which causes kinks and losses in the transmission line compared to a transmission line having a fixed impedance characteristic resulting from a constant spacing.

[0007] It is desirable to form traces using a catalytic prepreg material that provides a blanket etched surface that exposes catalytic particles, followed by a combination of electroless plating to provide a conductive deposit followed by electroless plating to form traces of desired thickness for fine trace line widths and trace separations. It is also desirable to provide a catalytic prepreg for use in printed circuit processing, wherein the catalytic prepreg has a non-catalytic surface, and removal of the surface of the catalytic prepreg exposes catalytic particles that are used to form traces in areas where the surface material has been removed.

[0008] Purpose of the Invention

[0009] A first object of the present invention is a catalytic prepreg containing catalytic particles, wherein the catalytic prepreg hides the catalytic particles beneath a resin-rich outer surface that does not expose the catalytic particles unless the outer surface of the catalytic prepreg has been removed, wherein the surface removal can be accomplished using any of laser cutting, mechanical abrasion, mechanical cutting, chemical or plasma etching, or any other means of removing the outer surface of the prepreg and exposing the underlying catalytic particles beneath the surface of the prepreg, followed by forming traces by drilling and performing a blanket etch on the surface, electroplating the entire surface, patterning the surface with a photoresist, electroplating the surface without a photoresist, stripping the photoresist, and rapidly etching for a sufficient period of time to remove the exposed electroless copper.

[0010] A second object of the present invention is a method for making a catalytic prepreg having a resin-rich outer surface free of exposed catalytic particles and a catalyst-rich layer beneath the resin-rich outer surface, wherein the catalytic prepreg is formed using a method having the following steps:

[0011] a fiber impregnation step in which the fiber cloth is impregnated with a catalytic resin formed by mixing the resin with catalytic particles;

[0012] a vacuum compression step performed at elevated temperature, whereby the outer surface of the fiber cloth impregnated with the catalytic resin is subjected to externally applied pressure in ambient vacuum conditions during a temperature ramp-up time;

[0013] a gel point step whereby an applied pressure is maintained on the outer surface of the fiber cloth impregnated with the catalytic resin to maintain a liquid / solid equilibrium for a duration sufficient to allow the catalytic particles to be drawn away from the outer surface;

[0014] a dwell step, whereby an elevated temperature is applied to the laminate at the gel point temperature for the duration of the dwell time;

[0015] A cooling step, whereby the fiber cloth impregnated with the catalytic resin is cooled into a substantially flat sheet. SUMMARY OF THE INVENTION

[0016] In a first embodiment of the invention, a catalytic prepreg is formed by mixing a resin, a volatile solvent, and catalytic particles to form a catalytic resin mixture, infusing the catalytic resin into a fiber fabric (such as woven glass fiber) or other fabric to form an "A-stage" catalytic prepreg, baking the fibers and resin together at an elevated temperature to remove most of the volatile solvent and form a partially cured "B-stage" catalytic prepreg, such as in the form of a sheet, thereafter placing the B-stage prepreg in a laminator, heating the B-stage prepreg at the gel point so that the prepreg is in liquid / solid equilibrium, thereafter curing the prepreg at elevated temperature and pressure for a residence time sufficient to migrate the catalytic particles away from the outer surface of the prepreg and form a finished "C-stage" prepreg having a resin-rich surface free of exposed surface catalytic particles. The resin-rich surface is mechanically removed to expose the underlying catalytic particles, forming a surface suitable for electroless plating using copper ions in solution or any suitable electroless plating metal ions in solution.

[0017] In a second embodiment of the present invention, a single or multi-layer PCB is formed by patterning an exposed surface onto a catalytic prepreg having a resin-rich surface, the resin-rich surface excluding catalytic particles from the surface, wherein the catalytic particles are distributed below the resin-rich surface and are not exposed. In a first step, the catalytic particles are exposed by removing the surface of the material using any of these techniques with or without a pattern mask using any removal means (including laser ablation, plasma etching, chemical etching, mechanical abrasion or cutting). In a second step, the catalytic laminate is placed in an electroless plating solution, wherein the electroless plated metal (such as Cu) is attracted and bonded to the exposed catalytic particles (such as Pt) in the patterned area where the resin-rich surface has been removed. The second step continues until the electroless plating fills the sides and bottom of the patterned grooves to the level of the surrounding natural surface of the catalytic laminate with the electroplated metal. In an optional third step, the surface of the patterned grooves is planarized such as by polishing, grinding, machining or etching to match the electroless plating level with the surrounding natural surface of the catalytic laminate. In an optional third or fourth step, a solder mask is applied to cover the area of ​​the catalytic laminate and the area of ​​the patterned traces.

[0018] In a third embodiment of the invention, the catalytic prepreg of the first embodiment has a hole formed by drilling or ablation or other means for removing material to form a hole in the catalytic prepreg, the hole being adjacent to the pad area, where the surface of the catalytic prepreg adjacent to the hole is removed, thereby exposing the underlying catalytic particles of the catalytic prepreg in the inner surface of the hole and also the outer surface of the catalytic prepreg, which is then plated into an electroless plating solution. The resulting catalytic prepreg then forms a conductive surface trace electrically connected to the conductive through hole, which can optionally form a component mounting pad. The through hole can also include a conductive surface trace on the opposite side of the catalytic prepreg, wherein the first surface trace, the through hole and the second surface trace are all produced in a single electroless plating step. After electroless plating, the outer surface of the catalytic laminate can be planarized so that the conductive trace is flush with the natural surface of the catalytic laminate, so that the individual layers of the catalytic laminate formed with the traces can be stacked and laminated into a multi-layer PCB.

[0019] In a fourth embodiment of the present invention using a conventional non-catalytic prepreg, a single-layer or multi-layer PCB is formed by a process having a first step of applying a catalytic adhesive to one or both sides of a non-catalytic prepreg, wherein the catalytic adhesive comprises a resin mixed with catalytic particles and forms a catalytic adhesive layer on the non-catalytic prepreg. In a second step, the catalytic prepreg surface layer is selectively partially removed, such as by using a plasma cleaning or plasma etching process for a duration sufficient to expose the catalytic particles while leaving an underlying adhesive resin that fixes the catalytic particles to the non-catalytic prepreg. In a third step, the partially removed or etched catalytic adhesive is exposed to chemical plating using metal ions bound to the catalytic particles in a solution, which is performed until a substantially continuous conductive layer of metal is deposited. In a fourth step, a pattern mask is applied that provides open areas where traces are required. In a fifth step, the continuous conductive layer is used as an electrode for electroplating in a metal plating solution, so that the metal ions in the solution are electrodeposited onto the patterned exposed conductive layer formed in the third step chemical deposition. In a sixth step, the pattern mask is stripped, and in a seventh step, a flash etch is performed long enough to remove the electroless plating in the previously unexposed areas under the pattern mask.

[0020] In a fifth embodiment of the present invention, a conductive via is formed in a non-catalytic laminate by forming a first hole in the non-catalytic laminate (optionally adjacent to a first pad or a second pad formed by a conductor on a first surface or a second surface of the non-catalytic laminate), filling the first hole with a catalytic resin or a catalytic adhesive, allowing the catalytic resin or adhesive to cure, drilling a second hole in the first hole that is smaller in diameter than the hole, and chemically plating the second hole and the surrounding pad to form a connection from the inner surface of the second hole to the first pad or the second pad.

[0021] In a sixth embodiment of the present invention, a non-catalytic laminate layer has a coated catalytic adhesive, the catalytic adhesive comprising a resin and catalytic particles, the catalytic adhesive having a thickness at least twice greater than the largest catalytic particle in the adhesive, the catalytic adhesive curing and developing a resin-rich surface and an exclusion zone below the resin-rich surface, in which the catalytic particles are excluded, the removal of the resin-rich surface providing exposed catalytic particles suitable for chemical plating, the non-catalytic laminate optionally also having holes which can be filled with the catalytic adhesive and drilled to provide exposed catalytic particles for chemical plating of the drilled holes together with conductive traces formed by chemical copper deposition.

[0022] In a seventh embodiment of the present invention, a catalytic laminate has a catalytic adhesive applied to at least one surface, the catalytic laminate includes a prepreg having catalytic particles, the adhesive includes a resin and catalytic particles, the catalytic adhesive and the catalytic laminate are drilled to form through holes, traces are patterned on the surface of the catalytic adhesive by removing a surface layer of the catalytic adhesive, the traces are then formed by chemical plating on the patterned traces, and the at least one surface is then planarized.

[0023] In an eighth embodiment of the present invention, a circuit board is formed by blanket etching a catalytic prepreg to expose catalytic particles below an exclusion depth, drilling through holes, chemically plating the circuit board, patterning the circuit board with a photoresist, electroplating the circuit board to form traces on areas not coated with the photoresist, thereafter removing the photoresist, and rapidly etching the exposed chemically plated copper to form a circuit board having traces.

[0024] This application also provides the following:

[0025] 1) A process for forming conductive traces on a catalytic laminate having a resin-rich surface, the resin-rich surface having catalytic particles of insufficient density for surface electroless plating, the catalytic laminate having catalytic particles dispersed below a catalytic particle exclusion depth sufficient for electroless plating when exposed, the process comprising:

[0026] drilling holes in the catalytic laminate;

[0027] etching an outer surface of the catalytic laminate until the catalytic particles are exposed;

[0028] electrolessly plating the catalytic laminate until a conductive metal is plated on the exterior surface and also within the drilled holes;

[0029] attaching a pattern mask to the outer surface of the catalytic laminate;

[0030] chemically plating the outer surface of the catalytic laminate;

[0031] peeling off the pattern mask;

[0032] The circuit board is etched quickly enough to remove any previously masked electroless conductive metal.

[0033] 2) The process according to 1), wherein the electroless plating and the electroplating deposit copper.

[0034] 3) The process according to 1), wherein the thickness of the electroplating deposition is greater than the thickness of the chemical deposition.

[0035] 4) The process according to 1), wherein the pattern mask is a dry film.

[0036] 5) The process according to 1), wherein the pattern mask is a liquid photoresist.

[0037] 6) The process according to 1), wherein plasma etching the outer surface uses at least one of the following: reactive plasma, chemical etchant, laser cutting, water jet cutting, mechanical abrasion or mechanical cutting.

[0038] 7) The process according to 1), wherein the exclusion depth is less than 25u.

[0039] 8) The catalytic laminate according to 1), wherein the catalytic particles are non-uniform.

[0040] 9) The catalytic laminate according to 8), wherein the catalytic particles include fillers coated with a catalyst.

[0041] 10) The catalytic laminate according to 9), wherein the filler is at least one of the following: a clay mineral, a hydrated aluminosilicate, silica, kaolinite, a polysilicate, a member of the kaolin or china clay group, or a high temperature plastic.

[0042] 11) The catalytic laminate according to 9), wherein the particle size is on the order of 3u or less.

[0043] 12) The catalytic laminate according to 9), wherein the ratio of the catalytic particles to the resin is in the range of 8% to 16% by weight.

[0044] 13) A catalytic laminate according to 9), wherein the catalytic particles are silica or kaolin coated with a catalytic material.

[0045] 14) A catalytic laminate according to 9), wherein the catalyst is palladium.

[0046] 15) A catalytic laminate according to 9), wherein the catalyst is at least one of the following: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) or other compounds or salts thereof.

[0047] 16) The catalytic laminate according to 1), wherein the catalytic particles are uniform.

[0048] 17) A catalytic laminate according to 16), wherein the catalyst is palladium.

[0049] 18) A catalytic laminate according to 16), wherein the catalyst is at least one of the following: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) or other compounds or salts thereof.

[0050] 19) A catalytic laminate according to 16), wherein the majority of the catalytic particles have a size less than 25u. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1A A schematic diagram of the process for forming a pristine catalyzed prepreg is shown.

[0052] Figure 1B A vacuum laminator for forming a finished catalytic prepreg from a raw catalytic prepreg is shown.

[0053] Figure 1C The vacuum lamination stage used to form multiple layers of catalytic prepreg during lamination is shown.

[0054] Figure 2 Shows Figure 1A-Figure 1C The processing time of the vacuum lamination step.

[0055] Figure 3 The process steps for forming a catalyzed prepreg are shown.

[0056] Figure 4 A graph showing the distribution of catalytic particles in a prepreg material versus a cross-sectional view of the prepreg material is shown.

[0057] Figure 5A A cross-section of a native catalyzed prepreg is shown.

[0058] Figure 5B A cross-sectional view of a catalyzed prepreg after the surface removal step is shown.

[0059] Figure 5C A cross-sectional view of a catalyzed prepreg during an electroless plating step during a time sequence is shown.

[0060] Figure 5D A cross-sectional view of a catalyzed prepreg after a surface smoothing step is shown.

[0061] Figure 5E A cross-sectional view of the catalyzed prepreg after the solder resist step is shown.

[0062] Fig. 5F A cross-sectional view of a prior art etched copper trace on a non-catalyzed prepreg is shown.

[0063] Fig. 6AA cross-sectional view of a catalyzed adhesive applied to a non-catalyzed prepreg is shown.

[0064] Figure 6B shows the plasma etching step after Fig. 6A Cross-sectional view of .

[0065] Figure 6C A cross-sectional view of electroless plating on a prepreg substrate is shown.

[0066] Fig.6D A cross-sectional view of a mask material patterned on a prepreg substrate is shown.

[0067] Fig. 6E A cross-sectional view of copper electroplating on a prepreg substrate is shown.

[0068] Fig. 6F A cross-sectional view of the copper electroplating after stripping the mask is shown.

[0069] Figure 6G Shown is a cross-sectional view of a prepreg substrate after a flash etch to remove surface copper.

[0070] Fig. 7A A cross-section of a non-catalytic prepreg with foil lamination is shown.

[0071] Figure 7B A cross-sectional view of an etched non-catalyzed prepreg after patterning is shown.

[0072] Figure 7C A cross-section of a non-catalyzed prepreg is shown after holes have been drilled.

[0073] Fig.7D A cross-sectional view of a non-catalytic prepreg after filling the holes with a catalytic filler is shown.

[0074] Fig. 7E A cross-section of a non-catalyzed prepreg is shown after the second annular hole has been drilled.

[0075] Figure 7F A cross-sectional view of a non-catalyzed prepreg after electroless plating of annular holes is shown.

[0076] Figure 7G Shows the use of Figures 7A to 7F A perspective transparent view of a through-hole formed by the process.

[0077] Fig. 8A A cross-sectional view of a non-catalyzed prepreg laminate is shown.

[0078] Figure 8B Shows the Fig. 8A .

[0079] Figure 8C shows the Figure 8B .

[0080] Fig.8D shows the surface after the removal operation Figure 8C .

[0081] Fig. 8E shows the electroless plating operation after Fig.8D .

[0082] Fig. 9A , 9B , 9C, 9D and 9E show various stages of a cross-sectional view of a catalytic adhesive applied to a catalytic laminate that has been drilled, etched, electrolessly plated and planarized.

[0083] Fig. 10A , 10B , 10C, 10D, 10E, 10F, 10G, 10H and 10I show various stages of a cross-sectional view of a catalytic laminate having traces formed on an exposed catalytic surface.

[0084] Detailed description of the invention

[0085] Figure 1A An example process for making a prepreg (a matrix of pre-impregnated fibers bonded in a resin) is shown. Many different materials can be used for the fibers of the prepreg, including woven fiberglass cloth, carbon fibers, or other fibers, and a variety of different materials can be used for the resin, including epoxy resins, polyimide resins, cyanate resins, PTFE (Teflon) blended resins, or other resins.

[0086] One aspect of the present invention is a printed circuit board laminate capable of supporting fine pitch conductive traces on the order of 1 mil (25u), and although the present description focuses on the formation of copper traces using a catalyst for electroless copper formation, it should be understood that the scope of the present invention can be extended to other metals suitable for electroless and electroplating. For the chemical deposition of copper (Cu) channels, elemental palladium (Pd) is preferred as a catalyst, however any of the selected periodic table transition metal elements (such as platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) from Groups 9 to 11 or other compounds of these (including other metals (such as iron (Fe), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tin (Sn)) or mixtures or salts of the above items can be used as catalytic particles. This candidate list is intended to be exemplary rather than comprehensive, and other catalysts known in the art for attracting copper ions can also be used. In one example of the present invention, the catalytic particles are uniform catalytic particles. In another example of the present invention, the catalytic particles are inorganic particles or high temperature resistant plastic particles that are coated with a catalytic metal of a few angstroms thickness to form a non-uniform catalytic particle having a thin catalytic outer surface that encapsulates a non-catalytic inner particle. This formulation may be desirable for larger catalytic particles, such as particles with a longest dimension on the order of 25u. The non-uniform catalytic particles of this formulation may include inorganic, organic or inert fillers such as silicon dioxide (SiO2), inorganic clays such as kaolin, or high temperature plastic fillers coated on the surface with a catalyst such as palladium adsorbed onto the surface of the filler by vapor deposition or chemical deposition. In order for the catalytic particles to have the ideal properties that facilitate chemical plating, only a few atomic layers of the catalyst are required.

[0087] In one example of forming non-uniform catalytic particles, a (organic or inorganic) filler bath is size-sorted to include particles less than 25u in size, these sorted inorganic particles are mixed into an aqueous bath in a tank, stirred, and then a palladium salt such as PdCl (or any other catalyst such as a silver salt of another catalyst) is introduced in the presence of an acid such as HCl and a reducing agent such as hydrazine hydrate, the mixture thereby reducing the metallic palladium coating the inorganic particles, providing a few angstroms of Pd coating on the filler, thereby producing non-uniform catalytic particles having the catalytic properties of uniform Pd particles with a greatly reduced volume requirement of Pd compared to using uniform Pd metal particles. However, for extremely small catalytic particles on the order of a few nm, uniform catalytic particles such as pure Pd may be preferred.

[0088] Example inorganic fillers include clay minerals that may contain variable amounts of iron, magnesium, alkali metals, alkaline earth metals, and other cations, such as hydrated aluminosilicates. Example inorganic fillers of this family include silica, aluminum silicate, kaolinite (Al2Si2O5(OH)4), polysilicates, or other clay minerals belonging to the kaolin or china clay family. Example organic fillers include PTFE (Teflon) and other polymers with high temperature resistance.

[0089] Examples of palladium salts are: BrPd, Cl2Pd, Pd(CN)2, I2Pd, Pd(NO3)2*2H2O, Pd(NO3)2, PdSO4, Pd(NH3)4Br2, Pd(NH3)4Cl2H2O. The catalytic powder of the present invention may also comprise a mixture of heterogeneous catalytic particles (e.g., catalytic material coated on inorganic filler particles), homogeneous catalytic particles (such as elemental palladium) and non-catalytic particles (selected from the group of inorganic fillers).

[0090] Among the catalysts, palladium is the preferred catalyst due to comparative economics, availability, and mechanical properties, but other catalysts may also be used.

[0091] Figure 1A A roll of fabric cloth 102, such as woven fiberglass, is shown being fed through as a set of rollers direct the fabric into a reservoir 108 filled with epoxy resin mixed with catalytic particles and mixed with a volatile liquid to reduce viscosity, thereby forming an A-stage (liquid) prepreg.

[0092] The resin may be a mixture of polyimide resins, epoxy resins, and cyanate esters (which provide cure at elevated temperatures) or any other suitable resin formulation having a selectable viscosity during coating and thermosetting properties after cooling. Flame retardants may be added, for example to comply with flammability standards or to be compatible with one of the standard FR series of prepregs, such as FR-4 or FR-10. Additional requirements for high speed circuits are the dielectric constant ε (permittivity), which is often about 4 and governs the characteristic impedance of transmission lines formed on the dielectric, and the loss tangent δ, which is a measure of the frequency-dependent energy absorption over a distance, whereby the loss tangent is a measure of how the dielectric interacts with high frequency electric fields to undesirably reduce the signal amplitude by a calculable amount of dB / cm of the transmission line length. The resin is mixed with catalytic particles sorted by size. In an example formulation, the catalytic particles include at least one of uniform catalytic particles (metallic palladium) or non-uniform catalytic particles (palladium coated on inorganic particles or high temperature plastics), and for either formulation, the catalytic particles preferably have a maximum range of less than 25u, and 50% of the particle sizes are between 12u and 25u or in the range of 1-25u or smaller by total. These are example catalytic particle size embodiments, which are not intended to limit the scope of the invention. In an example embodiment, the catalytic particles (uniform or non-uniform) are in the size range of 1u-25u. In another example of the invention, uniform catalytic particles are formed by grinding metal palladium into particles and passing the resulting particles through a sieve having a mesh with 25u rectangular openings. In another example, a catalytic resin mixture is formed by mixing uniform or non-uniform catalytic particles into a pre-impregnated resin in a weight ratio (such as a ratio of substantially 12% by weight of catalytic particles to the weight of the resin). The weight ratio of the catalytic particles in the resin mixture can optionally be in the range of 8-16% of the weight of the catalytic particles relative to the total weight of the resin. It will be appreciated that other mixing ratios may be used and that the use of smaller particles may be preferred. In one example of the invention, the catalytic particle density is selected to provide an average distance between catalytic particles of the order of 3u-5u.

[0093] After the fabric is immersed in the catalytic resin bath 106 by roller 104, the catalytic resin saturated cloth is directed to roller 110 which establishes the thickness of the uncured liquid A-stage prepreg 105 which also establishes the percentage of resin in terms of the resin / glass+resin ratio. The A-stage prepreg 105 then passes through oven 103 which drives out the organics and other volatile compounds of the A-stage prepreg and greatly reduces the liquid content to form a tack-free B-stage prepreg 107 which is conveyed by roller 111. In an exemplary embodiment, oven 103 dries the volatile compounds from about 80% solvent ratio of the A-stage prepreg to less than about 0.1% solvent ratio of the B-stage prepreg. The resulting B-stage prepreg 107 is provided to a material handling device and may be cut into thin sheets for ease of handling and storage and subsequently placed into Figure 1B The laminator 126 applies pressure under vacuum over the entire surface of the sheet, changing the temperature profile while the prepreg core is in the laminator, following Figure 2Temperature profile 202 is shown. In one example of the present invention, to create a resin-rich surface, the prepreg sheets located near the outer surface (which will later have the surface removed to expose the underlying catalytic particles) are selected to have greater than 65% resin (such as glass 106 (71% resin), glass 1067, or glass 1035 (65% resin)), and the inner prepreg sheets (which are not subject to surface removal) are selected to have less than 65% resin. In addition, to reduce the possibility of glass fibers being present near the surface of the catalytic prepreg, woven glass fibers can be used with the inner prepreg layers, and flat non-woven glass fibers can be used in the outer resin-rich prepreg layers. The combination of the resin-rich prepreg and the flat non-woven glass fibers on the outer surface layer results in a 0.7 mil (17u) to 0.9 mil (23u) keep-out zone between the outer surface and the encapsulating glass fibers. Glass types 106, 1035 and 1067 are preferred for use on the resin rich outer surfaces because the glass fiber thickness (1.3-1.4 mils / 33-35u) is less than that found in typical prepreg sheets having greater than 65% resin used in the center region of the laminate, such as glass type 2116 with 3.7 mil (94u) fibers. These values ​​are given as examples, and it is expected that the smallest glass fibers available on the market will continue to decrease in diameter. The temperature versus time curve 202 is modified in the present invention to cause the catalytic particles and glass fibers to migrate away from the outer surface of the laminate, being repelled by the surface tension of the epoxy resin during the liquid state at the gel point temperature. After the cooling cycle of curve 202, the cured C-stage prepreg sheet is unloaded 114. The process of forming the cured C-stage prepreg sheets can use single or multiple fiber fabric sheets to vary the finished thickness, which can vary from 2 mils (51u) to 60 mils (1.5mm).

[0094] Figure 3 A flow chart of a process for making a prepreg laminate having catalytic particles infused but excluded from the outer surface of the prepreg is shown. Step 302 is mixing the catalytic particles into a resin, often with organic volatiles added to reduce the viscosity of the mixture, which forms a catalytic resin placed in a reservoir 108. Step 304 is infusing the catalytic resin into a fabric (such as a Figure 1ARoller 104 may be provided to form an A-stage prepreg), and step 306 is the initial rolling of the fabric impregnated with catalytic resin into a B-stage prepreg, for example by roller 110, step 307 is a baking step for removing organic solvent to form the B-stage prepreg, and step 308 is pressing the fabric impregnated with catalytic resin 130 into sheets of catalytic C-stage prepreg in laminator 126, which follows the temperature cycle of curve 202, and vacuum pump 128 evacuates chamber 124 throughout the lamination process to remove bubbles from the epoxy resin and reduce any pores that may form in the epoxy resin. The cooled finished catalytic C-stage prepreg sheets are cut and stored for later use.

[0095] Figure 2 The temperature versus time curve 202 shows the temperature distribution of the prepreg in the laminator 126, which is critical to the formation of a catalytic prepreg having a surface property of catalytic particles excluded from but just below the resin-rich outer surface. The resin is in a liquid state in the reservoir 108, and after the resin impregnates the glass fibers and the prepreg passes through the rollers 110, the prepreg is in the A stage. The prepreg is in the B stage after baking, where volatile organics are baked off, accompanied by initial resin hardening, which is at the end of the lamination cycle (e.g., Figure 2 The B-stage prepreg is converted to a C-stage prepreg (with a cooling stage). The B-stage prepreg is placed in a laminator and a vacuum is drawn to prevent trapped air from forming between the laminate layers. Heat is applied during the temperature ramp time 204 to reach the temperature and pressure determined prepreg gel point 205 (the gel point is defined as a state where the liquid and solid states are close to equilibrium with each other) within a duration of about 10-15 seconds, which is critical to the process of migrating catalytic particles away from the surface, after which the temperature of the prepreg is maintained at a dwell temperature and dwell time 206, which can be in the range of 60-90 minutes, followed by a cooling cycle 208. The dwell temperature and gel point temperature are pressure and resin dependent, in the example range of 120°C (for epoxy resins) to 350°C (for Teflon / polyimide resins). Keeping the prepreg at the gel point 205 for too short a duration will result in catalytic particles or glass fibers being undesirably present at the surface of the finished prepreg.

[0096] Figure 4 Shown by Figure 1A-Figure 1C , Figure 2 and Figure 3The resulting catalytic prepreg 402 is formed by a process in which catalytic particles 414 are uniformly distributed within the central region of the prepreg 402, but are not present below a first boundary 408 below the first surface 404, or below a second boundary 410 below the second surface 406. For the example particle distribution of particles less than 25u, the catalytic particle boundary is typically 10-12u below the surface (approximately half the particle size), so in order to make the embedded catalytic particles available for electroless plating, surface material to this depth or greater must be removed.

[0097] The catalytic laminate of the prior art has an activated surface, which must be masked to prevent undesirable chemical plating on the activated surface of the catalytic laminate. On the contrary, the catalytic laminate of the present invention excludes catalytic particles within the thickness range from the first surface 404 to the first boundary 408 and from the second surface 406 to the second boundary 410, providing the following benefits: for chemical plating, a separate mask layer to prevent contact with catalytic particles is not required, as it is in the prior art. Therefore, the removal of the surface material from the depth of the first surface 404 to the first boundary 408 or the removal of the surface material from the second surface 406 to the second boundary 410 leads to the exposure of the catalytic material that can be used for chemical plating. It is also desirable for providing a resin-rich surface to exclude not only catalysts but also processes for excluding fiber fabrics, because in the subsequent steps leading to the exposure of the fiber, the removal of the surface layer requires an additional cleaning step, so the surface removal is only for resin so as to expose the lower catalytic particles is preferred. This is achieved by using a combination of a resin-rich outer prepreg layer and a flat non-woven glass fiber layer with smaller diameter fibers on the outer layer. Another advantage of using electroless plating to form traces in vias is that the traces are mechanically supported on three sides, which provides greatly improved trace adhesion to the dielectric laminate.

[0098] Figures 5A to 5E The process steps identifying various structures are shown in a sequence (but not to scale) and are merely provided as a simplified view of the process steps for understanding the present invention. Figure 5A Shown by Figure 1A-Figure 1C , Figure 2 and Figure 3 1 is an enlarged cross-sectional view of a catalytic prepreg 508 formed by a process of forming a catalytic prepreg 508. The catalytic particles 502 can range in size from 25u and smaller, in this example they are shown as being in the range of 12u to 25u for clarity. As previously described, the catalytic particles can include non-uniform catalytic particles (organic or inorganic particles with a catalytic surface coating) or uniform particles (catalytic metal particles). The first boundary 504 is approximately 25u below the first surface layer 506. The second surface layer 505 and the second surface boundary 503 on the opposite surface are shown for reference, but can be shown in the same manner as for the embodiment of the present invention. Figures 5A to 5E The sequence is formed in the same manner as described above. Also shown is a drill hole 511 which will provide a connection between the trace on the first surface layer 506 and the trace on the second surface layer 505.

[0099] Figure 5B A channel 510 is shown. Figure 5AThe laminate of FIG. 5 is formed by removing the first surface layer 506 in the area where the trace is desired. The prepreg is also removed in an annular ring 513 around the passage at the same or different depth as the trace channel 510. The surface material can be removed by laser ablation, wherein the temperature of the catalytic prepreg is immediately increased until the catalytic prepreg is evaporated, while keeping the surrounding prepreg structurally unchanged, keeping the catalytic particles exposed. For the prepreg material to be ablated, it may be preferred to use a laser with a wavelength (such as an ultraviolet (UV) wavelength) with low reflectivity and high absorption of the optical wavelength. Examples of such UV lasers are UV excimer lasers or yttrium aluminum garnet (YAG) lasers, which are also good choices due to the narrow beam range and high available power, which are used to form channels with precise mechanical depth and well-defined sidewalls. An example laser can remove material at a 0.9-1.1 mil (23u to 28u) diameter width with a depth controlled by the laser power and a speed of movement across the surface. Another surface removal technique for forming the channel 510 and the annular ring 513 is plasma etching, which can be done locally or by preparing the surface with a patterned mask that excludes plasma from the first surface layer 506 or the second surface layer 505 (such as a dry film photoresist or other mask material with a low etch rate compared to the etch rate of the catalytic prepreg). The photoresist thickness is typically selected based on the epoxy / photoresist etch selectivity (so that the plasma etch for removing the desired depth of cured epoxy leaves enough photoresist at the end of the etch), or in the case where the photoresist is used as a plating mask, the thickness is selected according to the desired deposition thickness. Typical dry film thicknesses are in the range of 0.8-2.5 mils (20-64u). Plasmas suitable for etching resin-rich surfaces include mixtures of oxygen (O) and CF4 plasma mixed with an inert gas such as nitrogen (N), or argon (Ar) can be added as a carrier gas for the reactive gas. The mask pattern can also be formed using a dry film mask, a metal mask, or any other type of mask with holes. In the case of using a mechanical mask, the resist can be applied using photolithography, screen printing, stencil printing, brushing with a squeegee, or any method of applying the resist. Another method for removing the surface layer of the prepreg is mechanical grinding, such as a linear or rotary cutting tool. In this example, the prepreg can be fixed in a vacuum plate chuck, and a rotary cutter (or a fixed cutter with a movable vacuum plate) can advance a pattern defining a trace such as a pair of x, y coordinates defined by a Gerber format photo file. In another example of removing surface material, a water cutting tool can be used, in which a water jet with abrasive particles entrained in the stream can impact on the surface, thereby removing material below the first boundary 504.Any of these methods may be used alone or in combination to remove surface material from the catalytic prepreg 508 and form a channel 510, preferably extending below the first boundary 504. Thus, the minimum channel depth is the depth required to expose the underlying catalytic particles (which are a feature of the cured prepreg). Because the catalytic material is uniformly dispersed throughout the cured prepreg below the first boundary 504, the maximum channel depth is limited by the depth of the woven fiber (such as glass fiber) fabric, which tends to complicate channel cleaning because the fibers may break and redeposit in the channel intended for chemical plating, or otherwise interfere with subsequent process steps. Typical channel depths are 1 mil (25u) to 2 mils (70u). The final step after removing the surface material to form the channel 510 is to clean off any particles of the removed material, which can be accomplished using ultrasonic cleaning, a water jet mixed with a surfactant, or any other cleaning means that does not result in the removal of material from the first surface layer 506 around the channel.

[0100] Figure 5C A contour plot showing the progress of electroless plating over time, where a dissolved reducing agent is used to Figure 5B The catalytic prepreg is placed in an electroless plating solution to reduce the metal ions on the catalytic prepreg to a metallic state. An example electroless copper plating solution formulation uses a mixture of Rochelle's salt as a complexing agent, copper sulfate as a copper metal source, formaldehyde as a reducing agent, and sodium hydroxide as a reactant. In this example, a tartrate (Rochelle's salt) plating solution is preferred for ease of waste disposal; Rochelle's salt does not chelate as strongly as alternatives (such as EDTA or ethylenediamine). In this example, tartrate (Rochelle's salt) is the finishing agent, copper sulfate is the metal source, formaldehyde is the reducing agent, and sodium hydroxide is the reactant. Other electroless plating formulations are also possible, and this example is given for reference. The electroless plating is initially formed on the surface of the exposed catalytic particles, as shown in the shadow pattern 520 at time t1 and the matching shadow pattern in the through hole 535. Copper deposition progresses as electroless plating continues into the hashed region of deposition shown for subsequent times t2 522 , t3 524 , and t4 526 , where deposition 526 may extend over first surface layer 506 and via 535 is also filled with copper.

[0101] A key advantage of electroless plating with channels etched in the catalytic material is that electroless plating progresses on all three sides simultaneously, compared to electroplating which processes only from the bottom (initially plated) layer.

[0102] Figure 5DThe result of the surface smoothing operation is shown, where the completed electroless plated traces 534 and vias 535 are coplanar with the surface 532. Surface smoothing can be achieved in many different ways, such as using a 420 to 1200 grit abrasive applied to the flat surface, with gentle pressure and linear or rotational agitation between the plate and the flat surface to provide the grinding action. Other methods for planarizing the surface can be used, including milling or machining using chemical processes, mechanical processes, or other methods for forming a flat surface. Figure 5E A solder mask layer 536 is shown, which may be screen printed over the traces 534 for isolation and protection, such as a finished outer layer of a multi-layer board.

[0103] Fig. 5F A prior art etched copper trace is shown for comparison purposes. Trace 554 is formed using a prior art subtractive etching process, where trace 554 is what remains after etching the remainder of the copper present on the surface layer on the non-catalytic prepreg 550. The outer layer of copper is patterned with a photoresist (such as a dry film), and the surface is subsequently etched, which produces a trapezoidal cross-sectional profile for trace 554 because the top of the trace undergoes greater lateral etching than the bottom of the trace adjacent to the non-catalytic prepreg 550. Another advantage of the additive process of the present invention is that for traces formed using the prior art process of etching all copper except the desired trace copper, surface contamination on the surface causes adjacent traces to short because copper bridges (where contamination is present on the surface of the copper) remain, which does not occur in the additive electroless plating of the present invention. For comparison with the figures of the present invention, solder mask 552 is also shown. As seen in the figure, trace 554 is supported only by adhesion to the non-catalytic prepreg 550, while Figure 5E The trace 534 is supported on three sides and locked into its associated channel in the catalytic prepreg 508.

[0104] Figures 6A to 6G Another embodiment of the present invention is shown using a non-catalytic prepreg 602, which may be a conventional prepreg without catalytic particles. Fig. 6A In this example, through holes 603 are first punched or drilled into a non-catalytic prepreg 602. The catalytic adhesive is formulated by mixing a resin and catalytic particles, which may be in the same proportions and manner as the catalytic resin described above (although it may have a higher viscosity for certain surface coating applications (such as by brushing with a squeegee), the main difference being that the catalytic adhesive is applied to a (generally) non-catalytic substrate, although it may also be applied to a catalytic substrate. For use in a catalytic adhesive, the catalytic particles are stirred until fully wetted, so that the catalytic adhesive 604 ensures that the catalytic particles 606 are not exposed until a subsequent surface coating removal operation (such as Figure 6BIn this example, the catalytic resin is sprayed or brushed onto the surface of the non-catalytic prepreg 602 and into the through hole 603, as shown in FIG. Fig. 6A As shown. The catalytic adhesive 604 includes a resin that contains a distribution of catalytic particles (such as palladium particles less than 25u), or in one example of the present invention, 50% of the particles by number fall within the range of 12-25u in terms of the longest particle size or have a particle range of 1-25u as possible examples. The catalytic adhesive can be formed using a ratio of 8-16% by weight of catalyst to weight of resin (where 12% is a preferred value), as described previously for the catalytic resin. The resulting catalytic adhesive can be applied to a non-catalytic substrate and both are baked to cure the catalytic adhesive to the non-catalytic prepreg 602. In one coating method, the catalytic adhesive is applied to the leading edge of a mechanized squeegee, the leading edge of which includes a flexible blade that carries the catalytic adhesive and passes over the surface of the non-catalytic laminate, and the pressure and spacing between the flexible blade and the non-catalytic laminate are adjusted so that any drilled holes are filled with the catalytic laminate and the desired thickness of the catalytic laminate is evenly arranged on the surface of the non-catalytic laminate in a single pass of the squeegee. The thickness of the catalytic adhesive is generally 12-75u. The thickness of the catalytic adhesive should be at least 2 times thicker than the largest catalytic particle to ensure that the catalytic particle remains below the surface of the catalytic adhesive.

[0105] Fig. 6A The surface of the catalytic particles is then subjected to a plasma cleaning step which strips the resin from the areas above the surface of the catalytic particles and the non-catalytic resin, leaving behind Figure 6B Catalytic particles 606 are shown adhered to the surface of non-catalytic prepreg 602. Figure 6C Shows the Figure 6B The plasma cleaned surface is subjected to an electroless plating bath which is performed for a sufficient period of time to form a thin but continuous coating of electroless copper deposited initially on the catalytic particles 606 and extending across the entire top surface. Fig.6D The addition of a pattern mask 610 over the electroless copper layer 608 is shown. Because the electroless layer now covers the surface of the non-catalytic prepreg 602, an electroplating operation can then occur to electroplate additional copper onto the exposed patterned areas, such as Fig. 6E As shown by trace 612, copper can be deposited to a level below or above mask 610. Fig. 6F A mask stripping operation is shown in FIG. 6 , which removes the pattern mask 610 , leaving behind copper traces 612 and the electroless copper layer 608 . Figure 6GThe results of a rapid etch are shown which removes the thin electroless copper layer 608 and an equal amount of the surface of the trace 612, leaving a trace comprising a uniform trace including both the electroplated copper and the underlying electroless copper deposit, thereby providing a conductive circuit trace.

[0106] Fig. 10A , 10B , 10C, 10D, 10D, 10E, 10F, 10G, 10H and 10I show that the previously Figure 4 The catalytic laminate described in the foregoing has catalytic particles 414 distributed throughout the catalytic laminate and has a catalytic particle exclusion depth 418 below the first surface 404 and the second surface 406, so that electroless plating does not occur unless the second surface 406 or the first surface 404 is removed below the exclusion depth 418, thereby exposing the catalytic particles. The catalytic particle exclusion depth 418 is 1 / 2 of the average size of the catalytic particles.

[0107] Fig. 10A The prepreg is shown associated with exterior surfaces 1004 and 1008 that are free of catalytic particles until the exterior surfaces are removed to depths 1002 and 1010, respectively, sufficient to expose underlying catalytic particles below the exclusion depth.

[0108] Fig. 10B An example through hole or via 1012 is shown which, when drilled, exposes catalytic particles on an inner surface 1014 of the bore.

[0109] Fig. 10C The catalytic laminate 1006 is shown after blanket etching the entire outer surface of the catalytic laminate 1006 to below the exclusion depth, thereby creating an outer surface 1018 with exposed catalytic particles. The original pre-etched catalytic laminate surface 1016 is shown for reference. Fig. 10B The holes / vias 1012 are drilled and Fig. 10C The sequence of operations for blanket etching the outer surface of the prepreg may be performed in any order. Blanket etching may preferably be performed using reactive plasma, chemical etchants, however laser cutting, water jet cutting, mechanical abrasion, mechanical cutting or any other means that uniformly etches the outer surface of the prepreg and exposes the underlying catalytic particles below the surface and into the exclusion depth may be used. Fig. 10C The step of is performed without any pattern mask from the previous catalytic laminate etching operation because the goal is to remove the resin rich surface below the exclusion depth to expose the catalytic particles on the entire surface of the catalytic laminate 1006.

[0110] Two different electroplating techniques can be used to perform deposition of surface conductors (such as copper) on a surface. In the first chemical plating technique, a dielectric layer with exposed catalytic particles (such as palladium) is immersed in a plating solution containing metal ions (such as copper). The rate at which metallic copper is chemically deposited on the catalytic surface is slower than the electroplating deposition rate of metallic copper, but chemical plating occurs on all surfaces with exposed catalytic particles and also on surfaces with copper. Electroplating requires a uniform conductive surface, so chemical plating is used as a pre-indicator for electroplating. Electroplating also requires an external voltage source, resulting in a faster rate of copper deposition than chemical deposition. A sacrificial copper anode with a positive voltage is placed in an electrolyte plating solution, and the conductive surface to be electroplated is connected to a negative voltage. Anode copper migrates from the anode as a metal ion and reaches the cathode surface through the electrolyte, and the metal ions are deposited on the cathode surface. In this example, the cathode surface is a PCB that needs to be copper-plated. Electroplating requires that all surfaces have a common potential, which is usually achieved by using copper foil or an electroless plating step on a dielectric surface with exposed catalytic particles until continuous conductivity across the board allows the board to function as an anode, as required for a cathodic copper source.

[0111] Fig. 10D The completion of the electroless plating step is shown, wherein the drilled and surface etched catalytic laminate 1006 is placed in an electroless plating bath of metal ions (usually copper) which are deposited onto the outer surface 1018 of the laminate and Fig. 10C The thickness of the electroless copper 1020 should be the minimum thickness required to ensure continuous coverage for successful electroplating, and is typically on the order of 0.15 mils.

[0112] Fig.10E A subsequent step of applying a patterned photoresist 1024 over the previously applied electroless copper 1020 is shown, where the photoresist 1024 covers all areas except where traces or loop conductors are needed around the drilled holes or vias 1012. The patterned photoresist 1024 has the effect of isolating the patterned areas from subsequent electroplating.

[0113] Fig.10F The subsequent step of electroplating copper 1022 on the electroless copper 1020 is shown, and the electroless copper 1020 is used as an electrode in the electroplating operation. The thickness of the electroplated copper 1022 can be any thickness, preferably less than the thickness of the resist 1024 and greater than 1 times (or preferably 2 times or more) the thickness of the electroless metal deposition.

[0114] Figure 10G Shows stripping Fig.10FThe subsequent step of removing the resist 1024 of the electroplated copper 1022 exposes the initially applied thin electroless copper plated area 1026. Preferably, the thickness of the electroplated copper 1022 is greater than the thickness of the electroless copper 1020, so that Fig. 10H The rapid etching step preferentially removes the exposed electroless copper areas 1026 and leaves substantially all of the electroplated copper 1022 behind.

[0115] Fig.10I The completed process is shown. For clarity in understanding the present invention and the processing steps, the boundary between the chemical copper plating 1020 and the electroplated copper 1022 is presented in the front. Fig.10F When deposited on the exposed chemically plated copper 1020 during the step of Fig.10I The resulting through-hole plating is continuous copper around the hole and the chemical copper 1020 / electroplated copper 1022, as shown.

[0116] Figures 7A to 7G The series of cross-sectional views show a series of steps for forming through holes in a conventional non-catalytic prepreg 702 having an upper foil laminate layer and a lower foil laminate layer. Figure 7G shows a perspective view of the finished through hole, and Figures 7A to 7F is passed through at the end of various intermediate processing steps Figure 7G Cross-sectional view of AA.

[0117] Figure 7B A cross-sectional view of upper trace 704 and lower trace 706 after patterning is shown, where upper trace 704 will connect to lower trace 706 on the opposing surface of non-catalyst prepreg 702 . Figure 7B A through hole 708 , which may be formed by punching or drilling, is shown located in the center of the annular ring of pads 716 formed by upper trace 704 and pads 718 formed by lower trace 706 . Fig.7D A catalytic filler 710 is shown, such as a formulation of plugged through-holes having catalytic particles. The catalytic filler 710 is typically a thick fluid having a viscosity in the range of 70,000-80,000 centipoise (cP) and is placed in Figure 7C through hole 708, and Fig. 7EA secondary hole 712 is shown drilled in the catalytic filler 710, which exposes the catalytic filler particles present in the catalytic filler 710, thereby making the catalyst available for the electroless plating operation. An electroless copper deposition step follows, and electroless copper Cu++ forms a conductive deposit layer 714 on the upper trace 704, the annular ring top pad 716, through the secondary hole 712 with the exposed catalytic particles, on the lower pad 718, and on the lower trace 706, which completes the circuit from the upper trace 704 through the via structure to the lower trace 706. As is clear to those skilled in the art, although an annular ring conductor is shown on each connection surface, the trace may be directly connected to the via with or without an annular ring.

[0118] Fig. 8A Another method for electroless plating of traces onto a laminate is shown using a non-catalyzed substrate or prepreg 802, with optional holes 804 drilled or punched for layer-to-layer connections. Figure 8B Such as using a squeegee, screen printing, stencil or as previously described. Fig. 6A Any other method described is used to apply the catalytic adhesive 806. In this coating operation, the holes 804 are also filled with the catalytic adhesive 806. Figure 8C Secondary drillings 808 are shown in the annular ring of holes 804 which activate the catalytic adhesive 806 in the drillings 808 by exposing the catalytic particles. Fig.8D Removal 814 of a surface layer sufficient to expose catalytic particles for forming electroless plated conductive traces, pads, and vias is shown. Fig. 8E The completion of electroless plating is shown, where copper 816 is plated onto the catalytic adhesive that has been drilled, etched, or otherwise removed. Figure 5D As described, planarization may be optionally performed, or a solder mask may be applied. In certain applications (such as high frequency applications where dielectric loss tangent is critical), it may be desirable to use a non-catalytic laminate (such as PTFE) and a non-uniform mixture of a resin-based catalytic laminate. In this case, it may be necessary to use plasma etching, chemical etching, or other methods known in the prior art for destroying long-chain polymer molecules to roughen the surface of a non-catalytic laminate (such as PTFE), thereby providing better adhesion for the catalytic adhesive at the catalytic adhesive / PTFE boundary. In one example of the present invention, the PTFE non-catalytic substrate is uniform PTFE, in another example, it is a laminate, and in either case, the substrate may or may not include fiber (such as glass fiber) reinforcement.

[0119] Figures 8A to 8E The deformation of the laminated structure Figures 9A to 9E, where a catalytic adhesive 906 is used on a catalytic laminate. This method has several advantages. One advantage is that the application of the catalytic adhesive 906 does not require Fig. 8A As shown in FIG804, through holes 908 are pre-drilled prior to application of the catalytic binder. Another advantage is that the resin-rich surface can be formed by the catalytic binder 906 rather than the catalytic substrate 904, so that the catalytic particles of the substrate 902 do not need to have a Figure 4 An exclusion zone near the surface is shown as this is now provided by the catalytic adhesive 906 applied to one or both sides of the substrate 902. Fig. 9C shows a cross-sectional view after hole 908 is drilled, step 9D shows surface removal 914, and Fig.9E Electroless plating 916 is shown using the aforementioned method.

[0120] The foregoing description provides examples of the present invention only for the purpose of understanding the underlying mechanisms and structures used, and is not intended to limit the scope of the present invention to only the specific methods or structures shown. For example, Figures 5A to 5E 6A to 6G illustrate a single-sided structure with trace channels cut only on the first surface, while the same structure and method can be applied to the second surface layer 505 without loss of generality, since the electroless plating step can be applied to the channels or exposed catalysts on both sides of the board in a single step. Figures 5A to 5E , 6A to 6G, 8A to 8E, 9A to 9E, 10A to 10I and the layers manufactured in Figures 7A to 7F The through holes may be formed on separate layers which are subsequently laminated together into a single board having mixed layers of catalytic prepreg and non-catalytic prepreg, and the scope of the claims relating to "multilayer PCB" will be interpreted to include such a structure. Similarly, although Figures 5A to 5E The trace structures and through-hole structures of 6A to 6G, 8A to 8E, and 7A to 7F are shown in combination as they typically appear on a PCB, but these examples are for illustration only and are not intended to limit the invention to these structures. For example, according to the novel aspects of the process, mounting holes for through-hole components without electrical connections can be formed without connecting traces or annular rings.

[0121] In this specification, "approximately" is understood to mean less than 4 times or more or less, and "substantially" is understood to mean less than 2 times or more or less. The "order of magnitude" of a value includes a range from 0.1 times the value to 10 times the value.

[0122] Certain post-processing operations that are common to printed circuit board manufacturing are not shown and can be performed using prior art methods on boards produced according to the new process. Such operations include tinning for improved solder flow, gold flashing for improved conductivity and reduced etching, solder mask operations, silk screen printing information on the board (part number, reference designator, etc.), scribing the finished board or providing separation tabs, etc. When performed on the planarized board of certain aspects of the present invention, some of these operations can produce improved results. For example, silk screen lettering on traces or vias is traditionally split due to the thickness of the traces and vias on the surface of the circuit board, while these operations will provide excellent results on a flat surface.

Claims

1. A catalytic laminate having at least one surface that is resin-rich compared to other areas of the catalytic laminate; The catalytic laminate has catalytic particles, and the catalytic particles have a maximum catalytic particle range; The catalytic laminate has a catalytic particle exclusion zone of 1 / 2 of the average size of the catalytic particles below the at least one surface, and the catalytic particles are not present in the catalytic particle exclusion zone; Thereby electroless plating deposits metal on the at least one surface from which surface material has been removed, and electroless plating deposition does not occur on other portions of the at least one surface.

2. The catalytic laminate according to claim 1, wherein the catalytic particles are non-uniform.

3. The catalytic laminate of claim 2, wherein the catalytic particles comprise fillers coated with a catalyst.

4. The catalytic laminate according to claim 3, wherein the filler is at least one of the following: a clay mineral, a hydrated aluminosilicate, silica, a polysilicate, or a high temperature plastic.

5. The catalytic laminate according to claim 3, wherein the filler is kaolinite.

6. The catalytic laminate according to claim 3, wherein the size of the catalytic particles is on the order of 3 μm or less.

7. The catalytic laminate according to claim 3, wherein the ratio of the catalytic particles to the resin is in the range of 8% to 16% by weight.

8. The catalytic laminate according to claim 3, wherein the catalytic particles are silica or kaolin coated with a catalytic material.

9. The catalytic laminate according to claim 3, wherein the catalyst is palladium.

10. The catalytic laminate according to claim 3, wherein the catalyst is at least one of the following: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or their salts.

11. The catalytic laminate of claim 1, wherein the catalytic particles are uniform.

12. The catalytic laminate of claim 11, wherein the catalytic particles are palladium.

13. The catalytic laminate according to claim 11, wherein the catalytic particles are at least one of the following: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or their salts.

14. The catalytic laminate according to claim 11, wherein the ratio of the catalytic particles to the resin is in the range of 8% to 16% by weight.

15. The catalytic laminate according to claim 11, wherein a majority of the catalytic particles have a size less than 25 μm.

16. A method for forming a catalytic prepreg laminate having a resin rich surface that excludes catalytic particles at an exclusion depth below the resin rich surface, the method comprising: The catalytic resin is formed by blending the catalytic particles into a resin and a solvent; infusing the catalytic resin into the fabric; rolling the fabric impregnated with the catalytic resin to a desired first thickness; baking the resin impregnated with the catalytic particles until most of the solvent is removed; placing the baked catalyzed prepreg into a laminator having a flat pressure surface; heating the catalytic prepreg under vacuum while applying lamination pressure, varying the temperature of the laminator to provide heating ramped to a dwell temperature that maintains a gel point, maintaining the dwell temperature for a dwell time sufficient to cause the catalytic particles to migrate away from an outer surface of the catalytic prepreg, and thereafter reducing the temperature in a cooling cycle; wherein the dwell time, the dwell temperature and the lamination pressure are selected such that the catalytic particles are excluded in the region below the resin-rich surface.

17. The method of claim 16, wherein the catalytic particles are at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or salts thereof.

18. The method of claim 16, wherein the resin comprises at least one of: an epoxy resin, a polyimide resin, a cyanate resin, or a Teflon blended resin.

19. The method of claim 16, wherein the gel temperature is in the range of 120°C to 350°C.

20. The method of claim 16, wherein the gel time during the temperature ramp time interval is in the range of 5 seconds to 15 seconds.

21. A catalytic prepreg comprising: A fabric impregnated with a resin having catalytic particles less than 25 μm; The prepreg has at least a first flat surface, and the catalytic particles are uniformly distributed in an inner region of the prepreg, the prepreg also having a resin-rich surface excluding the catalytic particles, the resin-rich surface having a depth of 1 / 2 of an average size of the catalytic particles; Thus, removal of material from the resin-rich surface exposes sufficient of the catalytic particles to allow electroless plating to occur.

22. A catalytic prepreg according to claim 21 wherein the fabric is formed from woven glass fibres.

23. The catalytic prepreg of claim 21, wherein the catalytic particles comprise at least one of palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or salts thereof.

24. A catalytic prepreg according to claim 21 wherein the catalytic particles are blended into the resin in a proportion in the range of 8% to 16% by weight of the resin.

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