Including a package containing a solder mask layer configured as a base plane for a device.

Abstract

A package includes: a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located above the solder resist layer such that a portion of the device contacts the solder resist layer; and an encapsulation layer located above the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a base plane for the device. The device is located above the solder resist layer such that a surface of the device facing the substrate is substantially parallel to the first surface of the substrate. The solder resist layer includes at least one recess. The device is located above the solder resist layer such that at least one corner of the device contacts the at least one recess.

Description

[0001] Priority requirements

[0002] This patent application claims priority to application number 16 / 590,299, filed on October 1, 2019, entitled “PACKAGE COMPRISING A SOLDERRESIST LAYER CONFIGURED AS A SEATING PLANE FOR A DEVICE”, which has been assigned to the assignee of this application and is expressly incorporated herein by reference. Technical Field

[0003] Various features relate to packages that include devices, but more specifically to packages that include solder mask layers configured as base planes for devices. Background Technology

[0004] Figure 1 The illustration shows a package 100 including a substrate 102, a die 104, and an encapsulation layer 160. The die 104 is coupled to a first surface of the substrate 102 via a plurality of solder interconnects 140, which may include bumps and pillars. The substrate 102 includes a plurality of dielectric layers 120 and a plurality of interconnects 122. Each of the dielectric layers 120 includes a patterned metal layer. The substrate 102 includes a first solder resist layer 124, a second solder resist layer 126, and a plurality of solder interconnects 130. The encapsulation layer 160 encapsulates the die 104. There is a continued need to improve the performance of packages. Summary of the Invention

[0005] Various features relate to packages that include devices, but more specifically to packages that include solder mask layers configured as base planes for devices.

[0006] One example provides a package comprising: a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located above the solder resist layer such that a portion of the device contacts the solder resist layer; and an encapsulation layer located above the solder resist layer such that the encapsulation layer encapsulates the device.

[0007] Another example provides an apparatus comprising: a substrate having a first surface; a component for providing horizontal support coupled to the first surface of the substrate; a device positioned above the component for providing horizontal support such that a portion of the device contacts the component for providing horizontal support; and an encapsulation component positioned above the component for providing horizontal support such that the encapsulation component encapsulates the device.

[0008] Another example provides a method for manufacturing a package. The method provides a substrate including a first surface. The method forms a solder resist layer over the first surface of the substrate. The method couples a device to the substrate such that the device is located above and in contact with the solder resist layer. The method forms an encapsulation layer over the solder resist layer such that the encapsulation layer encapsulates the device. Attached Figure Description

[0009] Various features, properties and advantages will become apparent when the following detailed description is presented in conjunction with the accompanying drawings, wherein the same reference numerals are correspondingly identified throughout.

[0010] Figure 1 The diagram shows the outline of the device, including the die and the substrate.

[0011] Figure 2 The illustration shows an assembly diagram of a package including a solder mask layer configured as a base plane for a device.

[0012] Figure 3 The illustration shows a view of a package including a solder mask layer configured as a base plane for a device.

[0013] Figure 4 The illustration shows a profile of the AA section of a package, including a solder mask layer configured as a base plane for a device.

[0014] Figure 5 The illustration shows a profile of the BB cross-section of a package including a solder mask layer configured as a base plane for a device.

[0015] Figure 6 The illustration shows a plan view of a package including a solder mask layer configured as a base plane for a device.

[0016] Figure 7 The illustration shows a plan view of an exemplary pattern of a solder mask layer configured as a base plane for a device.

[0017] Figure 8 The illustration shows a plan view of another exemplary pattern of a solder mask layer configured as a base plane for a device.

[0018] Figure 9 The illustration shows a plan view of another exemplary pattern of a solder mask layer configured as a base plane for a device.

[0019] Figure 10 The illustration shows a plan view of another exemplary pattern of a solder mask layer configured as a base plane for a device.

[0020] Figure 11 The illustration shows a plan view of another exemplary pattern of a solder mask layer configured as a base plane for a device.

[0021] Figure 12 The illustration shows a plan view of another exemplary pattern of a solder mask layer configured as a base plane for a device.

[0022] Figure 13 The illustration shows a plan view of a package including a solder mask layer configured as a base plane for a device.

[0023] Figure 14 (including) Figures 14A to 14D The illustration shows an exemplary sequence for manufacturing a package that includes a solder mask layer configured as a base plane for a device.

[0024] Figure 15 An exemplary flowchart of a method for manufacturing a package is illustrated, the package including a solder mask layer configured as a base plane for a device.

[0025] Figure 16 The illustrations depict various electronic devices that can integrate dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. Detailed Implementation

[0026] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring aspects of this disclosure.

[0027] This disclosure describes a package comprising: a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; and a device disposed above the solder resist layer such that a portion of the device contacts the solder resist layer. The package also includes an encapsulation layer disposed above the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a base plane for the device. The solder resist layer provides a layer that helps to reduce, minimize, and / or eliminate tilt of the device (relative to the substrate), which can help the device perform better. For example, the device may be a tilt-sensitive radio frequency (RF) device. Therefore, reducing, minimizing, and / or eliminating tilt of the RF device relative to the substrate helps to improve the performance of the RF device. The device and / or a portion of the device may be disposed above the solder resist layer such that the substrate-facing surface of the device is substantially parallel to the first surface of the substrate. The solder resist layer includes at least one recess. The device is disposed above the solder resist layer such that at least one corner of the device contacts the at least one recess.

[0028] An exemplary package including a solder mask layer configured as a base plane for a device.

[0029] Figure 2 The illustration shows an assembly of a package 200 including a solder mask layer configured as a base plane for a device. Package 200 includes a substrate 202, a solder mask layer 204, substrate interconnects 205, solder interconnects 206, device interconnects 207, and a device 208. Package 200 may include a radio frequency (RF) device package.

[0030] Substrate 202 can be any type of substrate, such as a laminated substrate. Substrate 202 may include silicon and / or glass. Substrate 202 may include one or more dielectric layers. Substrate 202 may include multiple interconnects.

[0031] Solder mask 204 is coupled to a surface (e.g., a first surface) of substrate 202. Solder mask 204 includes patterns and / or openings that allow solder mask 204 to be configured as a base plane for device 208. As will be further described below, when at least a portion of device 208 is positioned (e.g., rested on, placed) above solder mask 204, solder mask 204 is configured as a horizontal support for device 208 such that the surface of device 208 (e.g., the surface facing substrate 202, bottom surface, active surface) is parallel to (or as parallel as possible to) the surface of substrate 202. Solder mask 204 may be a component for providing horizontal support.

[0032] Substrate interconnects 205 (e.g., 205a-205c), solder interconnects 206 (e.g., 206a-206c), and device interconnects 207 (e.g., 207a-207c) are configured to provide one or more electrical paths between substrate 202 and device 208. For example, substrate interconnects 205a, solder interconnects 206a, and device interconnects 207a may be configured to provide one or more electrical paths for ground between substrate 202 and device 208. Substrate interconnects 205b, solder interconnects 206b, and device interconnects 207b may be configured to provide one or more electrical paths for input / output (I / O) signals between substrate 202 and device 208. Substrate interconnects 205c, solder interconnects 206c, and device interconnects 207c may be configured to provide one or more electrical paths for power between substrate 202 and device 208. However, different implementations may use different interconnect configurations and / or arrangements to provide ground, power and / or I / O signals between substrate 202 and device 208.

[0033] Substrate interconnect 205 may be coupled to a first surface of substrate 202. Substrate interconnect 205 may include one or more conductive layers (e.g., metal, copper). In some implementations, substrate interconnect 205 may be considered part of substrate 202. Solder interconnect 206 may be coupled to substrate interconnect 205. Device interconnect 207 may be coupled to solder interconnect 206. Device interconnect 207 may include one or more conductive layers (e.g., metal, copper). In some implementations, device interconnect 207 may be considered part of device 208.

[0034] Device 208 is coupled to solder mask 204 and device interconnect 207. Device 208 is located above substrate 202 and solder mask 204 such that at least a portion of device 208 contacts (e.g., directly contacts) solder mask 204. In this configuration, portions of device 208 can be positioned (e.g., rested) above solder mask 204. For example, one or more corners of device 208 can rest on and / or contact portions of solder mask 204. Thus, one or more portions of solder mask 204 can be configured as a base plane for device 208.

[0035] The solder mask layer 204 provides a layer that helps reduce, minimize, and / or eliminate tilt (e.g., tilt along length and / or width) of the device 208 (relative to the substrate 202), which can help the device 208 perform better. For example, the device 208 may be a tilt-sensitive radio frequency (RF) device. Therefore, reducing, minimizing, and / or eliminating the tilt of the RF device relative to the substrate 202 helps improve the performance of the RF device. The device 208 may be located above the solder mask layer 204 such that the surface of the device 208 facing the substrate 202 is generally parallel to a first surface of the substrate 202. The solder mask layer 204 includes at least one recess (e.g., 240a-240d). The device 208 may be located above the solder mask layer 204 such that at least one corner of the device 208 contacts at least one recess (e.g., 240a-240d).

[0036] Device 208 may include radio frequency (RF) devices, dies, integrated devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, and / or combinations thereof. Device 208 may be an assembly of components and / or devices.

[0037] As will be Figure 3As further described herein, package 200 may include an encapsulation layer 209 and a shield 210. Encapsulation layer 209 may include a mold, resin, and / or epoxy resin. Encapsulation layer 209 may be a component for encapsulation. Shield 210 may be an electromagnetic interference (EMI) shield. Shield 210 may be a component for shielding (e.g., a component for EMI shielding). Shield 210 may be configured to couple to ground.

[0038] Figure 3 Another view of package 200 is shown. Package 200 includes a substrate 202, a solder mask 204, substrate interconnects 205, solder interconnects 206, device interconnects 207, a device 208, an encapsulation layer 209, and a shield 210. It should be noted that the solder mask 204 can be considered as part of the substrate 202.

[0039] As described above, the solder mask 204 includes recesses (e.g., a first recess 240a, a second recess 240b, a third recess 240c, and a fourth recess 240d). The solder mask 204 is disposed above the substrate 202. The device 208 is coupled to a first surface of the substrate 202 such that a portion of the device 208 contacts the solder mask 204. For example, (i) a first corner of device 208 may rest on and / or contact the first recess 240a of solder resist 204, (ii) a second corner of device 208 may rest on and / or contact the second recess 240b of solder resist 204, (iii) a third corner of device 208 may rest on and / or contact the third recess 240c of solder resist 204, and / or (iv) a fourth corner of device 208 may rest on and / or contact the fourth recess 240d of solder resist 204. The solder resist 204 (particularly the recesses (e.g., 240a-240d)) is configured as a component for providing horizontal support, which helps prevent excessive tilting of device 208. In some implementations, using solder mask 204 as a base plane for device 208 helps keep the surface of device 208 within 2 degrees or less parallel to the first surface of substrate 202. Thus, for example, solder mask 205 can help prevent device 208 from tilting more than 2 degrees from substrate 202.

[0040] Figure 3 The illustration shows device 208 positioned above substrate 202 and solder mask 204, such that at least one gap exists between the surface of device 208 and the surface of solder mask 204. For example, Figure 3The illustration shows a first gap 310, a second gap 312, a third gap 314, and a fourth gap 316 between the lateral surface (e.g., side surface) of device 208 and the surface (e.g., lateral surface) of solder mask 204. As will be further described below, one or more gaps (e.g., 310, 312, 314, 316) may be configured to allow encapsulation layer 209 to be formed between device 208 and substrate 202 (e.g., in spaces not yet occupied by interconnects and solder mask 204).

[0041] Figure 3 The illustration shows an encapsulation layer 209 formed over a substrate 202 and a solder mask 204, such that the encapsulation layer 209 encapsulates a device 208. For example, the encapsulation layer 209 may be located over the solder mask 204, such that the encapsulation layer 209 encapsulates the device 208. The encapsulation layer 209 may be formed and located within and around gaps (e.g., 310, 312, 314, 316). The encapsulation layer 209 may be formed and located between the substrate 202 and the surface (e.g., the bottom surface) of the device 208. In some implementations, the encapsulation layer 209 may be provided between the device 208 and the substrate 202 through one or more gaps (e.g., 310, 312, 314, 316). In some implementations, the encapsulation layer 209 is provided such that the space between the device 208 and the substrate 202 is substantially free of voids (e.g., air gaps). The absence of voids may mean that voids represent five percent (5%) or less of the space between device 208 and substrate 202. This is possible because encapsulation layer 209 can enter and be disposed in the unoccupied space between substrate 202 and device 208 through one or more gaps. When device 208 includes RF components sensitive to different materials, it may be important to reduce, minimize, and / or eliminate the voids between substrate 202 and device 208. Encapsulation layer 209 and voids have different properties, which may affect the performance of device 208. For example, a portion of device 208 near a void may perform differently than another portion of device 208 near encapsulation layer 209. To provide a consistently performing device 208, it may be important to ensure that the voids between substrate 202 and device 208 are reduced, minimized, and / or eliminated. In some implementations, five percent (5%) or less of voids exist in the space between substrate 202 and device 208. The solder mask 204 and interconnects (e.g., 205, 206, 207) between the substrate 202 and the device 208 should not be considered as voids.

[0042] Shielding element 210 may be formed above the surface of encapsulation layer 209, the side surface of solder resist layer 204, and / or the side surface of substrate 202. Shielding element 210 may be an electromagnetic interference (EMI) shielding element. Shielding element 210 may be a component for shielding (e.g., a component for EMI shielding). Shielding element 210 may be configured as a Faraday cage. Shielding element 210 may include a conductive material (e.g., a metal). Shielding element 210 may be coupled to ground. Shielding element 210 may be patterned.

[0043] Figure 4 The diagram illustrates the outline of the AA section spanning package 200. (See figure.) Figure 4 As shown, device 208 is located above substrate 202 and solder mask 204, such that solder mask 204 is configured as a base plane for device 208. Figure 4 As shown, device 208 is positioned above solder mask 204, such that a portion of device 208 contacts solder mask 204. In this example, a first corner of device 208 contacts a first recess 240a of solder mask 204, and a second corner of device 208 contacts a fourth recess 240d. This configuration allows device 208 to be as parallel as possible to substrate 202. For example, this configuration allows the surface of device 208 (e.g., bottom surface, top surface) to be as parallel as possible to the surface of substrate 202. In some implementations, device 208 and / or the surface of device 208 are within 2 degrees of parallelness to substrate 202 and / or the surface of substrate 202. The tilt angle of device 208 relative to substrate 202 can be approximately 2 degrees or less.

[0044] Figure 5 The diagram illustrates the profile of the BB cross-section across package 200. (See figure.) Figure 5 As shown, device 208 is located above substrate 202. Device 208 is electrically coupled to the substrate via interconnects (205, 206, 207). Device 208 is located above substrate 202 such that at least one gap (e.g., a second gap 312, a fourth gap 316) exists between device 208 and solder mask 204. The gaps(multiple) are configured to allow encapsulation layer 209 to be formed below device 208 and between device 208 and substrate 202. The gaps(multiple) may have a width of at least 15 micrometers (μm). In some implementations, the gaps(multiple) (e.g., 310, 312, 314, 316) may have a width in the range of approximately 15 to 60 micrometers (μm).

[0045] Figure 4 and Figure 5 The illustration shows a shield 210 formed above the surface of the encapsulation layer 209 (e.g., the outer surface), the side surface of the solder mask layer 204, and / or the side surface of the substrate 202. The shield 210 may be patterned.

[0046] Figure 6 The diagram illustrates a plan view of how device 208 can be positioned above substrate 202 and solder mask layer 204. Figure 6 As shown, in one example, device 208 may be positioned above substrate 202 and solder mask 204 such that (i) a first corner of device 208 may rest on and / or contact the first recess 240a of solder mask 204, (ii) a second corner of device 208 may rest on and / or contact the second recess 240b of solder mask 204, (iii) a third corner of device 208 may rest on and / or contact the third recess 240c of solder mask 204, and / or (iv) a fourth corner of device 208 may rest on and / or contact the fourth recess 240d of solder mask 204. Furthermore, device 208 can be positioned above substrate 202 and solder mask 204, such that a first gap 310, a second gap 312, a third gap 314, and a fourth gap 316 exist to allow encapsulation layer 209 to enter and be disposed between device 208 and substrate 202. The first gap 310, the second gap 312, the third gap 314, and / or the fourth gap 316 can be filled with encapsulation layer 209.

[0047] Using a solder mask layer configured as a base plane provides several technical advantages, such as (i) reducing, minimizing and / or eliminating device tilt or excessive tilt relative to the substrate, (ii) reducing, minimizing and / or eliminating voids or excessive voids between the substrate and the device, (iii) reducing, minimizing and / or eliminating changes in device height due to tilt, (iv) reducing, minimizing and / or eliminating inconsistencies in the encapsulation layer between the substrate and the device, and / or (v) reducing, minimizing and / or eliminating changes in device performance.

[0048] Figures 2-6 An example of a patterned solder mask layer 204 is illustrated. However, different implementations may use solder mask layers with different patterns and / or openings. Figures 7-12 Various solder mask layers with different patterns and / or openings are illustrated, which can be implemented using package 200 or any package described in this disclosure. Figures 7-12 The illustration also shows how device 208 can contact and / or rest on various solder mask layers.

[0049] Figure 7The illustration shows a solder mask layer 704 including a first recess 240a, a second recess 740a, a third recess 740b, and a fourth recess 240d. The second recess 740a and the third recess 740b may have different dimensions than the first recess 240a and the fourth recess 240d.

[0050] Figure 8 The illustration shows a solder mask layer 804 including a first recess 840a, a second recess 840b, a third recess 840c, and a fourth recess 840d. The first recess 840a, the second recess 840b, the third recess 840c, and the fourth recess 840d may have curved and / or arcuate shapes. The dimensions of the recesses may be the same or different.

[0051] Figure 9 The diagram illustrates a solder mask layer 904 including a first recess 240a, a fourth recess 240d, and a first portion 940a. One or more portions of the device 208 may contact the first recess 240a, the fourth recess 240d, and / or the first portion 940a. Figure 10 The diagram illustrates a solder mask layer 1004 including a first portion 940a and a second portion 1040a. One or more portions of the device 208 may contact the first portion 940a and / or the second portion 1040a.

[0052] Figure 11 The diagram illustrates a solder mask layer 1104, which includes a first island 1140a (e.g., a solder mask island), a second island 1140b (e.g., a solder mask island), a third island 1140c, and a fourth island 1140d. One or more portions of device 208 may contact the first island 1140a, the second island 1140b, the third island 1140c, and / or the fourth island 1140d.

[0053] Figure 12 The diagram illustrates a solder mask layer 1204 comprising a first island 1240a and a second island 1240b. The first island 1240a and the second island 1240b have a rectangular shape. One or more portions of the device 208 may contact the first island 1240a and / or the second island 1240b.

[0054] It should be noted that different implementations may use solder mask layers with different combinations of recesses, planes, and / or islands. Furthermore, the positions of the recesses, planes, and / or islands may vary. The number of recesses, planes, and / or islands may also vary. The size and / or shape of the recesses, planes, and / or islands may also vary.

[0055] Figures 2-6 The illustration shows a package 200 including device 208. It should be noted that package 200 may include several components, such as other devices, dies, integrated devices, capacitors and / or inductors. Figure 13The illustration shows a package 1300 comprising several devices 1308, a capacitor 1318, a solder mask 204, and devices 208. Package 1300 may include similar or identical components to those of package 300. Device 1308 may include a die and / or an integrated device. Device 208 is positioned over solder mask 204 such that a portion of device 208 lies over a recess (e.g., 240a-240d). Solder mask 204 of package 1300 may be configured as a base plane for device 208.

[0056] Various packages including a solder mask layer configured as a base plane for a device have been described. The sequence for manufacturing a package including a solder mask layer configured as a base plane for a device will now be described below.

[0057] An exemplary sequence for manufacturing a package including a solder mask layer configured as a base plane for a device.

[0058] Figure 14 (including) Figures 14A-14D The illustration depicts an exemplary sequence for providing or manufacturing a package including a solder mask layer configured as a base plane for a device. In some implementations, Figures 14A-14D The order can be used to provide or manufacture Figure 3 The package 200 or any package described in this disclosure.

[0059] It should be noted that, Figures 14A-14D The sequence of processes can be combined into one or more stages to simplify and / or clarify the sequence for providing or manufacturing a package including a solder mask layer configured as a base plane for a device. In some implementations, the sequence of processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the spirit of this disclosure. However, different implementations can manufacture the package in different ways.

[0060] Phase 1, such as Figure 14A The diagram illustrates the state of substrate 202 after it has been provided. Substrate 202 may include one or more dielectric layers and multiple interconnects. Substrate 202 may include silicon. Substrate 202 may be fabricated. In some implementations, fabricating substrate 202 may include using a semi-additive process (SAP) and / or a modified semi-additive process (mSAP).

[0061] Phase 2 illustrates the state after the solder mask 204 has been disposed (e.g., formed) over the substrate 202. The solder mask 204 can be configured to operate as a base plane for a device (e.g., 208). The solder mask 204 includes recesses (e.g., 240a-240d). Different implementations may use solder mask layers with different patterns and / or openings, such as... Figures 7 to 12 The solder mask layer described herein may include recesses, planar surfaces, and / or islands.

[0062] Phase 3, such as Figure 14B The illustration shows a state after the substrate interconnect 205 has been disposed (e.g., formed) over the substrate 202. The substrate interconnect 205 can be formed using an electroplating process. In some implementations, the substrate interconnect 205 may be disposed before the solder mask layer 204 is formed over the substrate 202. In some implementations, the substrate 202 may include the substrate interconnect 205 when the substrate 202 is provided in stage 1.

[0063] Phase 4 illustrates the state after the solder interconnect 206 has been disposed (e.g., formed) over the substrate interconnect 205. The solder interconnect 206 can be formed over the substrate interconnect 205 using an electroplating process.

[0064] Phase 5 illustrates the state after device interconnect 207 is disposed (e.g., formed) over solder interconnect 206. Electroplating processes can be used to form device interconnect 207 over solder interconnect 206. In some implementations, device interconnect 207 can be considered part of device 208. In this case, device interconnect 207 can be coupled to solder interconnect 206 while device 208 is coupled to substrate 202 and solder mask 204.

[0065] Phase 6, such as Figure 14CThe diagram illustrates a state where device 208 is coupled to substrate 202 and solder mask layer 204. Device 208 can be coupled via pick-and-place processes. Device 208 can be configured to be electrically coupled to device interconnect 207, solder interconnect 206, and substrate interconnect 205. Device 208 is positioned above substrate 202 and solder mask 204 such that (i) a first corner of device 208 can rest on and / or contact the first recess 240a of solder mask 204, (ii) a second corner of device 208 can rest on and / or contact the second recess 240b of solder mask 204, (iii) a third corner of device 208 can rest on and / or contact the third recess 240c of solder mask 204, and / or (iv) a fourth corner of device 208 can rest on and / or contact the fourth recess 240d of solder mask 204.

[0066] As shown in stage 6, the recesses of the solder mask layer 204 are configured as a base plane for the device 208, which helps to reduce, minimize and / or eliminate the tilt of the device 208 relative to the substrate 202.

[0067] Furthermore, device 208 can be positioned above substrate 202 and solder mask 204 such that a first gap 310, a second gap 312, a third gap 314, and a fourth gap 316 exist between the surface of device 208 and the surface of solder mask 204. As will be further described below, the gaps (e.g., 210, 312, 314, 316) can be used to allow the encapsulation layer to travel beneath device 208, thereby reducing, minimizing, and / or eliminating the gap between device 208 and substrate 202.

[0068] Device 208 may include radio frequency (RF) devices, dies, integrated devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, and / or combinations thereof. Device 208 may be an assembly of components and / or devices.

[0069] Phase 7 illustrates the state after the encapsulation layer 209 is formed over the substrate 202, the solder mask 204, and the device 208. The encapsulation layer 209 is formed such that it encapsulates the device 208. Furthermore, the encapsulation layer 209 can be formed and located in gaps (e.g., 310, 312, 314, 316) and between the substrate 202 and the device 208. Different implementations may provide and form the encapsulation layer 209 differently. Some implementations may use compression and transfer molding, sheet molding, or liquid molding processes to provide and form the encapsulation layer 209. Phase 7 may illustrate an example of a package 200 including a solder mask configured as a base plane for a device.

[0070] Phase 8, such as Figure 14D The diagram illustrates the state after shielding 210 is formed above encapsulation layer 209. Shielding 210 may be an EMI shield. Shielding 210 may include one or more conductive materials (e.g., metal). Shielding 210 may be formed above the side surface of solder resist layer 204 and / or the side surface of substrate 202. Electroplating and / or sputtering processes may be used to form shielding 210. Shielding 210 may be a patterned shield. Shielding 210 may be formed such that shielding 210 is configured to be coupled to ground. Stage 8 may illustrate an example of a package 200 including a solder resist layer configured as a base plane for a device.

[0071] An exemplary flowchart of a method for manufacturing a package including a solder mask layer configured as a base plane for a device.

[0072] In some implementations, manufacturing a package that includes a solder mask layer configured as a base plane for a device involves several processes. Figure 15 An exemplary flowchart of a method 1500 for providing or manufacturing a package is illustrated, the package including a solder mask layer configured as a base plane for a device. Figure 15 Method 1500 can be used to provide or manufacture the method described in this disclosure. Figure 3 Package 200. However, method 1500 can be used to provide or manufacture any package described in this disclosure.

[0073] It should be noted that, Figure 15The order of processes can be combined to simplify and / or clarify the method for providing or manufacturing a package including a solder mask layer configured as a base plane for a device. In some implementations, the order of processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the spirit of this disclosure. However, different implementations can manufacture the package in different ways.

[0074] The method provides a substrate (e.g., 202) at 1505. Substrate 202 may include one or more dielectric layers and multiple interconnects. Substrate 202 may include a first surface and a second surface. Substrate 202 may be fabricated. In some implementations, fabricating substrate 202 may include using a semi-additive process (SAP) and / or a modified semi-additive process (mSAP).

[0075] The method involves forming a solder resist layer (e.g., 204) above a first surface of a substrate (e.g., 202) at 1510. The pattern and / or openings of the solder resist layer can vary with different implementations. Figure 14A Phase 2 illustrates an example of a solder mask 204 disposed (e.g., formed) over a substrate 202. The solder mask 204 can be configured to operate as a base plane for a device (e.g., 208). The solder mask 204 includes recesses (e.g., 240a-240d). Different implementations may use solder mask layers with different patterns and / or openings, such as... Figures 7-12 The solder mask layer described herein. The solder mask layer may include recesses, planes, islands, and / or combinations thereof.

[0076] The method forms a substrate interconnect (e.g., 205) over the substrate 202 (at 1515). Figure 14B Phase 3 illustrates an example of a substrate interconnect 205 disposed (e.g., formed) over a substrate 202. The substrate interconnect 205 can be formed using an electroplating process. In some implementations, the substrate interconnect 205 may be disposed before the solder mask 204 is formed over the substrate 202. In some implementations, when the substrate 202 is... Figure 14A When phase 1 is provided, substrate 202 may include substrate interconnect 205.

[0077] This method forms solder interconnects (e.g., 206) over substrate interconnects 205 (at 1520). Figure 14B Stage 4 illustrates an example of solder interconnect 206 disposed (e.g., formed) over substrate interconnect 205. The solder interconnect 206 can be formed over substrate interconnect 205 using an electroplating process.

[0078] This method forms a device interconnect (e.g., 207) over the solder interconnect 206 (at 1525). Figure 14B Phase 5 illustrates an example of a device interconnect 207 disposed (e.g., formed) over solder interconnect 206. Electroplating processes can be used to form the device interconnect 207 over solder interconnect 206. In some implementations, device interconnect 207 may be considered part of device 208. In this case, device interconnect 207 can be coupled to solder interconnect 206 while device 208 is coupled to substrate 202 and solder mask 204.

[0079] This method couples a device (e.g., 208) to a substrate (at 1530) such that at least a portion of the device is located above and in contact with the solder resist layer. Figure 14C Phase 6 illustrates an example of a device 208 coupled to a substrate 202 and a solder mask layer 204. Device 208 can be coupled to the substrate via a pick-and-place process.

[0080] Device 208 can be configured to be electrically coupled to device interconnect 207, solder interconnect 206, and substrate interconnect 205. Device 208 is positioned above substrate 202 and solder mask 204 such that (i) a first corner of device 208 can rest on and / or contact the first recess 240a of solder mask 204, (ii) a second corner of device 208 can rest on and / or contact the second recess 240b of solder mask 204, (iii) a third corner of device 208 can rest on and / or contact the third recess 240c of solder mask 204, and / or (iv) a fourth corner of device 208 can rest on and / or contact the fourth recess 240d of solder mask 204.

[0081] The recesses of the solder mask layer 204 are configured as a base plane for the device 208, thereby reducing, minimizing and / or eliminating the tilt of the device 208 relative to the substrate 202.

[0082] Device 208 can be positioned above substrate 202 and solder mask 204 such that a first gap 310, a second gap 312, a third gap 314 and a fourth gap 316 exist between the surface of device 208 and the surface of solder mask 204.

[0083] Device 208 may include radio frequency (RF) devices, dies, integrated devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, and / or combinations thereof. Device 208 may be an assembly of components and / or devices.

[0084] This method forms an encapsulation layer (e.g., 209) over the solder mask layer 204 and / or the substrate 202 (at location 1535), such that the encapsulation layer encapsulates the device 208. Figure 14C Phase 7 illustrated here shows an example of an encapsulation layer 209 formed over substrate 202, solder mask 204, and device 208. The encapsulation layer 209 is formed such that it encapsulates device 208. Furthermore, the encapsulation layer 209 may be formed and located in gaps (e.g., 310, 312, 314, 316) and between substrate 202 and device 208. The gaps (e.g., 210, 312, 314, 316) may be used to allow the encapsulation layer to travel beneath device 208, thereby reducing, minimizing, and / or eliminating the void between device 208 and substrate 202. Different implementations can provide and form the encapsulation layer 209. Some implementations may use compression and transfer molding processes, sheet molding processes, or liquid molding processes to provide and form the encapsulation layer 209.

[0085] The method forms a shield (e.g., 210) above the surface of the encapsulation layer (e.g., 209) (at 1540). Figure 14D Phase 8 illustrates an example of a shield 210 formed over an encapsulation layer 209. The shield 210 may be an EMI shield. The shield 210 may comprise one or more conductive materials (e.g., metals). The shield 210 may be formed above the side surface of the solder mask layer 204 and / or the side surface of the substrate 202. The shield 210 may be formed using electroplating and / or sputtering processes. The shield 210 may be a patterned shield. The shield 210 may be formed such that it is configured to be coupled to ground.

[0086] Exemplary electronic devices

[0087] Figure 16 The illustrations depict various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1602, laptop computer device 1604, fixed-location terminal device 1606, wearable device 16016, or autonomous vehicle 1610 may include device 1600 as described herein. For example, device 1600 may be any device and / or package described herein. Figure 16The electronic devices 1602, 1604, 1606, and 16016 and vehicle 1610 illustrated herein are merely exemplary. Other electronic devices may also feature device 1600, including but not limited to combinations of devices (e.g., electronic devices), such as: mobile devices, handheld personal communication system (PCS) units, portable data units such as personal digital assistants, devices supporting Global Positioning System (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in autonomous vehicles (e.g., self-driving cars), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0088] exist Figures 2-13 , Figures 14A-14D and / or Figures 15-16 One or more components, processes, features, and / or functions illustrated in the diagram may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from this disclosure. It should also be noted that... Figures 2-13 , Figures 14A-14D and / or Figures 15-16 The corresponding descriptions herein are not limited to dies and / or ICs. In some implementations, Figures 2-13 , Figures 14A-14D and / or Figures 15-16 The descriptions and their corresponding information can be used to manufacture, create, supply, and / or produce devices and / or integrated devices. In some implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0089] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior or advantageous to other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” as used herein refers to direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. The term “encapsulation” means that an object can partially or completely encapsulate another object. It should also be noted that the term “above,” as used in the context of one component being above another component in this application, can be used to mean a component on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, a first component above a second component may mean: (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is (e.g., embedded in) the second component. The terms “approximately 'X value'” or “approximately X value” as used in this disclosure mean within 10% of the “X value”. For example, a value of approximately 1 or approximately 1 would mean a value in the range of 0.9–1.1.

[0090] In some implementations, interconnects are elements or components of a device or package that allow or facilitate electrical connections between two points, elements, and / or components. In some implementations, interconnects may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. Interconnects may include one or more metal components (e.g., a seed layer + metal layer). In some implementations, interconnects are conductive materials that can be configured to provide an electrical path for a signal (e.g., a data signal, ground, or power supply). Interconnects may be part of a circuit. Interconnects may include more than one element or component. Interconnects may be defined by one or more interconnects. Different implementations may use similar or different processes to form interconnects. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or electroplating processes may be used to form interconnects. Processes for forming and / or mounting encapsulation layers may include compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0091] Furthermore, it should be noted that the various disclosures included herein can be described as processes depicted as flowcharts, diagrams, structure diagrams, or block diagrams. Although a flowchart can describe operations as a sequential process, many operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0092] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The descriptions of various aspects of this disclosure are intended to be illustrative and not to limit the scope of the claims. Thus, this teaching can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: Substrate, including a first surface; A solder resist layer is coupled to the first surface of the substrate, the solder resist layer having a plurality of sides, the sides defining an internal opening in the solder resist layer, the internal opening being surrounded by the plurality of sides of the solder resist layer; The internal opening contains no solder resist material, and the solder resist layer includes at least one recess at the periphery of the internal opening, the at least one recess being formed from the solder resist layer and forming a protrusion in the internal opening; A device located above the solder mask layer such that a portion of the device contacts the solder mask layer, the portion of the device including at least one corner of the device that contacts the at least one recess; One or more interconnects are configured to provide one or more electrical paths between the substrate and the device, the one or more interconnects being located within the internal opening between the device and the substrate, wherein there is a gap between the one or more interconnects and the solder mask layer within the internal opening; as well as An encapsulation layer is located above the solder mask layer, thereby encapsulating the device.

2. The package of claim 1, wherein the solder mask is configured as a base plane for the device.

3. The package of claim 1, wherein the device is located above the solder mask layer such that the surface of the device facing the substrate is within 2 degrees parallel to the first surface of the substrate.

4. The package of claim 1, wherein the encapsulation layer is further located between the device and the substrate within the internal opening of the solder mask layer.

5. The package of claim 1, wherein the encapsulation layer is located between the device and the substrate such that the space between the device and the substrate is substantially free of gaps.

6. The package of claim 1, further comprising a lateral gap between one side of the device and one of the plurality of sides of the solder mask, wherein the lateral gap is filled with the encapsulation layer.

7. The package of claim 1, wherein the device comprises a radio frequency (RF) device, a die, an integrated device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, and / or combinations thereof.

8. The package of claim 1, wherein the package is incorporated into a unit selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and components in autonomous vehicles.

9. The package of claim 1, wherein the edge of the device extends beyond each side of the one or more interconnects.

10. The package of claim 1, wherein the device has a device surface facing the first surface of the substrate, wherein the device surface includes a portion of the device that contacts the solder resist layer, wherein a second portion of the device surface that does not contact the solder resist layer has a larger area than the portion of the device that contacts the solder resist layer.

11. The package of claim 1, wherein the solder mask includes at least one additional recess at the periphery of the internal opening formed from the solder mask, and the recess forms another protrusion in the internal opening, wherein the portion of the device contacting the solder mask further includes at least one additional angle of the device contacting the at least one additional recess.

12. An apparatus comprising: Substrate, including a first surface; A component for providing horizontal support coupled to the first surface of the substrate, the component for providing horizontal support having a plurality of sides defining an internal opening in the component for providing horizontal support, the internal opening being surrounded by the plurality of sides of the component for providing horizontal support; the internal opening containing no material of the component for providing horizontal support, the component for providing horizontal support including at least one recess at the periphery of the internal opening, the at least one recess being formed from the component for providing horizontal support and forming a protrusion in the internal opening; A device, the device being positioned above the component for providing horizontal support, such that a portion of the device contacts the component for providing horizontal support, the portion of the device including at least one corner of the device that contacts the at least one recess; One or more interconnects are configured to provide one or more electrical paths between the substrate and the device, the one or more interconnects being located within the internal opening between the device and the substrate, wherein within the internal opening, there is a gap between the one or more interconnects and the component for providing horizontal support; as well as A component for encapsulation, located above the component for providing horizontal support, such that the component for encapsulation encapsulates the device.

13. The apparatus of claim 12, wherein the component for providing horizontal support is configured as a base plane for the device.

14. The apparatus of claim 12, wherein the device is positioned above the component for providing horizontal support such that the surface of the device facing the substrate is within 2 degrees parallel to the first surface of the substrate.

15. The apparatus of claim 12, wherein the encapsulation component is further located between the device and the substrate.

16. The apparatus of claim 12, wherein the encapsulation component is located between the device and the substrate such that the space between the device and the substrate is substantially free of gaps.

17. The apparatus of claim 12, further comprising a lateral gap between one side of the device and one of the plurality of sides of the component for providing horizontal support.

18. The apparatus of claim 12, wherein the device comprises a radio frequency (RF) device, a die, an integrated device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, and / or combinations thereof.

19. The apparatus of claim 12, wherein the apparatus is incorporated into a unit selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and components in autonomous vehicles.

20. A method for manufacturing a package, comprising: Provide a substrate including a first surface; A solder resist layer is formed above the first surface of the substrate. The solder resist layer is formed to have a plurality of sides, each side defining an internal opening in the solder resist layer. The internal opening is surrounded by the plurality of sides of the solder resist layer. The internal opening does not contain any solder resist material. The solder resist layer is formed to include at least one recess at the periphery of the internal opening. The at least one recess is formed from the solder resist layer and forms a protrusion in the internal opening. One or more interconnects are formed, the one or more interconnects being configured to provide one or more electrical paths between the substrate and the device, the one or more interconnects being formed within the internal opening between the device and the substrate, wherein there is a gap between the one or more interconnects and the solder mask layer within the internal opening; The device is coupled to the substrate such that the device is located above the solder mask and a portion of the device contacts the solder mask, the portion of the device including at least one corner of the device that contacts the at least one recess; as well as An encapsulation layer is formed over the solder mask layer, thereby encapsulating the device.

21. The method of claim 20, wherein the solder mask is configured as a base plane for the device.

22. The method of claim 20, wherein the device is coupled over the solder mask layer such that the surface of the device facing the substrate is within 2 degrees parallel to the first surface of the substrate.

23. The method of claim 20, wherein the encapsulation layer is formed such that the encapsulation layer is also located between the device and the substrate.

24. The method of claim 20, wherein the encapsulation layer is formed such that the encapsulation layer is located between the devices and the space between the devices and the substrate is substantially free of voids.

25. The method of claim 20, wherein the device is coupled to the substrate such that a lateral gap exists between one side of the device and one of the plurality of sides of the solder mask layer.

26. The method of claim 20, wherein the device comprises a radio frequency (RF) device, a die, an integrated device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, and / or combinations thereof.

27. An apparatus comprising: Substrate, including a first surface; A solder resist layer is coupled to the first surface of the substrate. The solder resist layer has a plurality of sides, each side defining an internal opening within the solder resist layer, the internal opening being surrounded by the plurality of sides. The internal opening contains no solder resist material. The solder resist layer further has: A first recess is formed from the solder mask layer and protrudes into the internal opening; A second recess is formed from the solder mask layer and protrudes into the internal opening; A third recess is formed from the solder mask layer and protrudes into the internal opening; as well as A fourth recess is formed from the solder mask layer and protrudes into the internal opening; A device is located above the solder mask layer such that a first corner of the bottom surface of the device facing the substrate contacts the first recess, a second corner of the bottom surface of the device contacts the second recess, a third corner of the bottom surface of the device contacts the third recess, and a fourth corner of the bottom surface of the device contacts the fourth recess, wherein a first side of the device different from the bottom surface has a first lateral gap with a first side of the plurality of sides of the solder mask layer, and wherein a second side of the device different from the bottom surface has a second lateral gap with a second side of the plurality of sides of the solder mask layer; One or more interconnects are configured to provide one or more electrical paths between the substrate and the device, the one or more interconnects being located within the internal opening; as well as An encapsulation layer is located above the solder resist layer and within the first lateral gap and the second lateral gap, and within the internal opening between the device and the substrate.

28. The apparatus of claim 27, wherein the solder mask layer is configured as a support surface of the device.

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