Method and device for improving FPGA prototype verification efficiency

Abstract

The present invention discloses a method and device for improving the efficiency of FPGA prototype verification. The method comprises: running a design synthesis command to obtain a netlist file after the design synthesis is completed; running a report_qor_assessment command to obtain a current report; detecting a report score and determining the relationship between the score and a preset threshold; if the score is less than the preset threshold, detecting the design and repeating the above steps; and if the score is greater than or equal to the preset threshold, continuing to perform clock relationship judgment, timing result judgment, combinational logic chain level threshold judgment, and fan-out threshold judgment to generate a new synthesis strategy and implementation strategy. In the FPGA prototype verification implementation process, after design synthesis, this method can automatically analyze and report the fan-out, logic level, clock relationship, and timing results, compare them with set parameters, and generate an effective implementation strategy, thereby improving the correctness of FPGA prototype verification implementation and improving the efficiency of prototype verification.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method and device for improving FPGA prototype verification efficiency. Background Art

[0002] FPGA (field-programmable gate array) prototyping is a technology used to verify the functions and performance of application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), and systems on a chip (SoCs) by porting RTL (resistor transistor logic) to a field-programmable gate array (FPGA). Prototype verification is a necessary verification process to check whether the chip is consistent with the expected results before tape-out. Due to the high cost of direct tape-out, the usual approach is to port, synthesize, and perform layout and routing on the FPGA prototype verification platform. FPGAs are programmable and can be repeatedly modified and implemented until the expected results are achieved, avoiding the high cost and high risk of multiple tape-outs. A prototype verification platform needs to be built before prototype verification is performed. The following are the main difficulties in the FPGA prototype verification process:

[0003] First, FPGA prototype verification cannot be completely consistent with ASIC design. It is necessary to modify the clock, memory, specific IP and other parts into files that can be synthesized by FPGA. There are many of these modules, and the replacement process is tedious and error-prone.

[0004] Secondly, FPGA prototype verification is the verification link of ASIC design, which will be iterated repeatedly according to the design needs, and the whole process will be repeated many times.

[0005] Thirdly, FPGA prototyping is limited by the FPGA's logic resources. Designs are large and implementation takes a long time. Chip frequencies are generally above 1 GHz, while clock frequencies in FPGA prototyping are around tens of MHz. This makes design implementation time very long, and timing closure is a key criterion for determining the usability of implementation results. Therefore, achieving timing closure and correct implementation is a significant challenge as designs grow larger. Summary of the Invention

[0006] In light of this, the present invention aims to provide a method for improving the efficiency of FPGA prototype verification. This method, after design synthesis, automatically analyzes and reports fanout, logic level, clock relationships, and timing results, comparing them with set parameters and generating an effective implementation strategy. This method improves the accuracy and efficiency of FPGA prototype verification.

[0007] Based on the above objectives, one aspect of an embodiment of the present invention provides a method for improving FPGA prototype verification efficiency. The method for improving FPGA prototype verification efficiency includes: running a design synthesis command to obtain a netlist file after the design synthesis is completed; running the report_qor_assessment command to obtain the current report; detecting the report score and determining the relationship between the score and a preset threshold; if the score is less than the preset threshold, testing the design and repeating the above steps; and if the score is greater than or equal to the preset threshold, continuing to perform clock relationship determination, timing result determination, combinational logic chain level threshold determination, and fan-out threshold determination to generate a new synthesis strategy and implementation strategy.

[0008] In some implementations, clock relationship determination includes: executing a report_clock_interaction command to obtain a clock relationship; determining whether an unexpected synchronous clock path exists; if so, adding an asynchronous timing constraint file to resolve the problem; and if not, continuing with timing result determination.

[0009] In some implementations, adding an asynchronous timing constraint file to resolve the issue includes: if there is an unexpected synchronous clock path, use

[0010] set_false_path-from[get_clocks clk1]-to[get_clocks clk2]

[0011] set_false_path-from[get_clocks clk2]-to[get_clocks clk1]

[0012] Eliminate undesirable synchronous clock relationships.

[0013] In some implementations, timing result determination includes: executing the report_timing_summary command to obtain a timing report; determining whether the timing result has converged; if not, establishing a hold time violation process; and if converged, performing a combinational logic chain level threshold determination.

[0014] In some embodiments, setting up hold time violation handling includes picking the worst timing path and optimizing it until convergence if timing does not converge.

[0015] In some embodiments, the threshold determination of the number of combinational logic chain levels includes: running the report_design_analysis command to obtain the number of combinational logic chain levels; determining the threshold range of the number of combinational logic chain levels; if it exceeds the threshold range, re-performing the timing constraints; if it does not exceed the threshold range, modifying the timing constraints or modifying the synthesis strategy to retiming00c synthesis.

[0016] In some implementations, run report_design_analysis-logic_level_distribution-logic_level_dist_paths 1000 to obtain the combinational logic levels of the current 1000 paths;

[0017] At a frequency of 50 MHz, the delay of a combinational logic is 0.5 ns, and the corresponding combinational logic level threshold is 40 levels;

[0018] If the number of combinational logic levels is greater than 40, re-perform timing constraints;

[0019] If the number of combinational logic levels is less than or equal to 40, the synthesis strategy is modified to retiming 00c synthesis.

[0020] In some implementations, fanout threshold determination includes: running report_high_fanout_nets to obtain fanout; determining a fanout threshold; if the fanout threshold is exceeded, selecting a corresponding optimization strategy in an implementation phase; if the fanout threshold is not exceeded, generating a new synthesis strategy and implementation strategy.

[0021] In some implementations, selecting a corresponding optimization strategy in the implementation phase includes: processing opt_design merge_equivalent_drivers hier_fanout_limit 512 in the implementation phase; or phys_opt_design-force_replication_on_nets[get_nets net_name].

[0022] Another aspect of the present invention provides an apparatus for improving FPGA prototype verification efficiency. The apparatus includes a design unit for designing synthesis strategies and implementation strategies; an operation analysis unit for obtaining and testing reports using the report_qor_assessment command; a clock relationship determination unit for obtaining and subsequently testing clock relationships using the report_clock_interaction command; a timing result determination unit for obtaining and testing timing reports using the report_timing_summary command; a combinational logic chain level threshold determination unit for obtaining and testing combinational logic chain level thresholds using the report_design_analysis command; and a fanout threshold determination unit for obtaining and testing fanout signal reports using the report_high_fanout_nets command.

[0023] In some embodiments, the design unit completes the synthesis of the design using a default synthesis strategy, opens the synthesized design, and runs a design synthesis command to obtain a netlist file after the design synthesis is completed.

[0024] In some embodiments, the analysis unit may execute report_qor_assessment to obtain a score between 1 and 5, and the convergence is determined based on the difference between the score and a preset threshold.

[0025] In some embodiments, the clock relationship judgment unit executes the report_clock_interaction command to obtain the clock relationship; judges whether there is an unexpected synchronous clock path; if so, adds an asynchronous timing constraint file to solve it; and if not, continues to judge the timing result.

[0026] In some embodiments, the timing result judgment unit runs the report_timing_summary command to obtain a timing report; judges whether the timing result converges; if not, establishes a hold time violation process; if converged, performs a combinational logic chain level threshold judgment.

[0027] In some embodiments, the combinational logic chain level threshold judgment unit runs the report_design_analysis command to obtain the combinational logic chain level; judges the threshold range of the combinational logic chain level; if it exceeds the threshold range, re-performs the timing constraints; if it does not exceed the threshold range, modifies the timing constraints or modifies the synthesis strategy to retiming 00c synthesis.

[0028] In some embodiments, the fanout threshold determination unit executes the report_high_fanout_nets command to obtain the fanout; determines the fanout threshold; if the fanout threshold is exceeded, selects a corresponding optimization strategy in the implementation phase; if the fanout threshold is not exceeded, generates a new synthesis strategy and implementation strategy.

[0029] In another aspect of an embodiment of the present invention, a computer device is provided, comprising: at least one processor; and a memory, wherein the memory stores computer instructions that can be run on the processor, and the steps of implementing a method when the instructions are executed by the processor include: running a design synthesis command to obtain a netlist file after the design synthesis is completed; running the report_qor_assessment command to obtain the current report; detecting the report score and determining the relationship between the score and a preset threshold; if the score is less than the preset threshold, detecting the design and repeating the above steps; and if the score is greater than or equal to the preset threshold, continuing to perform clock relationship judgment, timing result judgment, combinational logic chain level threshold judgment, and fan-out threshold judgment to generate a new synthesis strategy and implementation strategy.

[0030] According to another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, which stores a computer program that implements the above method steps when executed by a processor.

[0031] The present invention has at least the following beneficial technical effects:

[0032] The present invention uses the default synthesis strategy to complete the design synthesis. Open the synthesized design, run the design synthesis command to obtain the netlist file after the design synthesis is completed, and run report_qor_assessment to obtain a score between 1 and 5. The higher the score, the easier it is for the design timing to converge. Next, read the timing report to analyze the clock relationship and timing results of the design, for example, to check whether there are unexpected synchronous clock paths. If so, eliminate the unexpected clock relationship. Next, analyze the timing violation paths with large deviations. When the violation exceeds the set parameters, stop in time. Within the parameter range, retiming synthesis or physical optimization options for establishing hold time can be adopted. Next, check the number of combinational logic levels. Run the command to report the current 1000 combinational logic levels, obtain the maximum number of levels and compare it with the set threshold. When the number of levels exceeds the threshold, it indicates that the design may be difficult to converge. At this time, it is necessary to confirm with the designer and modify the clock constraints. The method for handling the combinational logic levels within a reasonable range is retiming. The typical retiming method is pipelining, which adds registers to the overly lengthy combinational logic to beat it. Finally, run the report fan-out command to obtain a report on the fan-out signal, find out the signals and modules whose fan-out signals are greater than the set value. For signals and modules that exceed the set value, you can optimize them by selecting a design optimization strategy. At the same time, the fan-out also needs to be checked and analyzed in the layout stage and processed using physical optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 A schematic diagram of an embodiment of a method for improving FPGA prototype verification efficiency provided by the present invention;

[0035] Figure 2 A schematic diagram of another embodiment of the method for improving FPGA prototype verification efficiency provided by the present invention;

[0036] Figure 3 A schematic diagram of an embodiment of a device for improving FPGA prototype verification efficiency provided by the present invention;

[0037] Figure 4 A schematic diagram of an embodiment of a computer device provided by the present invention;

[0038] Figure 5A schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0040] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. Subsequent embodiments will not explain this one by one.

[0041] Based on the above objectives, a first aspect of the embodiments of the present invention provides an embodiment of a method for improving the efficiency of FPGA prototype verification. Figure 1 Shown is a schematic diagram of an embodiment of a method for improving FPGA prototype verification efficiency provided by the present invention. Figure 2 FIG. 1 is a schematic diagram of another embodiment of the method for improving FPGA prototype verification efficiency provided by the present invention. Figure 1 and Figure 2 As shown, the method for improving FPGA prototype verification efficiency according to an embodiment of the present invention includes the following steps:

[0042] 001. Run the design synthesis command to obtain the netlist file after the design synthesis is completed;

[0043] 002. Run the report_qor_assessment command to obtain the current report;

[0044] 003. Detect the report score and determine the relationship between the score and the preset threshold;

[0045] 004. If the score is less than the preset threshold, the design is tested and the above steps are repeated;

[0046] 005. If the score is greater than or equal to the preset threshold, continue to perform clock relationship judgment, timing result judgment, combinational logic chain level threshold judgment, and fan-out threshold judgment to generate a new synthesis strategy and implementation strategy.

[0047] In this embodiment, the basic design implementation process in the Vivado tool is used, wherein the FPGA verification implementation process includes design synthesis - design optimization - power optimization - physical layout - physical optimization - physical routing - generating a bitstream file.

[0048] Synthesis: Completes the conversion and mapping of HDL (Hardware Description Language) code into hardware circuits, generating the netlist files required for implementation. The gate-level netlist generated after synthesis is only a virtual connection relationship and does not reflect the physical device. Synthesis is a creative transformation process that not only translates our circuits but also optimizes them, such as removing redundant circuit structures in the circuit description or reusing circuit structures with the same function.

[0049] Power optimization: It is to minimize the power consumption of FPGA while minimizing its impact on timing.

[0050] Physical optimization: It is an important means of optimizing timing by copying and moving registers to reduce fan-out and readjust timing in the back end. It generally runs between physical layout and physical routing.

[0051] Physical layout: The process of placing the synthesized circuit components inside the FPGA according to the constraint file.

[0052] Physical routing: The process of routing wires between components after completing the physical layout.

[0053] Running report_qor_assessment can get a score between 1 and 5. The higher the score, the easier it is for the design timing to converge. If the score is 1 or 2, the design is unlikely to converge; if the score is 3, the design is unlikely to converge. Therefore, the preset threshold is set to 3. As shown in Table 1 below

[0054] Table 1--Overall Assessment Summary

[0055]

[0056] The second part of this command is crucial, as shown in Table 2 below. It reports resource utilization, notably the actual value and the guideline. If the guideline is exceeded, the Status column displays "REVIEW." Exceeding the guideline is not unacceptable, but it can significantly impact timing closure. Furthermore, the report also analyzes the number of logic levels, control sets, congestion, and fanout.

[0057] Table 2 Qor Assessment Details

[0058]

[0059] If the report score is less than 3, the process stops and the FPGA verifier checks the design. If the score is greater than or equal to 3, the process continues to analyze timing, combinational logic levels, fan-out, etc.

[0060] In some embodiments of the present invention, the clock relationship determination includes: running the report_clock_interaction command to obtain the clock relationship; determining whether there is an unexpected synchronous clock path; if so, adding an asynchronous timing constraint file to solve the problem; and if not, continuing to determine the timing result. Adding an asynchronous timing constraint file to solve the problem includes: if there is an unexpected synchronous clock path, using

[0061] set_false_path-from[get_clocks clk1]-to[get_clocks clk2]

[0062] set_false_path-from[get_clocks clk2]-to[get_clocks clk1]

[0063] Eliminate undesirable synchronous clock relationships.

[0064] Among them, resynthesis is required after eliminating the undesirable synchronous clock relationship.

[0065] In some embodiments of the present invention, determining timing results includes: executing the report_timing_summary command to obtain a timing report; determining whether the timing results have converged; if not, establishing a hold time violation process; and if converged, performing a combinational logic chain level threshold determination. Establishing a hold time violation process includes, if timing has not converged, selecting the worst timing path and optimizing it until convergence.

[0066] In this embodiment, if the clock relationships are normal, the Report Timing Summary command is used to obtain an overall timing report. This summary displays information such as Setup time and Hold time. If either WNS or WHS is less than 0, it indicates that timing has not converged. If timing has not converged, it is not necessary to analyze all unconverged paths. Instead, focus on the paths with the worst timing and optimize them first. It is possible that after optimizing these paths, they converge and other paths can also converge. Based on the timing results, the corresponding physical optimization strategy can be selected during the implementation phase.

[0067] In some embodiments of the present invention, determining the threshold value of the number of combinatorial logic chain levels includes: running the report_design_analysis command to obtain the number of combinatorial logic chain levels; determining the threshold range of the number of combinatorial logic chain levels; if it exceeds the threshold range, re-applying timing constraints; if it does not exceed the threshold range, modifying the timing constraints or changing the synthesis strategy to retiming 00c synthesis. Running report_design_analysis-logic_level_distribution-logic_level_dist_paths 1000 to obtain the current number of combinatorial logic levels for 1000 paths; at a frequency of 50MHZ, the delay of a combinatorial logic is 0.5ns, and the corresponding combinatorial logic level threshold is 40 levels; if the number of combinatorial logic levels is greater than 40, re-applying timing constraints; if the number of combinatorial logic levels is less than or equal to 40, changing the synthesis strategy to retiming 00c synthesis.

[0068] In this embodiment, report_design_analysis-logic_level_distribution-logic_level_dist_paths 1000 is run to obtain the current 1000 path combinatorial logic levels, as shown in Table 3. The combinatorial logic level generally affects the maximum clock frequency. Generally, the delay of a combinatorial logic level corresponds to the delay of a lookup table and a line. The delay varies for different devices and frequencies. Assuming the highest design frequency is 50 MHz and the delay of a combinatorial logic is 0.5 ns, the combinatorial logic level should be controlled at around 40 levels. When the tool detects that the combinatorial logic level is much greater than 40, the design may be difficult to converge. In this case, it is necessary to confirm with the designer and modify the clock constraints. When the combinatorial logic is within the set range of the design, the combinatorial logic level is handled by retiming. The typical retiming method is pipelining, which adds registers to the overly lengthy combinatorial logic for pacing.

[0069] Table 3 Logic Level Distribution

[0070]

[0071] In some embodiments of the present invention, fanout threshold determination includes: running the report_high_fanout_nets command to obtain fanout; determining the fanout threshold; if the fanout threshold is exceeded, selecting a corresponding optimization strategy in the implementation phase; if the fanout threshold is not exceeded, generating a new comprehensive strategy and implementation strategy. Selecting a corresponding optimization strategy in the implementation phase includes: taking the following two approaches in the implementation phase:

[0072] opt_design merge_equivalent_drivers hier_fanout_limit 512; or

[0073] phys_opt_design-force_replication_on_nets[get_nets net_name].

[0074] In this embodiment, running the report_high_fanout_nets command (report_high_fanout_nets-fanout_greater_than 50-max_nets 200) yields a report of 200 signals with fanout greater than 50, as shown in Table 4 below. For designs that exceed the fanout setting, the following two methods can be used in the implementation phase:

[0075] opt_design merge_equivalent_drivers hier_fanout_limit 512

[0076] phys_opt_design-force_replication_on_nets[get_nets net_name].

[0077] Table 4 Report of 200 signals with fan-out greater than 50

[0078]

[0079]

[0080] Based on the above objectives, a second aspect of an embodiment of the present invention provides a device for improving the efficiency of FPGA prototype verification. Figure 3 FIG. 1 is a schematic diagram of an embodiment of a device for improving FPGA prototype verification efficiency provided by the present invention. Figure 3As shown, the apparatus for improving FPGA prototype verification efficiency according to an embodiment of the present invention includes the following components: a design unit 011, for designing a synthesis strategy and an implementation strategy; an operation analysis unit 012, for obtaining a report and detecting the report through the report_qor_assessment command; a clock relationship judgment unit 013, for obtaining a clock relationship through the report_clock_interaction command and then detecting the clock relationship; a timing result judgment unit 014, for obtaining a timing report and detecting the timing result through the report_timing_summary command; a combinational logic chain level threshold judgment unit 016, for obtaining a combinational logic chain level and detecting the combinational logic chain level threshold through the report_design_analysis command; and a fan-out threshold judgment unit, for obtaining a fan-out signal report and detecting the fan-out threshold through the report_high_fanout_nets command.

[0081] In some embodiments of the present invention, the design unit 011 is further configured to: complete the synthesis of the design using a default synthesis strategy, open the synthesized design, and run a design synthesis command to obtain a netlist file after the design synthesis is completed.

[0082] In some embodiments of the present invention, the operation analysis unit 012 is further configured to: the operation analysis unit may obtain a score between 1 and 5 by running report_qor_assessment, and the convergence is judged according to the size of the score and 3.

[0083] In some embodiments of the present invention, the clock relationship judgment unit 013 is further configured as: a clock relationship judgment unit, running the report_clock_interaction command to obtain the clock relationship; judging whether there is an unexpected synchronous clock path; if so, adding an asynchronous timing constraint file to solve it; and if not, continuing to judge the timing result.

[0084] In some embodiments of the present invention, the timing result judgment unit 014 is further configured as follows: the timing result judgment unit runs the report_timing_summary command to obtain a timing report; determines whether the timing result converges; if not, establishes a hold time violation process; if converged, performs a combinational logic chain level threshold judgment.

[0085] In some embodiments of the present invention, the combinational logic chain level threshold judgment unit 015 is further configured as follows: the combinational logic chain level threshold judgment unit runs the report_design_analysis command to obtain the combinational logic chain level; judges the threshold range of the combinational logic chain level; if it exceeds the threshold range, re-performs the timing constraints; if it does not exceed the threshold range, modifies the timing constraints or modifies the synthesis strategy to retiming 00c synthesis.

[0086] In some embodiments of the present invention, the fan-out threshold determination unit 016 is further configured as follows: the fan-out threshold determination unit runs the report_high_fanout_nets command to obtain the fan-out; determines the fan-out threshold; if the fan-out threshold is exceeded, selects a corresponding optimization strategy in the implementation stage; if the fan-out threshold is not exceeded, generates a new comprehensive strategy and implementation strategy.

[0087] Based on the above objectives, a third aspect of an embodiment of the present invention provides a computer device. Figure 4 FIG. 1 is a schematic diagram of an embodiment of a computer device provided by the present invention. Figure 4 As shown, the computer device of the embodiment of the present invention includes the following devices: at least one processor 021; and a memory 022, the memory 022 stores computer instructions 023 that can be run on the processor, and the steps of implementing the method when the instructions are executed by the processor include: running a design synthesis command to obtain a netlist file after the design synthesis is completed; running the report_qor_assessment command to obtain the current report; detecting the report score and judging the relationship between the score and 3; if the score is less than 3, detecting the design and repeating the above steps; and if the score is greater than or equal to 3, continuing to perform clock relationship judgment, timing result judgment, combinational logic chain level threshold judgment, and fan-out threshold judgment to generate a new synthesis strategy and implementation strategy.

[0088] The present invention also provides a computer-readable storage medium. Figure 5 FIG. 1 is a schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention. Figure 5 As shown, the computer-readable storage medium 031 stores a computer program 032 that performs the above method when executed by a processor.

[0089] Finally, it should be noted that those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program. The program of the server centralized testing method can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium of the program can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding embodiments of any of the aforementioned methods.

[0090] In addition, the method disclosed in the embodiment of the present invention can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the above functions defined in the method disclosed in the embodiment of the present invention are performed.

[0091] In addition, the above method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.

[0092] It will also be appreciated by those skilled in the art that the various exemplary logic blocks, modules, circuits and algorithmic steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0093] In one or more exemplary designs, the function can be implemented in hardware, software, firmware or any combination thereof. If implemented in software, the function can be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Computer-readable media include computer storage media and communication media, and the communication media include any media that helps to transmit a computer program from one location to another. The storage medium can be any available medium that can be accessed by a general or special-purpose computer. As an example and not limitation, the computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the required program code in the form of an instruction or data structure and can be accessed by a general or special-purpose computer or a general or special-purpose processor. In addition, any connection can be appropriately referred to as a computer-readable medium. For example, if a coaxial cable, optical fiber cable, twisted pair, digital subscriber line (DOL) or wireless technologies such as infrared, radio and microwaves are used to send software from a website, server or other remote source, the above-mentioned coaxial cable, optical fiber cable, twisted pair, DOL or wireless technologies such as infrared, radio and microwaves are all included in the definition of medium. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0094] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless expressly limited to the singular.

[0095] It should be understood that, as used herein, the singular forms "a" and "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" is intended to include any and all possible combinations of one or more of the associated listed items.

[0096] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0097] Those skilled in the art will understand that all or part of the steps of implementing the above embodiments may be accomplished by hardware, or may be accomplished by instructing relevant hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk, or an optical disk, etc.

[0098] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples. Within the spirit of the embodiments of the present invention, the technical features of the above embodiments or different embodiments may be combined, and there are many other variations of different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of the embodiments of the present invention.

Claims

1. A method for improving FPGA prototype verification efficiency, characterized in that: include: Run the design synthesis command to obtain the netlist file after the design synthesis is completed, which includes: completing the conversion and mapping of HDL code to hardware circuit, and generating the netlist file required for implementation; Run the report_qor_assessment command to obtain the current report; Detect the reported score and determine its relationship to the preset threshold; If the score is less than the preset threshold, the design is tested and the above steps are repeated; and If the score is greater than or equal to the preset threshold, the clock relationship judgment, timing result judgment, combinational logic chain level threshold judgment, and fan-out threshold judgment are continued to generate a new synthesis strategy and implementation strategy; The clock relationship determination includes: determining whether there is an unexpected synchronous clock path; if so, adding an asynchronous timing constraint file to resolve the problem; and if not, continuing with the timing result determination. The timing result judgment includes: judging whether the timing result converges; if not, establishing a hold time violation process; if converged, performing a combinational logic chain level threshold judgment; The threshold determination of the combinational logic chain level includes: determining a threshold range of the combinational logic chain level; if the threshold range is exceeded, re-performing timing constraints; if the threshold range is not exceeded, modifying timing constraints or modifying the synthesis strategy to retiming 00 c synthesis; The fan-out threshold determination includes: determining the fan-out threshold; if the fan-out threshold is exceeded, selecting a corresponding optimization strategy in the implementation phase; if the fan-out threshold is not exceeded, generating a new synthesis strategy and implementation strategy; the selection of the corresponding optimization strategy in the implementation phase includes: processing opt_design merge_equivalent_drivers hier_fanout_limit 512 or phys_opt_design -force_replication_on_nets[get_nets net_name] in the implementation phase in the following two ways.

2. The method for improving FPGA prototype verification efficiency according to claim 1, wherein: Determining the clock relationship includes running the report_clock_interaction command to obtain the clock relationship.

3. The method for improving FPGA prototype verification efficiency according to claim 2, wherein: Add asynchronous timing constraint files to solve the problem: If there is an unexpected synchronous clock path, use set_false_path -from [get_clocks clk1] -to [get_clocks clk2] set_false_path -from [get_clocks clk2] -to [get_clocks clk1] Eliminate undesirable synchronous clock relationships.

4. The method for improving FPGA prototype verification efficiency according to claim 1, wherein: Timing result judgment includes: running the report_timing_summary command to obtain a timing report.

5. The method for improving FPGA prototype verification efficiency according to claim 4, wherein: Setup and hold time violation handling includes picking the worst timing path and optimizing it until it converges if timing does not close.

6. The method for improving FPGA prototype verification efficiency according to claim 1, wherein: The threshold value judgment of the combinational logic chain level includes: running the report_design_analysis command to obtain the combinational logic chain level.

7. The method for improving FPGA prototype verification efficiency according to claim 6, wherein: include: Run report_design_analysis -logic_level_distribution -logic_level_dist_paths 1000 to obtain the combinational logic levels of the current 1000 paths; At a frequency of 50 MHz, the delay of a combinational logic is 0.5 ns, and the corresponding combinational logic level threshold is 40 levels; If the number of combinational logic levels is greater than 40, re-perform timing constraints; If the number of combinational logic levels is less than or equal to 40, the synthesis strategy is modified to retiming 00 c synthesis.

8. The method for improving FPGA prototype verification efficiency according to claim 1, wherein: The fanout threshold determination includes: running the report_high_fanout_nets command to obtain the fanout.

9. A device for improving FPGA prototype verification efficiency, characterized in that: include: Design unit, used to design synthesis strategy and implementation strategy; Run the analysis unit to obtain and test reports through the report_qor_assessment command; A clock relationship determination unit, configured to obtain the clock relationship through a report_clock_interaction command and then detect the clock relationship; Timing result judgment unit, used to obtain timing report and detect timing results through report_timing_summary command; A combinational logic chain level threshold judgment unit is used to obtain the combinational logic chain level and detect the combinational logic chain level threshold through the report_design_analysis command; A fanout threshold judgment unit is used to obtain a fanout signal report and detect a fanout threshold through the report_high_fanout_nets command; The design unit is used to: complete the conversion and mapping of HDL code to hardware circuit, and generate the netlist file required for implementation; The clock relationship judgment unit is used to: judge whether there is an unexpected synchronous clock path; if so, add an asynchronous timing constraint file to solve it; and if not, continue to judge the timing result; The timing result judgment unit is used to: judge whether the timing result converges; if not, establish a hold time violation process; if converged, perform a combinational logic chain level threshold judgment; The combinational logic chain level threshold determination unit is used to: determine the threshold range of the combinational logic chain level; if it exceeds the threshold range, re-perform the timing constraint; if it does not exceed the threshold range, modify the timing constraint or modify the synthesis strategy to retiming 00 c synthesis; The fan-out threshold determination unit is configured to determine a fan-out threshold; if the fan-out threshold is exceeded, select a corresponding optimization strategy during an implementation phase; if the fan-out threshold is not exceeded, generate a new synthesis strategy and implementation strategy; selecting a corresponding optimization strategy during an implementation phase includes: processing opt_design merge_equivalent_drivers hier_fanout_limit 512 or phys_opt_design -force_replication_on_nets[get_nets net_name] in the implementation phase.

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