Field programmable gate array (FPGA) prototype partitioning method based on result driving
By adopting a result-driven FPGA prototyping partitioning method, the problems of placement and routing congestion and timing non-compliance were solved, realizing high-speed FPGA prototyping without human intervention, improving signal transmission speed and parallel clock rate, and ensuring the success of onboard testing.
Patent Information
- Application Number
- CN202511534880.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-24
- Publication Date
- 2026-02-03
AI Technical Summary
Traditional FPGA prototyping partitioning methods result in congested placement and routing, timing inconsistencies, and inability to directly test on the board. Furthermore, existing tools require manual intervention to adjust parameters, which cannot meet the requirements of high-speed FPGA prototyping.
A result-driven FPGA prototyping partitioning method is adopted. The module is marked by the initial partitioning algorithm, a graph model is established, the partitioning cost is calculated, and the placement and routing optimization is performed. Adaptive optimization and time-division multiplexing technology are used to eliminate the latency limitations of traditional partitioning and realize unattended board testing.
It improves the speed and ratio of cross-zone signal transmission, increases the parallel clock rate, reduces the layout and routing failure rate, and enables unattended onboard testing.
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Figure CN121457415A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of FPGA chip prototyping technology, and in particular to a result-driven FPGA prototyping partitioning method. BACKGROUND
[0002] A field programmable gate array (FPGA) is a programmable semiconductor device that can be configured by a user to realize a specific digital circuit function after manufacturing. FPGA chip prototyping technology allows software development to no longer rely on ASIC silicon during chip development, enabling software development to be advanced before tape-out, reducing software development costs, and making it possible to synchronize software and hardware releases.
[0003] In FPGA prototyping design, a single FPGA cannot carry the entire ASIC chip design, so the ASIC chip design needs to be partitioned into multiple FPGAs. Traditional solutions mainly use graph modeling partitioning methods based on area resources and interconnection costs when automatically partitioning into multiple FPGAs, such as the classic iterative greedy Kernighan-Lin algorithm, the Fiduccia-Mattheyses algorithm, and other iterative improvement algorithms that only fine-tune the partitioning results.
[0004] However, due to the natural differences in structure between LUT-based FPGAs and logic gate-based ASICs, the results of the above algorithms or tools often encounter routing congestion and FPGA timing non-compliance when further performing back-end layout and routing, resulting in partitioning results that cannot meet on-board testing. In addition, due to the design scale of artificial intelligence chips exceeding 10 billion gates, compared to the limited pin resources (IO) of FPGAs, pure partitioning circuit methods cannot achieve interconnection between FPGAs, and existing partitioning TDM solutions will introduce additional TDM delays, further increasing the timing cost of prototyping partitioning, which limits the parallel clock frequency of signals to be partitioned and cannot meet the growing requirements of high-speed FPGA prototyping, especially when frequent interactions with peripherals are required and faster hardware regression testing is needed. In addition, current commercial automatic partitioning tools or open-source methods generally require deep involvement of R&D personnel, who need to manually adjust parameters or partition constraints to generate the final FPGA data bitstream for on-board testing. SUMMARY
[0005] The FPGA prototyping partitioning method based on result-driven provided by the embodiments of the present application solves the problem that the partitioning results in the prior art easily lead to layout and routing congestion, timing non-compliance, and cannot be directly tested on board.
[0006] The embodiment of the present application provides a result-driven FPGA prototype partitioning method, comprising the following steps: Based on the initial partitioning algorithm, a first module and a second module are marked in a to-be-processed module; the first module is a module conforming to a VR handshake protocol; and the second module is a module not conforming to the VR handshake protocol; A first graph model is established based on the first module; and a second graph model is established based on the second module; The partitioning cost of the first graph model and the second graph model is calculated, and a partitioning result when the partitioning cost is the lowest is obtained; Based on the partitioning result, layout and wiring are performed, and adaptive optimization is performed on the partitioned FPGA until the timing requirement of the layout and wiring is met; FPGA data bitstream meeting the timing requirement of the layout and wiring is output.
[0007] In some feasible embodiments, the initial partitioning algorithm comprises the following steps: A first module in the form of a VR interface is traversed in all to-be-processed modules; and a first mark is added to the first module in the traversal process; A plurality of FPGA to-be-partitioned for accommodating the first module are defined, and the FPGA to-be-partitioned have a second mark; The FPGA to-be-partitioned are allocated with the first module based on the order of the second mark, and all the first modules are allocated to the FPGA to-be-partitioned.
[0008] In some feasible embodiments, the FPGA to-be-partitioned are allocated with the first module based on the order of the second mark, and the method comprises the following steps: If the area of the first module is smaller than the remaining area of the FPGA to-be-partitioned, the first module is allocated to the FPGA to-be-partitioned; If the area of the first module is greater than the remaining area of the FPGA to-be-partitioned, the remaining first modules are continuously traversed, and when the areas of all the first modules are greater than the remaining area of the FPGA to-be-partitioned, the first module is allocated to the FPGA to-be-partitioned in the next order.
[0009] In some feasible embodiments, the partitioning cost of the first graph model and the second graph model is calculated, and the partitioning result when the partitioning cost is the lowest is obtained, and the method comprises the following steps: The branch cell range of the first module is calculated based on partitioning constraints and target FPGA resource values; the branch cell range comprises an upper limit value and a lower limit value; When the area of a branch cell is smaller than the lower limit value, the cell value of the first module corresponding to the branch cell is pruned to 0; Based on the greedy strategy, the total cost of the partition after the exchange of the branch unit is calculated, and the total cost of the partition is the area of the branch unit and the number of interconnections between the branch unit and the first FPGA partition and the second FPGA partition. The partition result with the lowest total cost of the partition is obtained.
[0010] In some feasible embodiments, based on the partition result, layout and routing are performed, including: Based on the partition-specific time division multiplexing technology, the traditional time division multiplexing technology, and the direct connection technology, layout and routing are performed on the partition result and timing is checked.
[0011] In some feasible embodiments, based on the partition-specific time division multiplexing technology, the step of performing layout and routing on the partition result and checking timing includes: The number of interconnections and partition resources of each FPGA partition corresponding to the partition result are obtained. A data transmission chain based on credit-based protocol conversion is established; the data transmission chain records the data transmitted and received through a serial transceiver; The signal transmission ratio of each FPGA partition is determined; Based on the signal transmission ratio and the transmission rate of the serial transceiver, the maximum clock frequency of the data to be transmitted is determined.
[0012] In some feasible embodiments, adaptive optimization is performed on the partitioned FPGA, including: Cross-partition optimization and multi-hop optimization.
[0013] In some feasible embodiments, the cross-partition optimization includes: When the number of interconnections between the first FPGA partition and the second FPGA partition is less than the actual number of interconnections, a third FPGA partition is used to provide a bridging connection between the first FPGA partition and the second FPGA partition; the number of interconnections between the third FPGA partition and the first FPGA partition and the second FPGA partition is greater than 1.
[0014] In some feasible embodiments, the third FPGA partition is used to provide a bridging connection between the first FPGA partition and the second FPGA partition, including: Based on the interconnection network between the first FPGA partition and the second FPGA partition, the smallest register unit connected is searched; The smallest register unit is copied to the bridging unit of the third FPGA partition to realize the bridging connection of the first FPGA partition, the second FPGA partition, and the third FPGA partition.
[0015] In some feasible embodiments, the multi-hop optimization includes: The timing path of multiple hops across different FPGA partitions is calculated; When the timing of the hop point does not meet the preset requirements, the hop point is moved to the adjacent FPGA partition.
[0016] The application provides a result-driven FPGA prototype partitioning method. In order to improve the signal transmission speed and ratio between partitions as much as possible, a priority partitioning method based on protocol characteristics is first proposed, and a method of first sparsification and then partitioning is adopted to improve the efficiency of partitioning. In view of the problem that the existing partitioning algorithms generally do not support parallel clock rate, a time division multiplexing method PTDM designed for partitioning is proposed. Based on the results of the protocol characteristic module partitioning, a credit protocol conversion method is used to eliminate the limitation of transmitting data within a single parallel clock cycle in the traditional partitioning. The parallel clock rate can be improved by 8 times in the time division multiplexing partitioning signal interconnection transmission method. Finally, in view of the situation that the partitioning can be passed in real industrial design, but the layout and wiring often fail, an algorithm strategy for dynamically adjusting the partitioning is proposed to realize the purpose of the FPGA data bit stream that can be finally tested without human intervention. BRIEF DESCRIPTION OF DRAWINGS
[0017] Figure 1 A principle diagram of the result-driven FPGA prototype partitioning method provided by the embodiment of the application is provided. Figure 2 A signal transmission principle diagram of the credit-based protocol conversion in the method provided by the embodiment of the application is provided. Figure 3 A strategy diagram of the self-adaptive dynamic automatic adjustment in the method provided by the embodiment of the application is provided. DETAILED DESCRIPTION
[0018] In order to enable the persons skilled in the art to better understand the technical solutions in the application, the technical solutions in the embodiments of the application will be clearly and completely described in the embodiments of the application in combination with the drawings. Obviously, the described embodiments are only a part of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by the persons skilled in the art without creative labor should belong to the protection scope of the application.
[0019] First, the terms mentioned in the embodiments of the application are explained as follows: FPGA (Field-Programmable Gate Array): field programmable gate array, which is a programmable semiconductor device that can be configured by users to realize specific digital circuit functions after manufacturing.
[0020] ASIC (Application-Specific Integrated Circuit): A specialized integrated circuit designed for a specific purpose. Compared to FPGAs, ASICs have fixed functionality that cannot be changed after design completion.
[0021] P&R (Place and Route): A key step in integrated circuit design flow, including placing logic cells in appropriate locations on the chip (placement) and connecting these cells (routing).
[0022] LUT (Look-Up Table): A basic logic unit in FPGAs that can be configured to implement various logic functions.
[0023] VR protocol (Valid-Ready protocol): A handshake protocol where "Valid" indicates that the data is valid, and "Ready" indicates that the receiver is ready to receive data. Data transmission is completed only when both are true.
[0024] TDM (Time Domain Multiplexing): A time division multiplexing technique that improves line utilization by transmitting different signals in different time slices.
[0025] PTDM (Partition TDM): A time division multiplexing method designed for partitioning provided by the embodiments of the present application, which improves transmission rate through credit protocol conversion.
[0026] bitfile (FPGA data bitstream): A binary file containing FPGA configuration information, used to program the design into the FPGA.
[0027] Due to the huge speed advantage of FPGA prototypes compared to simulation and EMULATION systems, the speed of hardware design regression testing is accelerated. However, as the scale of integrated circuit design expands (artificial intelligence chips have exceeded one billion gate levels), the chip development cycle is extended, and the demand for "computing power chip rapid listing" by generative AI is in conflict; at the same time, traditional FPGA prototype partitioning technology has the following pain points: The partitioning results cannot adapt to the architectural differences between FPGAs and ASICs, leading to congestion in back-end placement and routing (P&R), timing not meeting, and unable to test on board; Traditional time division multiplexing (TDM) technology limits the cross-partition parallel clock rate (measured at only 2-25 MHz), which cannot meet the needs of high-speed hardware regression testing and peripheral interaction; Most existing tools such as hMETIS / PaToH (only million-level LUTs) or require repeated manual parameter adjustment, and the efficiency is still not high.
[0028] To solve the above problems, the application provides a result-driven FPGA prototype partitioning method, see Figure 1 The principle diagram of the result-driven FPGA prototype partitioning method provided by the embodiment of the application is shown in the following figure: In combination with Figure 1 In some embodiments, the result-driven FPGA prototype partitioning method provided by the application can include: The input data can include: a design to be partitioned (an ASIC code to be implemented as an FPGA prototype), a partition constraint file (for example, containing target partition area, resource upper and lower limit ratio, etc.); The module initial division step: in this step, the modules (such as AXI, APB interface IP) that meet the VR handshake protocol in the design to be partitioned can be searched and marked, the modules that meet the VR protocol are marked as VR modules (first modules), and the module-level initial allocation process is preferentially completed; for the remaining modules that do not meet the VR protocol, they can be marked as NVR modules (second modules), and the NVR modules can be modeled in a synchronous graph in a traditional manner.
[0029] The interface commonly used between integrated circuit IPs such as AXI, APB, etc. is based on the handshake process of data valid-data ready to receive, and data can only be accepted when both are valid. This data acknowledgment mechanism with feedback will cause sampling data errors in data transmission if a register is inserted in the data valid or data ready to receive signal path.
[0030] In the FPGA partitioning implementation, time division multiplexing is needed to improve the utilization rate of interconnection pins IO, and the traditional VR protocol-based method will cause greater delay in the critical path due to the introduction of TDM, while in the credit-based data transmission method in the embodiment of the application, data can be continuously sent when there is a credit value, which can avoid the above problems. Specifically, in the module initial division step, the module initial division algorithm based on VR protocol (MFSGrain Partition based on VR protocol-based modules) can be used to implement the initial allocation of the partition, and then before inserting TDM, the VR protocol is converted to a credit-based transmission method to further time division multiplex the partition.
[0031] In some embodiments, the module initial division algorithm based on VR protocol can include: Iterate through the first module with the VR interface among all the modules to be processed; during the iteration, add a first tag to the first module; for example, the module at the top level is tagged as L0, the module directly instantiated at the top level is tagged as L1, and so on, to obtain tags L2 to L... n The first module; during traversal, it can be done from L1 to L... n In the order of assignment, the corresponding first modules are assigned to the FPGA to be partitioned in turn, until all first modules have been assigned to the FPGA.
[0032] Define multiple FPGA partitions to accommodate the first module, each FPGA partition having a second label; for example, define the FPGA partitions as F1~F1. m When allocating the first module, you can use F1~F m The order is to assign the first module of the same level or hierarchy (marked L) to each FPGA to be partitioned.
[0033] After marking the first module and the FPGA to be partitioned, the first module can be assigned to the FPGA to be partitioned based on the order of the second marking, until all the first modules have been assigned to the FPGA to be partitioned.
[0034] Specifically, in some embodiments, the method for allocating the first module may include: If the area of the first module is smaller than the remaining area of the FPGA to be partitioned, then the first module is allocated to the FPGA to be partitioned; for example, if The area of the module is smaller than the area of the target partition. ,but Belongs to the current partition .
[0035] If the area of the first module is greater than the remaining area of the FPGA to be partitioned, then continue traversing the remaining first modules until the area of all first modules is greater than the remaining area of the FPGA to be partitioned, then allocate the first module to the next FPGA to be partitioned. For example, if L i The module's area is already larger than the target partition's area. Right now Then jump to the next module level L (i+1) Perform a search until a suitable first module is placed in the current partition. .
[0036] If the current partition F i If there is insufficient space to accommodate any one of the first modules, then we can begin preparing for the next FPGA partition F. jThe operation of allocating the first module is performed, and j is i+1 at this time.
[0037] In some embodiments, if the labels L1-L n have all been allocated, the operation can be terminated in advance. If the flag of area balance is set, the subsequent operation can be continued.
[0038] In some embodiments, after all the FPGA partitions F1-F m have obtained resource allocation, if the allocation of the first module is still not completed at this time (for example, i i , and there are still remaining modules in F m ), the loop of F1-F up can be continued to find the FPGA partitions that can accommodate the remaining first modules.
[0039] In some embodiments, when all the marked VR modules in all levels have been allocated, it can be considered that the module initial division step is completed.
[0040] Module pruning and graph modeling step: In this step, the modules with small area ratios need to be pruned to reduce the time consumption of the subsequent fine-tuning step. Among them, the VR-level graph model can be established based on the VR modules (first modules), and the traditional synchronous graph model can be established based on the non-VR modules (second modules).
[0041] Partition cost fine-tuning step: Through this step, the partition cost is calculated, and the strategy optimization adjustment is performed to minimize the total cost. Specifically, the partition costs of the first graph model and the second graph model can be calculated respectively to obtain the partition result when the partition cost is the lowest.
[0042] In some embodiments, the application embodiments adopt a partition cost fine-tuning algorithm (MFS Fine-Tuning According to Trimming and Cutting Costs) of first sparseness and then adjustment. The algorithm can include: After the graph model G(M, E) is established based on the VR-compliant modules and the graph model G(V, E) is established based on the non-VR-compliant modules, the branch element range of the set M composed of the first modules can be calculated based on the partition constraints and the target FPGA resource value. Among them, the branch element is the smallest unit of the partition cost calculation, and the branch element range includes the upper limit value B up and the lower limit value B bottom ; the upper limit value and the lower limit value satisfy the formula: ; ; Among them, is the total resource of the target partition single-chip FPGA. and respectively represent the ratio of the upper and lower limits of the pruning unit to the single-chip FPGA resource, and The initial value of the above-mentioned parameters can be defined by the user in the partition constraint file.
[0043] Then, the basic unit sparsification processing is performed, and when the area of the branch unit is less than the lower limit value, the unit value of the first module corresponding to the branch unit is pruned to 0; for example, the area of the branch unit is defined as When , the unit value of the first module is pruned to 0.
[0044] Based on the greedy strategy, the total partition cost after the exchange of the branch unit is calculated, and the total partition cost is the area sum of the branch unit. In this way, by traversing the current set M, all branch units can be pruned according to the range of B up and B bottom , and the cost is determined based on the unit value of the branch unit.
[0045] After the above steps are performed on all first modules, a corresponding total cost can be obtained, at this time, the first module with a basic unit value of 0 is moved, only the cut cost CC is changed, and the area cost AC is not increased, therefore, the greedy strategy is used to exchange the branch unit, and the resource calculation method of the current node V during the movement is as follows: N is the total number of modules; Therefore, the total partition cost is: ; Among them, represents the partition cost of each partition.
[0046] It should be noted that the above steps list the method of calculating the partition cost of the VR module, for non-VR modules, the partition resource can also be adjusted according to the above method until all resources are allocated and the total partition cost is minimized, which is not repeated here.
[0047] Finally, when the total partition cost is obtained, the subsequent steps can be performed using the partition result at this time.
[0048] Interconnection resource insertion step: in this step, three types of interconnection resources are introduced respectively based on the partition results obtained in the foregoing steps. In addition to the traditional time division multiplexing technology (CTDM), the interconnection resources also newly add a partition-specific time division multiplexing technology (PTDM) and a direct connection technology (DL, Direct Line). The PTDM includes a conversion process from a VR protocol to a credit-based protocol, and the purpose is to eliminate the additional delay caused by the traditional TDM. The DL interconnection type is a direct connection of partition signals for the case where the speed exceeds the PTDM and the TDM. The CTDM is a traditional TDM inserted for the case where the VR protocol is not met.
[0049] In some embodiments, after partitioning by using the minimization sparse objective function, the resources of each partition and the number of interconnections of each partition are obtained. The relationship between the number of FPGA interconnections and the partition cost is represented by a convergence factor β, and is represented by the following formula: ; Wherein, represents the number of interconnections of the FPGA of the current project. When β < 1, it represents that the partition is successful, and the TDM ratio used in the current partition can be represented by
[0050] In the embodiments of the present application, the algorithm principle of the partition-specific time division multiplexing technology is that the received signal is converted into a credit-based protocol in the PTDM. The specific principle is as follows: The PTDM transmitter maintains a credit counter.
[0051] If the sender still has credit points, it can continue to send data to the receiving side; The credit points decrease by one each time the sender sends data; If the sender receives a credit return from the receiving side, the credit points increase by one; The sender only sends data when the credit points are positive.
[0052] Referring to Figure 2 , a signal transmission principle diagram based on the credit-based protocol conversion in the method provided in the embodiments of the present application; The specific process of data transmission of the PTDM can be: Obtain the number of interconnection lines and partition resources of each FPGA partition corresponding to the partition result; The signal converted by the credit-based protocol can be transmitted by calling the I / O serial receiver / transmitter (I / OSDERDES) of the FPGA.
[0053] Before data transmission, LVDS level data link establishment is performed to ensure error-free data transmission, and therefore a data transmission link based on a credit protocol conversion is established; the data transmission link can record the data transmitted and received by the serial transceiver; specifically, the method for establishing the data transmission link can include: A1, a calibration sequence is sent from the sending side to the receiving side, and the principle of the calibration sequence is to distinguish the clock window.
[0054] A2, adjust the delay unit of the clock, and find the rising edge and falling edge of the training data.
[0055] A3, calculate the size of the clock adjustment window, and adjust the delay phase of the synchronization clock to the middle of the data window.
[0056] A4, after the correct sampling window of the clock data is trained, the training data is continuously sent, the serial received data is bit by bit moved at the receiving side, and the corresponding parallel data is converted, until the collected data is word aligned.
[0057] The boundary of the partition is set between the register-to-register path, and the signal transmission ratio of each FPGA partition is determined according to the following formula: ; Where N p is the number of signals transmitted after partitioning, and N a is the number of interconnection lines set for partitioning.
[0058] In some embodiments, for the multi-hop that cannot be eliminated, a direct connection mode is automatically used for processing.
[0059] In the embodiments of the present application, since the method of transmitting partitioned data based on a credit protocol is adopted, and both ends of the transmission have the function of register, the timing of PTDM across partitions is naturally satisfied. Only the transmission rate requirement of the serial transceiver (I / O serdes) needs to be met. The clock frequency requirement for the PTDM data to be put in is as follows: ; Where L serdes is the clock line rate of the serializer; and f max is the maximum clock frequency.
[0060] It can be seen that based on the signal transmission ratio and the transmission rate of the serial transceiver, the maximum clock frequency of the data to be transmitted can be determined. It has been measured that compared with the traditional partition tool which can only cope with 20~30 megahertz parallel clock data, the method provided by the embodiments of the present application can support hundreds of megahertz parallel clock data into the cross-partition by adjusting the transmission ratio used.
[0061] Wiring and timing optimization step: This step solves the problems such as timing violation by performing layout and wiring and checking timing through two different adjustments. Specifically, layout and wiring can be performed based on the partition result, and adaptive optimization is performed on the partitioned FPGA until the timing requirement of layout and wiring is met.
[0062] In some embodiments, when the interconnection resources between the partitioned FPGAs are insufficient, the adaptive optimization performed on the partitioned FPGAs can adopt two optimization methods, i.e., cross-partition optimization and multi-hop optimization.
[0063] In some embodiments, the specific method of cross-partition optimization includes: When the number of interconnection lines between the first FPGA partition and the second FPGA partition is less than the actual number of interconnections, a third FPGA partition is used to provide bridging connection between the first FPGA partition and the second FPGA partition; the number of interconnection lines between the third FPGA partition and the first FPGA partition and the second FPGA partition is greater than 1.
[0064] For example, the number of available interconnection lines between Fm and Fn is , the actual number of interconnections required after PTDM is , if , and there is another bridging FPGA, which is assumed to be Fj, if there is , and , then Fj can be used to bridge the excess signals between Fm and Fn.
[0065] In some embodiments, when the third FPGA partition is used to provide bridging connection between the first FPGA partition and the second FPGA partition, specifically, the connected smallest register unit can be searched based on the interconnection line network between the first FPGA partition and the second FPGA partition. The smallest register unit is copied to the bridging unit of the third FPGA partition to realize the bridging connection of the first FPGA partition, the second FPGA partition and the third FPGA partition.
[0066] For example, Fm is the partition where the source node is located, Fn is the partition where the target node is located, the smallest register unit connected with the source and target is searched through the interconnection line network W(Fm, Fn) between Fm and Fn, and is copied to the bridging Fj unit, so as to realize the bridging connection of Fm-Fj-Fn.
[0067] In some embodiments, the multi-hop optimization method is for the case where the combined logic path does not fit into a single partition, and the combined logic needs to be broken up into multiple hops across different partitions and placed into different FPGAs. The method allows the existence of relay FPGA hops to meet the timing requirements across FPGAs after partitioning. The method specifically includes: Calculating the timing path of the multiple hops across different FPGA partitions. When the timing of the hops does not meet the preset requirements, moving the hops to adjacent FPGA partitions to reduce the path of the combined logic of the hops.
[0068] Referring to Figure 3 The method provided in the embodiments of the present application has an adaptive dynamic automatic adjustment strategy.
[0069] Further, in the optimization process, an adaptive dynamic automatic adjustment strategy can also be used. Specifically, after fine-tuning the partitions, P&R (Plance and Route) operation is started for the partitioned FPGAs. Since the computing power of computers is becoming stronger and stronger, compared with the complex calculation of large-scale large models with hundreds of billions of parameters, the computing power requirement of P&R for computers is no longer a bottleneck. The method uses parallel computing power resource pool to exchange efficiency. All strategies of the corresponding FPGA layout and routing tool vendors are traversed. Taking the VIVADO 2025 tool as an example, the tool has a total of 31 routing strategies. The method uses a way of trying all routing strategies in parallel. If all layout and routing results fail, first start congestion checking, search for congestion and high fan-out nodes in the report, and insert global routing resources and remapping constraints, and then start the tool for layout and routing again. If it still fails, check the FPGA resources of the partition that fails in layout and routing. Decrease the constraint resources of the partition by a fixed ratio, and keep the total constraint resources of other partitions unchanged. The adjustment strategy of the partition is as follows: in FPGA back-end layout and routing, fewer resources usually make routing easier. If the partition Fi still fails in P&R after performing some back-end strategy optimizations such as multi-strategy layout and routing, inserting global resources, and congestion unit remapping, then decrease the resources of the partition by a fixed ratio, and keep the total constraint resources of other partitions unchanged. Reduce by 5%, and re-execute the partition fine-tuning algorithm until the final FPGA data bitstream that meets the board requirements is generated.
[0070] After all the foregoing optimizations are completed, the FPGA data bitstream that meets the layout and routing timing requirements can be output.
[0071] By the method provided in the embodiments of the present application, the parallel clock rate delivered by TDM can be increased from the traditional 2-20Mhz to 200Mhz or above, and the overall performance can be improved by nearly 10 times. In addition, after the method of automatic re-adjustment of partitioned resources is adopted, the layout and routing timing failure rate of a design with a scale of more than 300000 LUTs and a cross-partition FPGA can be reduced from (12 / 200000~100 / 200000) to (0 / 200000~10 / 200000), which is equivalent to an improvement of one order of magnitude. This is a FPGA prototype high-speed partition method directly facing the result, and the FPGA data bit stream file generated after partitioning can be directly used for board-level circuit debugging.
[0072] From the above technical solutions, it can be seen that the FPGA prototype partition method based on result driving provided in the embodiments of the present application improves the partition efficiency by adopting the method of first sparsification and then partitioning based on the protocol feature division module, and eliminates the limitation of transmitting data within a single parallel clock cycle in the traditional partitioning by using the time division multiplexing method PTDM designed for partitioning and converting the credit protocol. In addition, based on the algorithm strategy of dynamic adjustment of partitioning, no human intervention can be truly realized, and the purpose of obtaining FPGA data bit stream that can be tested on board can be achieved.
[0073] It is easy to understand that, based on the several embodiments provided in the present application, a person skilled in the art can combine, split, recombine, etc. the embodiments of the present application to obtain other embodiments, and these embodiments do not exceed the protection scope of the present application.
[0074] The above specific embodiments have further detailed the purposes, technical solutions and beneficial effects of the embodiments of the present application. It should be understood that the above is only a specific embodiment of the present application, and is not used to limit the protection scope of the embodiments of the present application. Any modification, equivalent replacement, improvement, etc. made on the basis of the technical solutions of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.
Claims
1. A result-driven based FPGA prototype partitioning method, characterized in that, The method comprises the following steps: Based on the initial partition algorithm, mark the first module and the second module in the to-be-processed module; The first module is a module conforming to the VR handshake protocol; The second module is a module not conforming to the VR handshake protocol; Based on the first module, a first graph model is established; and based on the second module, a second graph model is established; The partition cost of the first graph model and the second graph model is calculated, and the partition result when the partition cost is the lowest is obtained; Based on the partition result, layout and routing are performed, adaptive optimization is performed on the partitioned FPGA, and the timing requirement of layout and routing is met; The FPGA data bit stream meeting the timing requirement of layout and routing is output.
2. The result-driven FPGA prototyping partitioning method of claim 1, wherein, The initial partition algorithm comprises the following steps: All first modules in the form of VR interface are traversed in all to-be-processed modules; and in the traversal process, the first modules are added with a first mark; A plurality of FPGA to-be-partitioned for accommodating the first modules are defined, and the FPGA to-be-partitioned have a second mark; Based on the order of the second mark, the FPGA to-be-partitioned are allocated with the first modules, and all the first modules are allocated to the FPGA to-be-partitioned.
3. The result-driven FPGA prototyping partitioning method of claim 2, wherein, Based on the order of the second mark, the FPGA to-be-partitioned are allocated with the first modules, comprising: If the area of the first module is smaller than the remaining area of the FPGA to-be-partitioned, the first module is allocated to the FPGA to-be-partitioned; If the area of the first module is larger than the remaining area of the FPGA to-be-partitioned, the remaining first modules are continuously traversed, and when the area of all the first modules is larger than the remaining area of the FPGA to-be-partitioned, the first module is allocated to the FPGA to-be-partitioned in the next order.
4. The result-driven FPGA prototyping partitioning method of claim 1, wherein, The partition cost of the first graph model and the second graph model is calculated, and the partition result when the partition cost is the lowest is obtained, comprising: Based on the partition constraint and the target FPGA resource value, the branch unit range of the first module is calculated; the branch unit range comprises an upper limit value and a lower limit value; When the area of the branch unit is smaller than the lower limit value, the unit value of the first module corresponding to the branch unit is pruned to 0; Based on the greedy strategy, the total partition cost after exchange in the branch unit is calculated, and the total partition cost is the area sum of the branch unit. The partition result is obtained when the total partition cost is the lowest.
5. The result-driven FPGA prototyping partitioning method of claim 4, wherein, Based on the partition result, layout and routing are performed, comprising: Based on the partition-specific time division multiplexing technology, the traditional time division multiplexing technology and the direct connection technology, layout and routing are performed on the partition result and timing is checked.
6. The result-driven FPGA prototyping partitioning method of claim 5, wherein, Based on the partition-specific time division multiplexing technology, the steps of performing layout and routing on the partition result and checking timing comprise: The number of interconnection lines and partition resources of each FPGA partition corresponding to the partition result are obtained; A data transmission chain based on credit-based protocol conversion is established; the data transmission chain records the data to be sent and received through a serial transceiver; The signal transmission ratio of each FPGA partition is determined; Based on the signal transmission ratio and the transmission rate of the serial transceiver, the maximum clock frequency of the data to be sent is determined.
7. The result-driven FPGA prototyping partitioning method of claim 1, wherein, The adaptive optimization of the partitioned FPGA comprises: Cross-partition optimization and multi-hop point optimization.
8. The result-driven FPGA prototyping partitioning method of claim 7, wherein, The cross-partition optimization comprises: When the number of interconnections between the first FPGA partition and the second FPGA partition is less than the real number of interconnections, a third FPGA partition is used to provide bridging connection between the first FPGA partition and the second FPGA partition; the number of interconnections between the third FPGA partition and the first FPGA partition and the second FPGA partition is greater than 1.
9. The result-driven FPGA prototyping partitioning method of claim 8, wherein, The third FPGA partition is used to provide bridging connection between the first FPGA partition and the second FPGA partition, comprising: Based on the interconnection network between the first FPGA partition and the second FPGA partition, searching for the smallest register unit connected; The smallest register unit is copied to the bridging unit of the third FPGA partition to realize bridging connection of the first FPGA partition, the second FPGA partition and the third FPGA partition.
10. The result-driven FPGA prototyping partitioning method of claim 7, wherein, The multi-hop optimization comprises: Calculating the timing path of the multiple hops across different FPGA partitions; When the timing of the hop does not meet the preset requirement, moving the hop to the adjacent FPGA partition.