Preparation method of split-gate flash memory cell

Abstract

The present invention provides a method for preparing a split-gate flash memory cell, comprising: providing a substrate, sequentially forming a floating gate material layer and a dielectric layer on the substrate; etching the dielectric layer and the floating gate material layer to form an opening exposing the substrate; filling an erase gate in the opening; forming a patterned photoresist layer on the erase gate and the dielectric layer, and sequentially etching the dielectric layer and the floating gate material layer using the patterned photoresist layer as a mask to expose the substrate; removing the patterned photoresist layer, and forming a word line gate on a side of the dielectric layer and the floating gate away from the erase gate; and forming a word line gate electrical connector and an erase gate electrical connector, wherein the word line gate electrical connector and the erase gate electrical connector pass through the passivation layer and are electrically connected to the word line gate and the erase gate, respectively. The present invention simplifies the device preparation process.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a split-gate flash memory unit. Background Art

[0002] Flash memory, a type of non-volatile memory, stores data by controlling the switching of gate channels by varying the threshold voltage of transistors or memory cells, ensuring that the data is not lost due to power outages. Flash memory, a specialized structure of electrically erasable and programmable read-only memory, currently accounts for the majority of the non-volatile semiconductor memory market, becoming the fastest-growing type. Conventional flash memory is typically formed using a self-aligned process, which involves multiple furnace steps and is complex. Summary of the Invention

[0003] The object of the present invention is to provide a method for preparing a split-gate flash memory cell to simplify the device preparation process.

[0004] In order to achieve the above object, the present invention provides a method for preparing a split-gate flash memory cell, comprising:

[0005] Providing a substrate, and sequentially forming a floating gate material layer and a dielectric layer on the substrate;

[0006] Etching the dielectric layer and the floating gate material layer to form an opening exposing the substrate;

[0007] filling an erase gate in the opening;

[0008] forming a patterned photoresist layer on the erase gate and the dielectric layer, and sequentially etching the dielectric layer and the floating gate material layer using the patterned photoresist layer as a mask to expose the substrate, with the remaining floating gate material layer serving as a floating gate;

[0009] removing the patterned photoresist layer, and forming a word line gate on the dielectric layer and the side of the floating gate away from the erase gate; and

[0010] A passivation layer is formed on the substrate, and a word line gate electrical connector and an erase gate electrical connector are formed on the passivation layer. The passivation layer covers the substrate, the word line gate, the dielectric layer and the erase gate. The word line gate electrical connector and the erase gate electrical connector pass through the passivation layer and are electrically connected to the word line gate and the erase gate, respectively.

[0011] Optionally, the step of forming the opening includes:

[0012] etching the dielectric layer to form a first opening exposing the floating gate material layer; and

[0013] A first oxide layer is formed on the sidewall of the first opening, and the floating gate material layer is etched using the first oxide layer as a mask to form a second opening exposing the substrate. The first opening and the second opening are connected to form the opening.

[0014] Optionally, after the opening is formed, the first oxide layer is removed by etching, and a second oxide layer is formed on the inner wall of the opening.

[0015] Optionally, after forming the opening, the method further includes performing ion implantation on the substrate at the bottom of the opening to form a source region in the substrate.

[0016] Optionally, the material of the dielectric layer includes silicon oxide.

[0017] Optionally, after filling the erase gate in the opening and before forming the patterned photoresist layer, the method further includes:

[0018] A third oxide layer is formed on the erase gate and the dielectric layer.

[0019] Optionally, before forming a word line gate on the side of the dielectric layer and the floating gate away from the erase gate, a fourth oxide layer is formed on the side of the dielectric layer and the floating gate away from the erase gate, and the word line gate covers at least a portion of the surface of the fourth oxide layer.

[0020] Optionally, after forming a word line gate on the dielectric layer and on a side of the floating gate away from the erase gate, the method further includes:

[0021] Ion implantation is performed on the substrate outside the word line gate to form a drain region in the substrate.

[0022] Optionally, the step of forming the word line gate electrical connection and the erase gate electrical connection includes:

[0023] Etching the passivation layer to form a word line gate contact hole and an erase gate contact hole in the passivation layer, respectively exposing the word line gate and the erase gate; and

[0024] Metal material is filled in the word line gate contact hole and the erase gate contact hole to form a word line gate plug and an erase gate plug, respectively. A word line gate metal pattern and an erase gate metal pattern are formed on the passivation layer. The word line gate metal pattern is electrically connected to the word line gate plug to form the word line gate electrical connection. The erase gate metal pattern is electrically connected to the erase gate plug to form the erase gate electrical connection.

[0025] Optionally, the word line gate electrical connection and the erase gate electrical connection extend linearly in the same direction.

[0026] In the preparation method of the split-gate flash memory cell provided by the present invention, a floating gate material layer and a dielectric layer are sequentially formed on a provided substrate, the dielectric layer and the floating gate material layer are etched to form an opening exposing the substrate, and an erase gate is filled in the opening; a patterned photoresist layer is formed on the erase gate and the dielectric layer, and the dielectric layer and the floating gate material layer are sequentially etched using the patterned photoresist layer as a mask to expose the substrate, with the remaining floating gate material layer serving as the floating gate; the patterned photoresist layer is then removed, and a word line gate is formed on a side of the dielectric layer and the floating gate away from the erase gate; and a passivation layer is formed on the substrate, and word line gate electrical connectors and erase gate electrical connectors are formed on the passivation layer, wherein the passivation layer covers the substrate, word line gate, dielectric layer and erase gate, and the word line gate electrical connectors and erase gate electrical connectors pass through the passivation layer and are electrically connected to the word line gate and erase gate, respectively. The present invention defines the spacing between two adjacent word line grids by a patterned photoresist layer rather than by self-alignment, thereby simplifying the preparation process; and making the spacing between two adjacent word line grids unrestricted, the word line grid electrical connectors and the erase gate electrical connectors can be arranged in a straight line without the need for staggered arrangement, thereby reducing the process difficulty of forming the electrical connectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A top view of a split-gate flash memory device;

[0028] Figure 2 A flow chart of a method for preparing a split-gate flash memory cell provided in one embodiment of the present invention;

[0029] Figures 3A to 3L A schematic cross-sectional view of corresponding steps in a method for preparing a split-gate flash memory cell provided by an embodiment of the present invention;

[0030] Figure 4 A top view of a split-gate flash memory device manufactured by a method for manufacturing a split-gate flash memory cell provided by an embodiment of the present invention.

[0031] Wherein, the accompanying drawings are marked as follows:

[0032] 10-substrate; 11, 11'-storage area; 12, 12'-connection area; 21-gate oxide layer; 22-first oxide layer; 23-second oxide layer; 24-third oxide layer; 25-fourth oxide layer; 31-floating gate material layer; 32-erase gate material layer; 41-dielectric layer; 42-mask layer; 51-first opening; 52-second opening; 61-source region; 62-drain region; 70-patterned photoresist layer; 80, 80'-word line gate; 320, 320'-erase gate; 310, 310'-floating gate; 90-passivation layer; 91, 91'-word line gate electrical connector; 92, 92'-erase gate electrical connector; 100, 100'-bit line. DETAILED DESCRIPTION

[0033] The steps of the preparation method of the split-gate flash memory cell include: forming a floating gate material layer and a mask layer on a provided substrate in sequence, wherein the material of the mask layer is generally selected from silicon nitride with high stress; then etching the mask layer to form a first opening, wherein the first opening exposes the surface of the floating gate material layer, and then forming a first sidewall spacer on the sidewall of the first opening; then etching the floating gate material layer using the first sidewall spacer as a mask to form a second opening exposing the substrate, and forming a second sidewall spacer on the sidewall of the second opening, wherein the first sidewall spacer and the second sidewall spacer are both selected from an oxide with low stress, such as silicon oxide; filling the first opening and the second opening with an erase gate, and then etching away the mask layer and the floating gate material layer directly below the mask layer, wherein the remaining floating gate material layer serves as the floating gate, and the first sidewall spacer is located on the floating gate; then, forming a third sidewall spacer and a wordline gate on the side of the floating gate and the first sidewall away from the erase gate in sequence, respectively. A split-gate flash memory device can be formed by using multiple split-gate flash memory cells. It can be seen that the above preparation method forms the floating gate and wordline gate based on a self-aligned process, and the self-aligned process requires multiple furnace tube processes and is relatively complex.

[0034] Figure 1 This is a top view of a split-gate flash memory device. Please refer to Figure 1 , Figure 1 The split-gate flash memory device is formed using a self-aligned process, wherein the split-gate flash memory device is composed of a plurality of split-gate flash memory cells, wherein the split-gate flash memory device includes a storage area 11' and a connection area 12', and the split-gate flash memory device includes a plurality of erase gates 320', floating gates 310', and word line gates 80' extending along a first direction and arranged along a second direction, wherein the erase gates 320', floating gates 310', and word line gates 80' all pass through the storage area 11' and the connection area 12'; the split-gate flash memory device also includes a plurality of bit lines 100' extending along the second direction and arranged along the first direction.

[0035] Since, when forming the floating gate 310' (i.e., when defining the position of the word line gate 80'), the mask layer and the floating gate material layer directly below the mask layer are removed by etching, the spacing between two adjacent word line gates 80' in the split-gate flash memory cell is approximately equal to the total width of the two adjacent floating gates 310' (since the third sidewall is made of oxide and its thickness is generally small, the thickness of the third sidewall can be ignored), when forming the first sidewall, the first opening is first filled with a first sidewall material layer, and then the first sidewall material layer is etched to expose the floating gate material layer. The remaining first sidewall material layer serves as the first sidewall. In the preparation process, the formation of the first sidewall and the erase gate 310' is considered to limit the spacing between two adjacent word line gates 80'. Furthermore, when the erase gate electrical connection 92' and the word line gate electrical connection 91' are formed, they need to be electrically connected to the erase gate 320' and the word line gate 80' respectively. If the distance between two adjacent word line gates 80' is small, the erase gate electrical connection 92' and the word line gate electrical connection 91' may be disconnected. Figure 1 The staggered arrangement is electrically connected to the erase gate 320 ′ and the word line gate 80 ′, respectively, which increases the difficulty of forming the erase gate electrical connection 92 ′ and the word line gate electrical connection 91 ′. The staggered arrangement also increases the area of ​​the connection region 12 ′.

[0036] Therefore, the present invention provides a method for preparing a split-gate flash memory cell, comprising: forming a floating gate material layer and a dielectric layer in sequence on a provided substrate, etching the dielectric layer and the floating gate material layer to form an opening exposing the substrate, and filling the opening with an erase gate; forming a patterned photoresist layer on the erase gate and the dielectric layer, and etching the dielectric layer and the floating gate material layer in sequence using the patterned photoresist layer as a mask to expose the substrate, with the remaining floating gate material layer serving as the floating gate; then removing the patterned photoresist layer, and forming a word line gate on a side of the dielectric layer and the floating gate away from the erase gate; and forming a passivation layer on the substrate and forming a word line gate electrical connector and an erase gate electrical connector on the passivation layer, wherein the passivation layer covers the substrate, the word line gate, the dielectric layer and the erase gate, and the word line gate electrical connector and the erase gate electrical connector pass through the passivation layer and are electrically connected to the word line gate and the erase gate, respectively. The present invention defines the spacing between two adjacent word line grids by a patterned photoresist layer rather than by self-alignment, thereby simplifying the preparation process; and making the spacing between two adjacent word line grids unrestricted, the word line grid electrical connectors and the erase gate electrical connectors can be arranged in a straight line without the need for staggered arrangement, thereby reducing the process difficulty of forming the electrical connectors.

[0037] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0038] Figure 2 This is a flow chart of the method for preparing a split-gate flash memory cell provided in this embodiment. Figure 2 This embodiment provides a method for preparing a split-gate flash memory cell, comprising:

[0039] Step S1: providing a substrate, and sequentially forming a floating gate material layer and a dielectric layer on the substrate;

[0040] Step S2: etching the dielectric layer and the floating gate material layer to form an opening exposing the substrate;

[0041] Step S3: filling the erase gate in the opening;

[0042] Step S4: forming a patterned photoresist layer on the erase gate and the dielectric layer, and sequentially etching the dielectric layer and the floating gate material layer using the patterned photoresist layer as a mask to expose the substrate, with the remaining floating gate material layer serving as the floating gate;

[0043] Step S5: removing the patterned photoresist layer, and forming a word line gate on the dielectric layer and the side of the floating gate away from the erase gate; and

[0044] Step S6: forming a passivation layer on the substrate and forming word line gate electrical connectors and erase gate electrical connectors on the passivation layer, the passivation layer covers the substrate, word line gate, dielectric layer and erase gate, the word line gate electrical connectors and erase gate electrical connectors pass through the passivation layer and are electrically connected to the word line gate and erase gate respectively.

[0045] Figures 3A to 3L The cross-sectional diagram of the corresponding steps in the method for preparing the split gate flash memory cell provided in this embodiment, combined with Figures 3A to 3L The method for preparing the split-gate flash memory cell provided in this embodiment is described in detail.

[0046] Please refer to Figure 3A Step S1 is performed: providing a substrate 10, wherein the material of substrate 10 includes one or more of silicon, germanium, gallium, nitrogen, or carbon. A gate oxide layer 21, a floating gate material layer 31, a dielectric layer 41, and a mask layer 42 are sequentially formed on substrate 10. In this embodiment, dielectric layer 41 is preferably silicon oxide, which has low stress.

[0047] Executing step S2: the step of forming an opening includes:

[0048] Please refer to Figure 3B The mask layer 42 and the dielectric layer 41 are sequentially etched by a dry etching process to form a first opening 51 exposing the floating gate material layer 31 .

[0049] Please refer to Figure 3C A first oxide layer 22 is formed on the inner wall (side wall and bottom) of the first opening 51 , and the first oxide layer 22 extends to cover the surface of the mask layer 42 .

[0050] Please refer to Figure 3D First, the first oxide layer 22 at the bottom of the first opening 51 and on the surface of the mask layer 42 is etched away, leaving the first oxide layer 22 on the sidewalls of the first opening 51. Next, the floating gate material layer 31 is etched downward along the first opening 51 using the first oxide layer 22 as a mask to form a second opening 52 that exposes the substrate 10. The first opening 51 and the second opening 52 are connected to form an opening. In this embodiment, since the gate oxide layer 21 is formed, when the floating gate material layer 31 is etched downward along the first opening 51 using the first oxide layer 22 as a mask, the etching preferably stops on the gate oxide layer 21, that is, the bottom of the second opening 52 is the gate oxide layer 21. Further, ion implantation is performed on the substrate 10 at the bottom of the opening to form a source region 61 in the substrate 10.

[0051] Please refer to Figure 3E The first oxide layer 22 on the sidewall of the first opening 51 is etched away, and the gate oxide layer 21 at the bottom of the second opening 52 is simultaneously etched away so that the second opening 52 extends to expose the surface of the substrate 10 .

[0052] Please refer to Figure 3F A second oxide layer 23 is formed on the sidewalls of the first opening 51 and the inner walls of the second opening 52 , and the second oxide layer 23 extends to cover the surface of the mask layer 42 .

[0053] Please refer to Figure 3G and Figure 3H , step S3 is performed: the erase gate material layer 32 is filled in the first opening 51 and the second opening 52, and the erase gate material layer 32 covers the surface of the second oxide layer 23. Furthermore, a grinding process is used to remove the mask layer 42, the second oxide layer 23, and the erase gate material layer 32 on the surface of the dielectric layer 41. The remaining erase gate material layer 32 serves as the erase gate 320, so that the top of the erase gate 320 is flush with the top of the dielectric layer 41. Next, a third oxide layer 24 is formed on the erase gate 320 and the dielectric layer 41. The third oxide layer 24 is used to protect the erase gate 320 from being affected by subsequent processes.

[0054] Please refer to Figure 3I and Figure 3J , perform step S4: form a patterned photoresist layer 70 on the third oxide layer 24, and use the patterned photoresist layer 70 as a mask to sequentially etch the third oxide layer 24, the dielectric layer 41, the floating gate material layer 31 and the gate oxide layer 21 to expose the surface of the substrate 10, and the remaining floating gate material layer serves as the floating gate 310.

[0055] Please refer to Figure 3K, step S5 is performed: removing the patterned photoresist layer, forming a fourth oxide layer 25 on the corresponding dielectric layer 41 and the side of the floating gate 310 away from the erase gate 320, and the fourth oxide layer 25 extends to cover the surface of the substrate 10. Next, a word line gate 80 is formed on the substrate 10, and the word line gate 80 covers at least a portion of the surface of the fourth oxide layer 25. In this embodiment, the spacing between two adjacent word line gates 80 is defined by the patterned photoresist layer 70, rather than by self-alignment. This can save furnace process, simplify the preparation process, and make the spacing between two adjacent word line gates 80 unlimited.

[0056] Furthermore, after the word line gate 80 is formed, ion implantation is performed on the substrate 10 outside the word line gate 80 to form two drain regions 62 in the substrate 10 .

[0057] Please refer to Figure 3L , step S6 is performed: forming a passivation layer 90 on the substrate 10, the passivation layer 90 covering the substrate 10, the word line gate 80, the dielectric layer 41, and the erase gate 320. Next, forming a word line gate electrical connector 91 and an erase gate electrical connector 92 on the passivation layer 90, the word line gate electrical connector 91 and the erase gate electrical connector 92 passing through the passivation layer 90 to be electrically connected to the word line gate 80 and the erase gate 320, respectively. Specifically, the passivation layer 90 is etched to form a word line gate contact hole and an erase gate contact hole in the passivation layer 90, and the bottom of the word line gate contact hole and the bottom of the erase gate contact hole respectively expose the word line gate 80 and the erase gate 320; metal material is filled in the word line gate contact hole and the erase gate contact hole to form a word line gate plug and an erase gate plug; a word line gate metal pattern and an erase gate metal pattern are formed on the passivation layer 90, the word line gate metal pattern is electrically connected to the word line gate plug to form a word line gate electrical connector 91, and the erase gate metal pattern is electrically connected to the erase gate plug to form an erase gate electrical connector 92, and the word line gate electrical connector 91 and the erase gate electrical connector 92 can extend in a straight line along the same direction.

[0058] Figure 4 This is a top view of a split gate flash memory device manufactured by the method for manufacturing a split gate flash memory cell provided in this embodiment. Figure 4In this embodiment, a plurality of split-gate flash memory cells can be used to form a split-gate flash memory device, wherein the split-gate flash memory device includes a storage area 11 and a connection area 12, and the split-gate flash memory device includes a plurality of erase gates 320, floating gates 310, and word line gates 80 extending along a first direction and arranged along a second direction, wherein the erase gates 320, floating gates 310, and word line gates 80 all pass through the storage area 11 and the connection area 12; the split-gate flash memory device also includes a plurality of bit lines 100 extending along the second direction and arranged along the first direction. In this embodiment, since the spacing between two adjacent word line gates 80 is not limited, the word line gate electrical connectors 91 and the erase gate electrical connectors 92 can be arranged in a straight line along the second direction, and there is no need for the following steps: Figure 1 The staggered arrangement can, on the one hand, reduce the difficulty of forming the electrical connector, and on the other hand, reduce the area of ​​the connection region 12 .

[0059] In summary, in the preparation method of the split-gate flash memory unit provided by the present invention, a floating gate material layer and a dielectric layer are sequentially formed on the provided substrate, the dielectric layer and the floating gate material layer are etched to form an opening exposing the substrate, and an erase gate is filled in the opening; a patterned photoresist layer is formed on the erase gate and the dielectric layer, and the dielectric layer and the floating gate material layer are sequentially etched using the patterned photoresist layer as a mask to expose the substrate, and the remaining floating gate material layer serves as the floating gate; thereafter, the patterned photoresist layer is removed, and a word line gate is formed on the side of the dielectric layer and the floating gate away from the erase gate; and, a passivation layer is formed on the substrate, and word line gate electrical connectors and erase gate electrical connectors are formed on the passivation layer, the passivation layer covers the substrate, word line gate, dielectric layer and erase gate, and the word line gate electrical connectors and erase gate electrical connectors pass through the passivation layer and are electrically connected to the word line gate and erase gate, respectively. The present invention defines the spacing between two adjacent word line grids by a patterned photoresist layer rather than by self-alignment, thereby simplifying the preparation process; and making the spacing between two adjacent word line grids unrestricted, the word line grid electrical connectors and the erase gate electrical connectors can be arranged in a straight line without the need for staggered arrangement, thereby reducing the process difficulty of forming the electrical connectors.

[0060] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A method for preparing a split-gate flash memory cell, characterized in that: include: Providing a substrate, and sequentially forming a floating gate material layer and a dielectric layer on the substrate; Etching the dielectric layer and the floating gate material layer to form an opening exposing the substrate; filling an erase gate in the opening; forming a patterned photoresist layer on the erase gate and the dielectric layer, and sequentially etching the dielectric layer and the floating gate material layer using the patterned photoresist layer as a mask to expose the substrate, with the remaining floating gate material layer serving as a floating gate; removing the patterned photoresist layer, and forming a word line gate on the dielectric layer and the side of the floating gate away from the erase gate; as well as, forming a passivation layer on the substrate and forming a word line grid electrical connector and an erase gate electrical connector on the passivation layer, wherein the passivation layer covers the substrate, the word line grid, the dielectric layer and the erase gate, the word line grid electrical connector and the erase gate electrical connector pass through the passivation layer and are electrically connected to the word line grid and the erase gate, respectively, and the word line grid electrical connector and the erase gate electrical connector extend linearly in the same direction; The step of forming the opening includes: etching the dielectric layer to form a first opening exposing the floating gate material layer; and A first oxide layer is formed on the sidewall of the first opening, and the floating gate material layer is etched using the first oxide layer as a mask to form a second opening exposing the substrate. The first opening and the second opening are connected to form the opening.

2. The method for preparing a split-gate flash memory cell according to claim 1, wherein: After the opening is formed, the first oxide layer is removed by etching, and a second oxide layer is formed on the inner wall of the opening.

3. The method for preparing a split-gate flash memory cell according to claim 1, wherein: After forming the opening, the method further includes performing ion implantation on the substrate at the bottom of the opening to form a source region in the substrate.

4. The method for preparing a split-gate flash memory cell according to claim 1, wherein: The material of the dielectric layer includes silicon oxide.

5. The method for preparing a split-gate flash memory cell according to claim 1, wherein: After filling the erase gate in the opening and before forming the patterned photoresist layer, the method further includes: A third oxide layer is formed on the erase gate and the dielectric layer.

6. The method for preparing a split-gate flash memory cell according to claim 1, wherein: Before forming a word line gate on the dielectric layer and the floating gate away from the erase gate, a fourth oxide layer is formed on the dielectric layer and the floating gate away from the erase gate, and the word line gate covers at least a portion of the surface of the fourth oxide layer.

7. The method for preparing a split-gate flash memory cell according to claim 1, wherein: After forming a word line gate on the dielectric layer and on a side of the floating gate away from the erase gate, the method further includes: Ion implantation is performed on the substrate outside the word line gate to form a drain region in the substrate.

8. The method for preparing a split-gate flash memory cell according to claim 1, wherein: The steps of forming the word line gate electrical connection and the erase gate electrical connection include: Etching the passivation layer to form a word line gate contact hole and an erase gate contact hole in the passivation layer, respectively exposing the word line gate and the erase gate; and Metal material is filled in the word line gate contact hole and the erase gate contact hole to form a word line gate plug and an erase gate plug, respectively. A word line gate metal pattern and an erase gate metal pattern are formed on the passivation layer. The word line gate metal pattern is electrically connected to the word line gate plug to form the word line gate electrical connection. The erase gate metal pattern is electrically connected to the erase gate plug to form the erase gate electrical connection.

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