An on-chip voltage measurement circuit

Abstract

The invention discloses an on-chip voltage measurement circuit. The on-chip voltage measurement circuit includes: an oscillation ring module, a phase sampler, a phase calculator, a pipeline register and a phase subtractor. The oscillation ring module self-excites to generate a periodic oscillation signal, and the number of oscillation cycles of the oscillation ring module is counted; the phase sampler samples the oscillation signal and the number of oscillation cycles under the control of a sampling clock signal to obtain a sampled oscillation signal and the number of sampled oscillation cycles; the phase calculator calculates the cumulative phase of the oscillation ring module according to the sampled oscillation signal and the number of sampled oscillation cycles; the pipeline register outputs the cumulative phase of the oscillation ring module in the previous sampling cycle under the control of the sampling clock signal; the phase subtractor calculates the phase change value of the oscillation ring module in the current sampling cycle according to the current cumulative phase and the cumulative phase of the oscillation ring module in the previous sampling cycle; the phase change value represents the on-chip voltage. The invention can realize accurate and high-speed measurement of the internal voltage of the chip.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to an on-chip voltage measurement circuit. Background Art

[0002] For large chips, especially AI computing chips, whether it is chip performance analysis (Profiling) or adaptive dynamic voltage frequency scaling (Adaptive Voltage Frequency Scaling, AVFS) when the chip is working, the chip is required to have internal voltage sensing capabilities. However, most solutions on the market currently measure the chip voltage through an external voltage measurement device, which has the following problems: 1. Due to the voltage drop in the chip power supply network, there is a large error between the external voltage of the chip and the internal voltage of the chip. 2. For AVFS, since the voltage measurement device is outside the chip, the feedback loop is long and cannot respond quickly. Therefore, the voltage measurement circuit of the existing chip has the problems of large errors and slow response. Summary of the invention

[0003] The invention provides an on-chip voltage measurement circuit to achieve accurate and high-speed measurement of the internal voltage of a chip.

[0004] An embodiment of the present invention provides an on-chip voltage measurement circuit, including:

[0005] Oscillating ring module; the oscillating ring module is used to self-excite to generate a periodic oscillation signal, and to count the number of oscillation cycles of the oscillating ring module and output it;

[0006] A phase sampler; the phase sampler is electrically connected to the oscillation ring module, accesses the oscillation signal and the oscillation cycle number, and the phase sampler accesses a sampling clock signal; the phase sampler is used to sample the oscillation signal and the oscillation cycle number under the control of the sampling clock signal to obtain a sampled oscillation signal and a sampled oscillation cycle number;

[0007] A phase calculator; the phase calculator is electrically connected to the phase sampler; the phase calculator is used to calculate the accumulated phase of the oscillation ring module according to the sampled oscillation signal and the number of sampled oscillation cycles;

[0008] A pipeline register; the pipeline register is electrically connected to the phase calculator, and the pipeline register is connected to the sampling clock signal; the pipeline register is used to output the accumulated phase of the oscillation ring module in the previous sampling cycle under the control of the sampling clock signal;

[0009] A phase subtractor; the phase subtractor is electrically connected to the phase calculator and the pipeline register respectively; the phase subtractor is used to calculate the phase change value of the oscillation ring module in the current sampling period according to the current accumulated phase and the accumulated phase of the oscillation ring module in the previous sampling period; the phase change value is used to characterize the on-chip voltage.

[0010] Optionally, the oscillating ring module includes:

[0011] An oscillation ring unit, comprising n oscillation signal output terminals; n is a non-zero even number; the oscillation ring unit is used to self-excite to generate a periodic oscillation signal, and the oscillation signal output terminals output the oscillation signal;

[0012] An oscillation counter; a clock end of the oscillation counter is electrically connected to the nth oscillation signal output end of the oscillation ring unit, and the oscillation counter is used to count the number of oscillation cycles of the oscillation ring unit.

[0013] Optionally, the oscillation ring unit comprises: a first AND gate and n-1 first inverters connected in series; the first input end of the first AND gate is connected to an oscillation enable signal, and the second input end of the first AND gate is electrically connected to the output end of the n-1th first inverter; the oscillation ring unit is used to self-excite and generate a periodic oscillation signal when the oscillation enable signal is valid; the output end of the first AND gate and the output ends of all the first inverters serve as n oscillation signal output ends of the oscillation ring unit;

[0014] The oscillation counter comprises:

[0015] A rising edge triggered counter; a clock end of the rising edge triggered counter is electrically connected to the output end of the n-1th first inverter; the rising edge triggered counter is triggered by the rising edge of the output signal of the n-1th first inverter, and is used to count the number of rising edge oscillation cycles of the oscillation ring unit;

[0016] A falling edge triggered counter; the clock end of the falling edge triggered counter is electrically connected to the output end of the n-1th first inverter; the falling edge triggered counter is triggered by the falling edge of the output signal of the n-1th first inverter, and is used to count the number of falling edge oscillation cycles of the oscillation ring unit.

[0017] Optionally, the oscillation ring module outputs n oscillation signals; n is a non-zero even number; the oscillation period number includes the rising edge oscillation period number and the falling edge oscillation period number;

[0018] The phase sampler comprises:

[0019] A first sampling unit comprises a clock terminal, a data input terminal and an output terminal; the clock terminal of the first sampling unit is connected to the sampling clock signal, and the data input terminal of the first sampling unit is connected to the rising edge oscillation cycle number; the first sampling unit is used to sample the rising edge oscillation cycle number under the control of the sampling clock signal and output a first sampling cycle number;

[0020] The second sampling unit comprises a clock terminal, a data input terminal and an output terminal; the clock terminal of the second sampling unit is connected to the sampling clock signal, and the data input terminal of the second sampling unit is connected to the falling edge oscillation cycle number; the second sampling unit is used to sample the falling edge oscillation cycle number under the control of the sampling clock signal and output a second sampling cycle number;

[0021] The third sampling unit comprises a clock end, n data input ends and n output ends; the clock end of the third sampling unit is connected to the sampling clock signal; the n data input ends of the third sampling unit are sequentially connected to the n oscillation signals output by the oscillation ring module; the third sampling unit is used to sample the n oscillation signals under the control of the sampling clock signal and output n sampled oscillation signals.

[0022] Optionally, the phase calculator comprises:

[0023] A fractional part calculator; the fractional part calculator is electrically connected to the third sampling unit; the fractional part calculator is used to calculate the fractional part of the accumulated phase according to n sampled oscillation signals;

[0024] An integer part calculator; the integer part calculator is electrically connected to the first sampling unit, the second sampling unit and the fractional part calculator respectively; the integer part calculator is used to calculate the integer part of the accumulated phase according to the fractional part of the accumulated phase, the first sampling cycle number and the second sampling cycle number.

[0025] Optionally, the decimal part calculator comprises:

[0026] An oscillation signal polarity adjustment unit, comprising n / 2 buffers and n / 2 second inverters; the input ends of the n / 2 buffers are electrically connected to the odd-numbered output ends of the third sampling unit in a one-to-one correspondence; the output end of the k-th buffer serves as the 2k-1-th output end of the oscillation signal polarity adjustment unit; the input ends of the n / 2 second inverters are electrically connected to the even-numbered output ends of the third sampling unit in a one-to-one correspondence; the output end of the k-th second inverter serves as the 2k-th output end of the oscillation signal polarity adjustment unit; 1≤k≤n / 2;

[0027] An oscillation signal edge detection unit, comprising n XOR gates; the output ends of the n XOR gates serve as n output ends of the oscillation signal edge detection unit; the first input end of the first XOR gate is electrically connected to the first output end of the oscillation signal polarity adjustment unit, and the second input end of the first XOR gate is electrically connected to the input end of the n / 2 second inverter; the first input end of the j-th XOR gate is electrically connected to the j-1-th output end of the oscillation signal polarity adjustment unit, and the second input end of the j-th XOR gate is electrically connected to the j-th output end of the oscillation signal polarity adjustment unit; 2≤j≤n;

[0028] An oscillation clock phase detection unit comprises 2n second AND gates; the output ends of the 2n second AND gates serve as the 2n output ends of the oscillation clock phase detection unit; the first input end of the i1th second AND gate is electrically connected to the i1th output end of the oscillation signal edge detection unit, and the second input end of the i1th second AND gate is connected to the inverted signal of the i1+n / 2th output signal of the oscillation signal polarity adjustment unit; 1≤i1≤n / 2; the first input end of the i2th second AND gate is electrically connected to the i2th output end of the oscillation signal edge detection unit, and the second input end of the i2th second AND gate is connected to the i2- n / 2 output terminals are electrically connected; n / 2+1≤i2≤n; the first input terminal of the i3th second AND gate is electrically connected to the i3-nth output terminal of the oscillation signal edge detection unit, and the second input terminal of the i3th second AND gate is electrically connected to the i3-n / 2th output terminal of the oscillation signal polarity adjustment unit; n+1≤i3≤3n / 2; the first input terminal of the i4th second AND gate is electrically connected to the i4-nth output terminal of the oscillation signal edge detection unit, and the second input terminal of the i4th second AND gate is connected to the inverted signal of the i4-3n / 2th output signal of the oscillation signal polarity adjustment unit; 3n / 2+1≤i4≤2n;

[0029] Phase encoder; the phase encoder is electrically connected to all output ends of the oscillation clock phase detection unit, and is used to encode the output signal of the oscillation clock phase detection unit to obtain the fractional part of the accumulated phase.

[0030] Optionally, the integer part calculator comprises:

[0031] A first comparator; a first input terminal of the first comparator is connected to a first threshold, and a second input terminal of the first comparator is connected to a fractional part of the accumulated phase;

[0032] A second comparator; a first input terminal of the second comparator is connected to a second threshold, and a second input terminal of the second comparator is connected to a fractional part of the accumulated phase;

[0033] A first selector; a control end of the first selector is electrically connected to the output end of the second comparator, and a first input end of the first selector is electrically connected to the output end of the second sampling unit;

[0034] a first subtractor; a first input end of the first subtractor is electrically connected to an output end of the second sampling unit, a second input end of the first subtractor is connected to an oscillation period count adjustment constant, and an output end of the first subtractor is electrically connected to a second input end of the first selector;

[0035] an OR gate; a first input terminal of the OR gate is electrically connected to the output terminal of the first comparator, and a second input terminal of the OR gate is electrically connected to the output terminal of the second comparator;

[0036] a second selector; a control end of the second selector is electrically connected to the output end of the OR gate, a first input end of the second selector is electrically connected to the output end of the first sampling unit, a second input end of the second selector is electrically connected to the output end of the first selector, and an output end of the second selector outputs the integer part of the accumulated phase.

[0037] Optionally, the accumulated phase of the oscillating ring module includes: an integer part of the accumulated phase and a decimal part of the accumulated phase

[0038] The pipeline register comprises:

[0039] A first register; a clock end of the first register is connected to the sampling clock signal, an input end of the first register is connected to the integer part of the accumulated phase, and an output end of the first register outputs the integer part of the accumulated phase of the oscillation ring module in the previous sampling cycle;

[0040] The second register; the clock end of the second register is connected to the sampling clock signal, the input end of the second register is connected to the fractional part of the accumulated phase, and the output end of the second register outputs the fractional part of the accumulated phase of the oscillation ring module in the previous sampling cycle.

[0041] Optionally, the accumulated phase of the oscillation ring module includes: an integer part of the accumulated phase and a decimal part of the accumulated phase;

[0042] The phase subtractor comprises:

[0043] A first adder; a first input terminal of the first adder is connected to the integer part of the current accumulated phase, and a second input terminal of the first adder is connected to the decimal part of the current accumulated phase;

[0044] A second adder; a first input end of the second adder is connected to the integer part of the accumulated phase of the oscillation ring module in the previous sampling period, and a second input end of the second adder is connected to the decimal part of the accumulated phase of the oscillation ring module in the previous sampling period;

[0045] A second subtractor; a first input end of the second subtractor is electrically connected to the output end of the first adder, a second input end of the second subtractor is electrically connected to the output end of the second adder, and the output end of the second subtractor outputs the phase change value of the oscillation ring module in the current sampling period.

[0046] Optionally, the phase subtractor further includes:

[0047] A third comparator; a first input terminal of the third comparator is connected to the integer part of the current accumulated phase, and a second input terminal of the third comparator is connected to the integer part of the accumulated phase of the oscillation ring module in the previous sampling period;

[0048] A third adder; a first input terminal of the third adder is connected to the integer part of the current accumulated phase, and a second input terminal of the third adder is connected to the phase integer adjustment value;

[0049] A third selector; the first input end of the third selector is connected to the integer part of the current accumulated phase, the second input end of the third selector is electrically connected to the output end of the third adder; the output end of the third selector is electrically connected to the first input end of the first adder.

[0050] The embodiment of the present invention provides a modular on-chip voltage measurement circuit. By integrating this circuit module on the chip, it is possible to achieve relatively accurate high-speed real-time measurement of the internal voltage of the chip. Specifically, the on-chip measurement circuit is composed of an oscillation ring module, a phase sampler, a phase calculator, a pipeline register and a phase subtractor. Among them, the oscillation ring module can follow the change of the on-chip voltage in real time, self-excite to generate an oscillation signal, and other modules directly sample and process the output signal of the oscillation ring module. In this way, it is equivalent to directly responding to the internal voltage of the chip, which not only effectively reduces the influence of the voltage difference between the inside and outside of the chip on the accuracy of the voltage measurement, but also avoids the influence of the length of the electrical signal transmission path on the response speed of the measurement circuit. And when using the on-chip voltage measurement circuit, by controlling the sampling frequency of the sampling clock signal, the accuracy of the voltage measurement can be controlled, and the measurement process is more flexible and controllable. Therefore, compared with the prior art, the embodiment of the present invention can achieve accurate and high-speed measurement of the internal voltage of the chip.

[0051] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 is a schematic structural diagram of an on-chip voltage measurement circuit provided by an embodiment of the present invention;

[0054] Figure 2 is a schematic structural diagram of an oscillating ring module provided by an embodiment of the present invention;

[0055] Figure 3 is a structural schematic diagram of a phase sampler provided by an embodiment of the present invention;

[0056] Figure 4 is a structural schematic diagram of a decimal part calculator provided by an embodiment of the present invention;

[0057] Figure 5 is a structural schematic diagram of an integer part calculator provided by an embodiment of the present invention;

[0058] Figure 6 It is a schematic diagram of the connection relationship between a pipeline register and a phase subtractor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0060] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0061] An embodiment of the present invention provides an on-chip voltage measurement circuit. Figure 1 is a schematic diagram of the structure of an on-chip voltage measurement circuit provided by an embodiment of the present invention. Figure 1 The on-chip voltage measurement circuit includes: an oscillating ring module 10, a phase sampler 20, a phase calculator 30, a pipeline register 40 and a phase subtractor 50.

[0062] Among them, the oscillation ring module 10 is used to self-excite to generate a periodic oscillation signal, and to count and output the number of oscillation cycles of the oscillation ring module 10. The phase sampler 20 is electrically connected to the oscillation ring module 10, and receives the oscillation signal and the number of oscillation cycles, and the phase sampler 20 receives the sampling clock signal sample_clk; the phase sampler 20 is used to sample the oscillation signal and the number of oscillation cycles under the control of the sampling clock signal sample_clk, and obtain the sampled oscillation signal and the sampled oscillation cycle number. The phase calculator 30 is electrically connected to the phase sampler 20; the phase calculator 30 is used to calculate the cumulative phase of the oscillation ring module 10 according to the sampled oscillation signal and the sampled oscillation cycle number. The pipeline register 40 is electrically connected to the phase calculator 30, and the pipeline register 40 receives the sampling clock signal sample_clk; the pipeline register 40 is used to output the cumulative phase of the oscillation ring module 10 in the previous sampling cycle under the control of the sampling clock signal sample_clk. The phase subtractor 50 is electrically connected to the phase calculator 30 and the pipeline register 40 respectively; the phase subtractor 50 is used to calculate the phase change value phase_delta of the oscillation ring module 10 in the current sampling period according to the current accumulated phase and the accumulated phase of the oscillation ring module 10 in the previous sampling period; the phase change value phase_delta is used to characterize the on-chip voltage.

[0063] Exemplarily, the oscillation ring module 10 includes n oscillation signal output terminals, which output n-level oscillation signals respectively; n is a non-zero even number. After two rounds of step-by-step output of the first-level oscillation signal to the n-level oscillation signal, it can be considered that an oscillation cycle has passed; for example, the n-level oscillation signal changes from a high level state to a low level, and then changes to a high level state again. This complete change process is an oscillation cycle. The on-chip voltage measurement circuit is modularly integrated on the chip, based on the oscillation ring (Ring Oscillator), and characterizes the voltage fluctuation by the change of the oscillation frequency. The principle is as follows: within a certain voltage range, the oscillation frequency is approximately linearly positively correlated with the voltage of the chip, so the high and low oscillation frequency can characterize the high and low voltage on the chip. The average oscillation frequency of the oscillation ring module 10 within a sampling period can be reflected by the cumulative phase change value of the oscillation ring module 10 within the sampling period. For example, if the sampling frequency is 1Ghz, and the cumulative phase change within a certain sampling period is 4π, it means that the oscillation frequency within this period is 2Ghz. If the cumulative phase change is 0.5π, it means that the clock frequency is 500Mhz. As described above, the on-chip voltage measurement circuit measures and calculates the phase change value phase_delta of the oscillation ring module 10, and combines the sampling frequency of the sampling clock signal sample_clk to obtain the oscillation frequency of the oscillation ring module 10, thereby obtaining the value of the on-chip voltage. When the sampling frequency is constant, the phase change value phase_delta has a certain corresponding relationship with the on-chip voltage, and the specific value of the on-chip voltage can be obtained by only calculating the phase change value phase_delta in real time.

[0064] The embodiment of the present invention provides a modular on-chip voltage measurement circuit. By integrating this circuit module on the chip, a relatively accurate high-speed real-time measurement of the internal voltage of the chip can be achieved. Specifically, the on-chip measurement circuit is composed of an oscillation ring module 10, a phase sampler 20, a phase calculator 30, a pipeline register 40 and a phase subtractor 50. Among them, the oscillation ring module 10 can follow the change of the on-chip voltage in real time, self-excite to generate an oscillation signal, and other modules directly sample and process the output signal of the oscillation ring module 10. In this way, it is equivalent to directly responding to the internal voltage of the chip, which not only effectively reduces the influence of the voltage difference between the inside and outside of the chip on the accuracy of the voltage measurement, but also avoids the influence of the length of the electrical signal transmission path on the response speed of the measurement circuit. And when using the on-chip voltage measurement circuit, by controlling the sampling frequency of the sampling clock signal sample_clk, the accuracy of the voltage measurement can be controlled, and the measurement process is more flexible and controllable. Therefore, compared with the prior art, the embodiment of the present invention can achieve accurate and high-speed measurement of the internal voltage of the chip.

[0065] On the basis of the above embodiments, the on-chip voltage measurement circuit may optionally further include a voltage conversion module, which is connected to the phase change value phase_delta and the sampling clock signal sample_clk, and is used to calculate the average oscillation frequency of the oscillation ring module 10 in the current sampling period according to the sampling frequency of the sampling clock signal sample_clk and the phase change value phase_delta, and then calculate the current value of the on-chip voltage according to the corresponding relationship between the average oscillation frequency and the on-chip voltage. Exemplarily, if the output of the on-chip voltage measurement circuit is used to control the actions of other parts of the chip, the control logic of other parts can be set according to the phase change value phase_delta, and the phase change value phase_delta can be directly output; the control logic of other parts can also be set according to the on-chip voltage, and the current value of the on-chip voltage can be output.

[0066] The above-mentioned embodiments exemplarily provide the overall module structure of the on-chip voltage measurement circuit. The specific structure that each module may have is described below, but it is not intended to limit the present invention.

[0067] Figure 2 is a schematic diagram of the structure of an oscillating ring module provided by an embodiment of the present invention. Figure 2 In one embodiment, optionally, the oscillation ring module 10 includes: an oscillation ring unit 110 and an oscillation counter 120. The oscillation ring unit 110 is used to self-excite and generate a periodic oscillation signal. The oscillation ring unit 110 includes n oscillation signal output terminals, which are respectively used to output n-level oscillation signals. The clock terminal of the oscillation counter 120 is electrically connected to the nth oscillation signal output terminal of the oscillation ring unit 110, and the oscillation counter 120 is used to count and output the number of oscillation cycles of the oscillation ring unit 110.

[0068] Specifically, the oscillation ring unit 110 includes: a first AND gate AND1 and n-1 first inverters (INV1_1 to INV1_n-1, respectively) connected in series. The first AND gate AND1 is a two-input AND gate, whose first input terminal is connected to the oscillation enable signal osc_en, and the second input terminal of the first AND gate AND1 is electrically connected to the output terminal of the n-1 first inverter INV1_n-1. That is, the first AND gate AND1 and the n-1 first inverters are connected in series end to end. The oscillation ring unit 110 is used to self-excite to generate a periodic oscillation signal when the oscillation enable signal osc_en is valid (output logic 1), and the oscillation frequency depends on the delay of the oscillation ring unit 110. Among them, the first AND gate AND1 is located at the first stage of the oscillation ring unit 110, and its output terminal serves as the first oscillation signal output terminal, outputting the first oscillation signal AND1_out. The 1st to n-1th first inverters are sequentially located at the 2nd to nth stages of the oscillation ring unit 110, and the output ends of the n-1th first inverters are sequentially used as the 2nd to nth oscillation signal output ends, and the 2nd to nth oscillation signals (INV1_1_out to INV1_n-1_out, respectively) are sequentially output.

[0069] Continue to see Figure 2 On the basis of the above embodiments, optionally, the oscillation counter 120 includes: a rising edge triggered counter Counter1 and a falling edge triggered counter Counter2. The clock end of the rising edge triggered counter Counter1 is electrically connected to the output end of the n-1th first inverter INV1_n-1; the rising edge triggered counter Counter1 is triggered by the rising edge of the output signal INV1_n-1_out of the n-1th first inverter INV1_n-1, and is used to count the number of rising edge oscillation cycles Counter1_out of the oscillation ring unit 110. The clock end of the falling edge triggered counter Counter2 is electrically connected to the output end of the n-1th first inverter INV1_n-1; the falling edge triggered counter Counter2 is triggered by the falling edge of the output signal INV1_n-1_out of the n-1th first inverter INV1_n-1, and is used to count the number of falling edge oscillation cycles Counter2_out of the oscillation ring unit 110.

[0070] Among them, since the subsequent sampling step is asynchronous sampling, setting the oscillation counter 120 specifically includes two counters triggered by the rising edge and the falling edge, which can avoid the metastable problem that may exist in the asynchronous sampling process and cause phase calculation errors. Since the process of the n-th level oscillation signal INV1_n-1_out changing from a high level to a low level and then to a high level, or from a low level to a high level and then to a low level can be regarded as a complete oscillation cycle, then the count triggering time of the rising edge triggering counter Counter1 and the falling edge triggering counter Counter2 is just half an oscillation cycle apart. In this way, in the asynchronous sampling process, the current sampling moment will always be far away from the count triggering time of at least one counter, so the sampling result of at least one counter can always be guaranteed to be credible, thereby ensuring the accuracy of the subsequent cumulative phase calculation results.

[0071] Exemplarily, the counter widths of the rising edge triggered counter Counter1 and the falling edge triggered counter Counter2 are both m, where m is a non-zero integer; both can adopt a cyclic counting mode for counting, and restart counting from zero after an overflow occurs.

[0072] Figure 3 is a schematic diagram of the structure of a phase sampler provided by an embodiment of the present invention. Figure 3 In one implementation, optionally, the phase sampler 20 includes: a first sampling unit 210 , a second sampling unit 220 and a third sampling unit 230 .

[0073] The first sampling unit 210 includes a clock terminal, a data input terminal and an output terminal; the clock terminal of the first sampling unit 210 is connected to the sampling clock signal sample_clk, and the data input terminal of the first sampling unit 210 is connected to the rising edge oscillation cycle number Counter1_out; the first sampling unit 210 is used to sample the rising edge oscillation cycle number Counter1_out under the control of the sampling clock signal sample_clk, and output the first sampling cycle number COUNT1. Exemplarily, the first sampling unit 210 can be composed of a common register Sampler1.

[0074] The second sampling unit 220 includes a clock terminal, a data input terminal and an output terminal; the clock terminal of the second sampling unit 220 is connected to the sampling clock signal sample_clk, and the data input terminal of the second sampling unit 220 is connected to the falling edge oscillation cycle number Counter2_out; the second sampling unit 220 is used to sample the falling edge oscillation cycle number Counter2_out under the control of the sampling clock signal sample_clk, and output the second sampling cycle number COUNT2. Exemplarily, the first sampling unit 210 can be composed of a common register Sampler2.

[0075] The third sampling unit 230 includes a clock terminal, n data input terminals and n output terminals; the clock terminal of the third sampling unit 230 is connected to the sampling clock signal sample_clk; the n data input terminals of the third sampling unit 230 are sequentially connected to the n oscillation signals output by the oscillation ring module 10; the third sampling unit 230 is used to sample the n oscillation signals under the control of the sampling clock signal sample_clk, and output n sampled oscillation signals (osc_1 to osc_n in sequence). Exemplarily, the third sampling unit 230 can be composed of n high-speed registers SAFF, and the input terminals of the n high-speed registers SAFF are sequentially used as the n data input terminals of the third sampling unit 230; the output terminals of the n high-speed registers SAFF are sequentially used as the n data output terminals of the third sampling unit 230.

[0076] Optionally, based on the above-mentioned embodiments, the phase calculator 30 includes: a fractional part calculator and an integer part calculator. The fractional part calculator is electrically connected to the third sampling unit 230; the fractional part calculator 230 is used to calculate the fractional part of the accumulated phase according to n sampled oscillation signals. The integer part calculator is electrically connected to the first sampling unit 210, the second sampling unit 220 and the fractional part calculator respectively; the integer part calculator is used to calculate the integer part of the accumulated phase according to the fractional part of the accumulated phase, the first sampling cycle number COUNT1 and the second sampling cycle number COUNT2. The integer part of the accumulated phase is used to characterize the number of complete oscillation cycles that the oscillation ring module 10 has gone through; the fractional part of the accumulated phase is used to characterize the progress of the current oscillation cycle when the oscillation ring module 10 has not completed the current oscillation cycle within the current cycle. This embodiment calculates the fractional part and the integer part of the accumulated phase respectively, which can make the calculation result of the accumulated phase more accurate and reliable. Next, combined with Figure 4 and Figure 5 , the specific structure of the phase calculator 30 is explained.

[0077] Figure 4 is a schematic diagram of the structure of a decimal part calculator provided by an embodiment of the present invention. Figure 4In one embodiment, the fractional part calculator 310 includes: an oscillation signal polarity adjustment unit 311, an oscillation signal edge detection unit 312, an oscillation clock phase detection unit 313 and a phase encoder 314. Among them, the oscillation signal polarity adjustment unit 311 is used to invert the even-numbered sampling oscillation signal so that the sampling oscillation signals of each level can be compared using the same method after processing. The output of the oscillation signal edge detection unit 312 represents the position of the oscillation signal edge (rising edge or falling edge) in the oscillation ring unit 110. The oscillation clock phase detection unit 313 is used to distinguish whether the oscillation signal edge is a rising edge or a falling edge (indicating the direction of the oscillation signal edge), thereby obtaining the actual phase of the oscillation ring unit 110 in the current oscillation cycle. The phase encoder 314 is used to encode the output signal of the oscillation clock phase detection unit 313, and the fractional part phase_frac of the accumulated phase is obtained after encoding.

[0078] The oscillation signal polarity adjustment unit 311 includes n / 2 buffers and n / 2 second inverters. The input ends of the n / 2 buffers are electrically connected to the odd-numbered output ends of the third sampling unit 230 in a one-to-one correspondence, and are sequentially connected to each odd-numbered sampling oscillation signal, that is, osc_1, osc_3, ..., osc_n-1. The output end of the kth buffer serves as the 2k-1th output end of the oscillation signal polarity adjustment unit 311; that is, the output ends of each buffer serve as each odd-numbered output end of the oscillation signal polarity adjustment unit 311 in turn, and output rosc_1, rosc_3, ..., rosc_n-1 in turn. The input ends of the n / 2 second inverters are electrically connected to the even-numbered output ends of the third sampling unit 230 in a one-to-one correspondence, and are sequentially connected to each even-numbered sampling oscillation signal, that is, osc_2, osc_4, ..., osc_n. The output end of the kth second inverter serves as the 2kth output end of the oscillation signal polarity adjustment unit 311; that is, the output ends of each second inverter serve as the output ends of each even-numbered stage of the oscillation signal polarity adjustment unit 311 in turn, and output rosc_2, rosc_4, ..., rosc_n in turn. 1≤k≤n / 2. After adjustment by the oscillation signal polarity adjustment unit 311, among the n output signals of the oscillation signal polarity adjustment unit 311, the position of the oscillation signal edge is used as the boundary, and the level of the output signal before and after the boundary is different.

[0079] The oscillation signal edge detection unit 312 includes n XOR gates; the output ends of the n XOR gates serve as n output ends of the oscillation signal edge detection unit 312, and output xor_1 to xor_n in sequence. The first input end of the first XOR gate is electrically connected to the first output end of the oscillation signal polarity adjustment unit 311, and the second input end of the first XOR gate is electrically connected to the input end of the n / 2 second inverter; the first input end of the j-th XOR gate is electrically connected to the j-1-th output end of the oscillation signal polarity adjustment unit 311, and the second input end of the j-th XOR gate is electrically connected to the j-th output end of the oscillation signal polarity adjustment unit 311; 2≤j≤n. In actual application, among the n output signals of the oscillation signal edge detection unit 312, only the output signal at the limit defined by the position of the oscillation signal edge is logical 1. That is, the position of the logic 1 output by the oscillation signal edge detection unit 312 can indicate the position of the oscillation signal edge, but the signal cannot indicate the direction of the signal edge (that is, it cannot indicate whether the oscillation signal edge is in the upper half cycle or the lower half cycle). Therefore, the oscillation clock phase detection unit 313 is also needed to make a judgment.

[0080] The oscillation clock phase detection unit 313 includes 2n second AND gates; the output ends of the 2n second AND gates serve as 2n output ends of the oscillation clock phase detection unit 313, and output P_1 to P_2n in sequence.

[0081] The first input terminal of the i1th second AND gate is electrically connected to the i1th output terminal of the oscillation signal edge detection unit 312, and the second input terminal of the i1th second AND gate is connected to the inverted signal of the i1+n / 2th output signal of the oscillation signal polarity adjustment unit 311; 1≤i1≤n / 2.

[0082] The first input terminal of the i2th second AND gate is electrically connected to the i2th output terminal of the oscillation signal edge detection unit 312, and the second input terminal of the i2th second AND gate is electrically connected to the i2-n / 2th output terminal of the oscillation signal polarity adjustment unit 311; n / 2+1≤i2≤n.

[0083] The first input terminal of the i3th second AND gate is electrically connected to the i3-nth output terminal of the oscillation signal edge detection unit 312, and the second input terminal of the i3th second AND gate is electrically connected to the i3-n / 2th output terminal of the oscillation signal polarity adjustment unit 311; n+1≤i3≤3n / 2.

[0084] The first input terminal of the i4th second AND gate is electrically connected to the i4-nth output terminal of the oscillation signal edge detection unit 312, and the second input terminal of the i4th second AND gate is connected to the inverted signal of the i4-3n / 2th output signal of the oscillation signal polarity adjustment unit 311; 3n / 2+1≤i4≤2n.

[0085] The oscillation clock phase detection unit 313 has only one output signal of logic 1; when there is logic 1 in the output of the 1st to nth second AND gates, it indicates that the oscillation signal edge is in the first half of the oscillation cycle; when there is logic 1 in the output of the n+1th to 2nth second AND gates, it indicates that the oscillation signal edge is in the second half of the oscillation cycle. The output of the oscillation clock phase detection unit 313 is a phase encoding in the form of a one-hot code.

[0086] In this embodiment, the phase of the oscillation signal can be obtained by the output signal of the oscillation clock phase detection unit 313, combined with the sampling result of the oscillation signal after or before the position of the oscillation signal edge, through the AND operation. In addition, in this embodiment, a second AND gate (i.e., the 1st to n / 2nd second AND gate and the n+1st to 3n / 2nd second AND gate) connected to the output end of the first n / 2 XOR gates is set to connect to the last n / 2 output signals of the oscillation signal polarity adjustment unit 311 or its inverted signal; and a second AND gate (i.e., the n / 2+1st to nth second AND gate and the 3n / 2+1st to 2nth second AND gate) connected to the output end of the last n / 2 XOR gates is set to connect to the first n / 2 output signals of the oscillation signal polarity adjustment unit 311 or its inverted signal. In this way, it is equivalent to that the output signal of each XOR gate is ANDed with the processing result of the oscillation signal that is one quarter of the oscillation period away from it, which can ensure the accuracy of the output signal of the second AND gate. Exemplarily, the inverted signal (~rosc_1 to ~rosc_n) of the output signal (rosc_1 to rosc_n) of the oscillation signal polarity adjustment unit 311 can be obtained by connecting an inverter to each output end of the oscillation signal polarity adjustment unit 311; in order to reduce the number of inverters, the even-level input signal (osc_2, osc_4, ..., osc_n) of the oscillation signal polarity adjustment unit 311 can also be directly used as the inverted signal (~rosc_2, ~rosc_4, ..., ~rosc_n) of the even-level output signal of the oscillation signal polarity adjustment unit 311.

[0087] The phase encoder 314 is electrically connected to all output ends of the oscillation clock phase detection unit 313 . The phase encoder 314 performs binary encoding on the output of the oscillation clock phase detection unit 313 , for example, outputs a binary code with a bit width of log22n.

[0088] Figure 5 is a schematic diagram of the structure of an integer part calculator provided by an embodiment of the present invention. Figure 5 In one implementation, illustratively, the integer part calculator 320 includes: a first comparator Comparator1, a second comparator Comparator2, a first selector MUX1, a first subtractor 321, an OR gate 322, and a second selector MUX2.

[0089] The first input terminal of the first comparator Comparator1 is connected to the first threshold Safe_Min, and the second input terminal of the first comparator Comparator1 is connected to the fractional part phase_frac of the accumulated phase. The first input terminal of the second comparator Comparator2 is connected to the second threshold Safe_Max, and the second input terminal of the second comparator Comparator2 is connected to the fractional part phase_frac of the accumulated phase. The control terminal of the first selector MUX1 is electrically connected to the output terminal of the second comparator Comparator2; the first input terminal of the first selector MUX1 is electrically connected to the output terminal of the second sampling unit, and connected to the second sampling cycle number COUNT2. The first input terminal of the first subtractor 321 is electrically connected to the output terminal of the second sampling unit, and connected to the second sampling cycle number COUNT2; the second input terminal of the first subtractor 321 is connected to the oscillation cycle count adjustment constant const1; the output terminal of the first subtractor 321 is electrically connected to the second input terminal of the first selector MUX1. The first input terminal of the OR gate 322 is electrically connected to the output terminal of the first comparator Comparator1, and the second input terminal of the OR gate 322 is electrically connected to the output terminal of the second comparator Comparator2. The control end of the second selector MUX2 is electrically connected to the output end of the OR gate 322; the first input end of the second selector MUX2 is electrically connected to the output end of the first sampling unit, and is connected to the first sampling cycle number COUNT1; the second input end of the second selector MUX2 is electrically connected to the output end of the first selector MUX1; the output end of the second selector MUX2 outputs the integer part phase_int of the accumulated phase.

[0090] In the integer part calculator 320, the two parameters of the first threshold Safe_Min and the second threshold Safe_Max can be set by the user according to actual needs. The first comparator Comparator1 and the second comparator Comparator2 compare the fractional part phase_frac of the accumulated phase with the first threshold Safe_Min and the second threshold respectively; the output of the second comparator Comparator2 controls the output of the first selector MUX1; the outputs of the first comparator Comparator1 and the second comparator Comparator2 are controlled by the output of the second selector MUX2 after the OR operation of the OR gate 322, thereby determining the integer part phase_int of the accumulated phase.

[0091] Exemplarily, the first threshold Safe_Min defaults to a value converted from decimal n / 2 in the same format as the fractional part phase_frac of the accumulated phase, and the second threshold Safe_Max defaults to a value converted from decimal 3n / 2 in the same format as the fractional part phase_frac of the accumulated phase. The oscillation cycle count adjustment constant const1 can be a value converted from the decimal number 1 in the same format as the second sampling cycle number COUNT2.

[0092] The judgment results of the two comparators are used to indicate whether the first sampling cycle number COUNT1 and the second sampling cycle number COUNT2 are credible. Below, taking the counting result of the rising edge trigger counter Counter1, that is, the rising edge oscillation cycle number Counter1_out, as an example to divide the oscillation cycle, the output of the integer part calculator 320 under various comparison results is explained. At this time, if the oscillation signal enters the second half cycle, the falling edge oscillation cycle number Counter2_out is 1 more than the rising edge oscillation cycle number Counter1_out.

[0093] There are three comparison results:

[0094] a) If the fractional part of the accumulated phase phase_frac is less than the first threshold Safe_Min, it indicates that the current is in the first half of the oscillation cycle, and the oscillation signal is close to the count jump time of the rising edge trigger counter Counter1, then the falling edge trigger counter Counter2 has no metastable risk at this time, and the second sampling cycle number COUNT2 is credible; and the rising edge oscillation cycle number Counter1_out is the same as the falling edge oscillation cycle number Counter2_out. The second comparator Comparator2 outputs 0, controls the first selector MUX1 to output the second sampling cycle number COUNT2; the first comparator Comparator1 outputs 1, and the OR gate 322 outputs 1, controls the second selector MUX2 to output the output signal of the first selector MUX1, that is, the second sampling cycle number COUNT2. At this time, the second sampling cycle number COUNT2 is used as the integer part phase_int of the accumulated phase.

[0095] b) If the fractional part phase_frac of the accumulated phase is greater than the second threshold Safe_Max, it indicates that the current is in the second half of the oscillation cycle, and the oscillation signal is close to the count jump time of the rising edge trigger counter Counter1, then the falling edge trigger counter Counter2 has no metastable risk at this time, and the second sampling cycle number COUNT2 is credible; and the falling edge oscillation cycle number Counter2_out is 1 more than the rising edge oscillation cycle number Counter1_out. The second comparator Comparator2 outputs 1, controls the first selector MUX1 to output the value of the second sampling cycle number COUNT2 after the first subtractor 321 subtracts 1; the first comparator Comparator1 outputs 0, and the OR gate 322 outputs 1, controls the second selector MUX2 to output the output signal of the first selector MUX1. At this time, the result of the second sampling cycle number COUNT2 subtracting 1 is used as the integer part phase_int of the accumulated phase.

[0096] c) If the fractional part phase_frac of the accumulated phase is between the first threshold Safe_Min and the second threshold Safe_Max, it indicates that the oscillation signal is close to the count jump time of the falling edge trigger counter Counter2, so the rising edge trigger counter Counter1 has no metastable risk at this time, and the first sampling cycle number COUNT1 is credible. The first comparator Comparator1 and the second comparator Comparator2 both output 0, and the OR gate 322 outputs 0, controlling the second selector MUX2 to directly output the first sampling cycle number COUNT1. At this time, the first sampling cycle number COUNT1 is used as the integer part phase_int of the accumulated phase.

[0097] Figure 6 Schematic diagram of the connection relationship between a pipeline register and a phase subtractor provided by an embodiment of the present invention. Figure 6In one embodiment, optionally, the pipeline register 40 includes: a first register pipeline1 and a second register pipeline2. The clock end of the first register pipeline1 is connected to the sampling clock signal sample_clk, the input end of the first register pipeline1 is connected to the integer part of the accumulated phase phase_int, and the output end of the first register pipeline1 outputs the integer part of the accumulated phase of the oscillation ring module in the previous sampling cycle phase_int_pre. The clock end of the second register pipeline2 is connected to the sampling clock signal sample_clk, the input end of the second register pipeline2 is connected to the fractional part of the accumulated phase phase_frac, and the output end of the second register pipeline2 outputs the fractional part of the accumulated phase of the oscillation ring module in the previous sampling cycle phase_frac_pre.

[0098] Continue to see Figure 6 In one implementation, optionally, the phase subtractor 50 includes: a first adder 511, a second adder 512, and a second subtractor 513. The first input end of the first adder 511 is connected to the integer part phase_int of the current accumulated phase, the second input end of the first adder 511 is connected to the fractional part phase_frac of the current accumulated phase, and the output of the first adder 511 is the complete current accumulated phase. The first input end of the second adder 512 is connected to the integer part phase_int_pre of the accumulated phase of the oscillation ring module in the previous sampling period, the second input end of the second adder is connected to the fractional part phase_frac_pre of the accumulated phase of the oscillation ring module in the previous sampling period, and the output of the second adder 512 is the complete accumulated phase of the oscillation ring module in the previous sampling period. The first input end of the second subtractor 513 is electrically connected to the output end of the first adder 511 , the second input end of the second subtractor 513 is electrically connected to the output end of the second adder 512 , and the output end of the second subtractor 513 outputs the phase change value phase_delta of the oscillation ring module in the current sampling period.

[0099] Continue to see Figure 6On the basis of the above embodiments, optionally, the phase subtractor 50 further includes: a third comparator Comparator3, a third adder 514 and a third selector MUX3. The first input terminal of the third comparator Comparator3 is connected to the integer part phase_int of the current accumulated phase, and the second input terminal of the third comparator Comparator3 is connected to the integer part phase_int_pre of the accumulated phase of the oscillation ring module in the previous sampling period. The first input terminal of the third adder 514 is connected to the integer part phase_int of the current accumulated phase, and the second input terminal of the third adder 514 is connected to the phase integer adjustment value const2. The first input terminal of the third selector MUX3 is connected to the integer part phase_int of the current accumulated phase, and the second input terminal of the third selector MUX3 is electrically connected to the output terminal of the third adder 514; the output terminal of the third selector MUX3 is electrically connected to the first input terminal of the first adder 511.

[0100] The addition of the above structure is equivalent to considering the overflow of the oscillation counter. The specific process is as follows: First, the third comparator Comparator3 comparator 25 compares the integer part phase_int of the current accumulated phase and the integer part phase_int_pre of the accumulated phase of the oscillation ring module in the previous sampling period. The comparison results have the following two situations:

[0101] a) If the integer part phase_int of the current accumulated phase is greater than the integer part phase_int_pre of the accumulated phase of the oscillation ring module in the previous sampling period, it indicates that the oscillation counter has not overflowed in the current sampling period. The third comparator Comparator3 outputs 0, and controls the third selector MUX3 to directly output the integer part phase_int of the current accumulated phase. At this time, it is equivalent to not adjusting the integer part phase_int of the current accumulated phase.

[0102] b) If the integer part phase_int of the current accumulated phase is less than the integer part phase_int_pre of the accumulated phase of the oscillation ring module in the previous sampling period, it indicates that the oscillation counter has overflowed in the current sampling period. The third comparator Comparator3 outputs 1, controls the third selector MUX3 to output the value obtained by adding the integer part phase_int of the current accumulated phase to the phase integer adjustment value const2 through the third adder 514, and uses the adjusted result for subsequent phase calculation. When the output of the oscillation counter is binary and the counting width is m, the phase integer adjustment value const2 is the decimal 2 mThe converted binary value is used to make up for the overflow of the oscillation counter, thereby ensuring that the output of the phase subtractor 50 is normal.

[0103] In summary, the modular on-chip voltage measurement circuit provided in the embodiment of the present invention only includes a digital logic circuit, so its area is small and has no correlation with the process. It can be quickly integrated into any chip and can realize accurate high-speed real-time measurement of the internal voltage of the chip.

[0104] Exemplarily, n is 32. The oscillation ring unit 110 includes a first AND gate and 31 first inverters; the rising edge trigger counter Counter1 and the falling edge trigger counter Counter2 can both be 8-bit wide clock counters. The third sampling unit 230 includes 32 high-speed registers SAFF. The oscillation signal polarity adjustment unit 311 includes 16 buffers and 16 second inverters, the oscillation signal edge detection unit includes 32 XOR gates, the oscillation clock phase detection unit includes 32 AND gates, and the fractional part phase_frac of the accumulated phase output by the phase encoder 314 can be a 6-bit binary code. The default value of the first threshold Safe_Min can be 6`d16, the default value of the second threshold Safe_Max can be 6`d48, and the oscillation period count adjustment constant const1 can be 8`d1. The phase integer adjustment value const2 can be 9`b100000000.

[0105] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0106] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An on-chip voltage measurement circuit, characterized in that: include: Oscillating ring module; The oscillation ring module is used to self-excite and generate a periodic oscillation signal, and to count and output the number of oscillation cycles of the oscillation ring module; A phase sampler; the phase sampler is electrically connected to the oscillation ring module, accesses the oscillation signal and the oscillation cycle number, and the phase sampler accesses a sampling clock signal; the phase sampler is used to sample the oscillation signal and the oscillation cycle number under the control of the sampling clock signal to obtain a sampled oscillation signal and a sampled oscillation cycle number; A phase calculator; the phase calculator is electrically connected to the phase sampler; the phase calculator is used to calculate the accumulated phase of the oscillation ring module according to the sampled oscillation signal and the number of sampled oscillation cycles; A pipeline register; the pipeline register is electrically connected to the phase calculator, and the pipeline register is connected to the sampling clock signal; the pipeline register is used to output the accumulated phase of the oscillation ring module in the previous sampling cycle under the control of the sampling clock signal; A phase subtractor; the phase subtractor is electrically connected to the phase calculator and the pipeline register respectively; the phase subtractor is used to calculate the phase change value of the oscillation ring module in the current sampling period according to the current accumulated phase and the accumulated phase of the oscillation ring module in the previous sampling period; the phase change value is used to characterize the on-chip voltage; The oscillation ring module outputs n oscillation signals; n is a non-zero even number; the oscillation period number includes the rising edge oscillation period number and the falling edge oscillation period number; The phase sampler comprises: A first sampling unit comprises a clock terminal, a data input terminal and an output terminal; the clock terminal of the first sampling unit is connected to the sampling clock signal, and the data input terminal of the first sampling unit is connected to the rising edge oscillation cycle number; the first sampling unit is used to sample the rising edge oscillation cycle number under the control of the sampling clock signal and output a first sampling cycle number; The second sampling unit comprises a clock terminal, a data input terminal and an output terminal; the clock terminal of the second sampling unit is connected to the sampling clock signal, and the data input terminal of the second sampling unit is connected to the falling edge oscillation cycle number; the second sampling unit is used to sample the falling edge oscillation cycle number under the control of the sampling clock signal and output a second sampling cycle number; The third sampling unit comprises a clock end, n data input ends and n output ends; the clock end of the third sampling unit is connected to the sampling clock signal; the n data input ends of the third sampling unit are sequentially connected to the n oscillation signals output by the oscillation ring module; the third sampling unit is used to sample the n oscillation signals under the control of the sampling clock signal and output n sampled oscillation signals.

2. The on-chip voltage measurement circuit according to claim 1, characterized in that: The oscillating ring module comprises: An oscillation ring unit, comprising n oscillation signal output terminals; n is a non-zero even number; the oscillation ring unit is used to self-excite to generate a periodic oscillation signal, and the oscillation signal output terminals output the oscillation signal; An oscillation counter; a clock end of the oscillation counter is electrically connected to the nth oscillation signal output end of the oscillation ring unit, and the oscillation counter is used to count the number of oscillation cycles of the oscillation ring unit.

3. The on-chip voltage measurement circuit according to claim 2, characterized in that: The oscillation ring unit comprises: a first AND gate and n-1 first inverters connected in series; a first input end of the first AND gate is connected to an oscillation enable signal, and a second input end of the first AND gate is electrically connected to an output end of the n-1th first inverter; the oscillation ring unit is used to self-excite and generate a periodic oscillation signal when the oscillation enable signal is valid; the output end of the first AND gate and the output ends of all the first inverters serve as n oscillation signal output ends of the oscillation ring unit; The oscillation counter comprises: A rising edge triggered counter; a clock end of the rising edge triggered counter is electrically connected to the output end of the n-1th first inverter; the rising edge triggered counter is triggered by the rising edge of the output signal of the n-1th first inverter, and is used to count the number of rising edge oscillation cycles of the oscillation ring unit; A falling edge triggered counter; the clock end of the falling edge triggered counter is electrically connected to the output end of the n-1th first inverter; the falling edge triggered counter is triggered by the falling edge of the output signal of the n-1th first inverter, and is used to count the number of falling edge oscillation cycles of the oscillation ring unit.

4. The on-chip voltage measurement circuit according to claim 1, characterized in that: The phase calculator comprises: A fractional part calculator; the fractional part calculator is electrically connected to the third sampling unit; the fractional part calculator is used to calculate the fractional part of the accumulated phase according to n sampled oscillation signals; An integer part calculator; the integer part calculator is electrically connected to the first sampling unit, the second sampling unit and the fractional part calculator respectively; the integer part calculator is used to calculate the integer part of the accumulated phase according to the fractional part of the accumulated phase, the first sampling cycle number and the second sampling cycle number.

5. The on-chip voltage measurement circuit according to claim 4, characterized in that: The decimal part calculator comprises: An oscillation signal polarity adjustment unit, comprising n / 2 buffers and n / 2 second inverters; the input ends of the n / 2 buffers are electrically connected to the odd-numbered output ends of the third sampling unit in a one-to-one correspondence; the output end of the k-th buffer serves as the 2k-1-th output end of the oscillation signal polarity adjustment unit; the input ends of the n / 2 second inverters are electrically connected to the even-numbered output ends of the third sampling unit in a one-to-one correspondence; the output end of the k-th second inverter serves as the 2k-th output end of the oscillation signal polarity adjustment unit; 1≤k≤n / 2; An oscillation signal edge detection unit, comprising n XOR gates; the output ends of the n XOR gates serve as n output ends of the oscillation signal edge detection unit; the first input end of the first XOR gate is electrically connected to the first output end of the oscillation signal polarity adjustment unit, and the second input end of the first XOR gate is electrically connected to the input end of the n / 2 second inverter; the first input end of the j-th XOR gate is electrically connected to the j-1-th output end of the oscillation signal polarity adjustment unit, and the second input end of the j-th XOR gate is electrically connected to the j-th output end of the oscillation signal polarity adjustment unit; 2≤j≤n; An oscillation clock phase detection unit comprises 2n second AND gates; the output ends of the 2n second AND gates serve as the 2n output ends of the oscillation clock phase detection unit; the first input end of the i1th second AND gate is electrically connected to the i1th output end of the oscillation signal edge detection unit, and the second input end of the i1th second AND gate is connected to the inverted signal of the i1+n / 2th output signal of the oscillation signal polarity adjustment unit; 1≤i1≤n / 2; the first input end of the i2th second AND gate is electrically connected to the i2th output end of the oscillation signal edge detection unit, and the second input end of the i2th second AND gate is connected to the i2- n / 2 output terminals are electrically connected; n / 2+1≤i2≤n; the first input terminal of the i3th second AND gate is electrically connected to the i3-nth output terminal of the oscillation signal edge detection unit, and the second input terminal of the i3th second AND gate is electrically connected to the i3-n / 2th output terminal of the oscillation signal polarity adjustment unit; n+1≤i3≤3n / 2; the first input terminal of the i4th second AND gate is electrically connected to the i4-nth output terminal of the oscillation signal edge detection unit, and the second input terminal of the i4th second AND gate is connected to the inverted signal of the i4-3n / 2th output signal of the oscillation signal polarity adjustment unit; 3n / 2+1≤i4≤2n; Phase encoder; the phase encoder is electrically connected to all output ends of the oscillation clock phase detection unit, and is used to encode the output signal of the oscillation clock phase detection unit to obtain the fractional part of the accumulated phase.

6. The on-chip voltage measurement circuit according to claim 4, characterized in that: The integer part calculator comprises: A first comparator; a first input terminal of the first comparator is connected to a first threshold, and a second input terminal of the first comparator is connected to a fractional part of the accumulated phase; A second comparator; a first input terminal of the second comparator is connected to a second threshold, and a second input terminal of the second comparator is connected to a fractional part of the accumulated phase; A first selector; a control end of the first selector is electrically connected to the output end of the second comparator, and a first input end of the first selector is electrically connected to the output end of the second sampling unit; a first subtractor; a first input end of the first subtractor is electrically connected to an output end of the second sampling unit, a second input end of the first subtractor is connected to an oscillation period count adjustment constant, and an output end of the first subtractor is electrically connected to a second input end of the first selector; an OR gate; a first input terminal of the OR gate is electrically connected to the output terminal of the first comparator, and a second input terminal of the OR gate is electrically connected to the output terminal of the second comparator; a second selector; a control end of the second selector is electrically connected to the output end of the OR gate, a first input end of the second selector is electrically connected to the output end of the first sampling unit, a second input end of the second selector is electrically connected to the output end of the first selector, and an output end of the second selector outputs the integer part of the accumulated phase.

7. The on-chip voltage measurement circuit according to claim 1, characterized in that: The accumulated phase of the oscillation ring module includes: an integer part of the accumulated phase and a decimal part of the accumulated phase; The pipeline register comprises: A first register; a clock end of the first register is connected to the sampling clock signal, an input end of the first register is connected to the integer part of the accumulated phase, and an output end of the first register outputs the integer part of the accumulated phase of the oscillation ring module in the previous sampling cycle; The second register; the clock end of the second register is connected to the sampling clock signal, the input end of the second register is connected to the fractional part of the accumulated phase, and the output end of the second register outputs the fractional part of the accumulated phase of the oscillation ring module in the previous sampling cycle.

8. The on-chip voltage measurement circuit according to claim 1, characterized in that: The accumulated phase of the oscillation ring module includes: an integer part of the accumulated phase and a decimal part of the accumulated phase; The phase subtractor comprises: A first adder; a first input terminal of the first adder is connected to the integer part of the current accumulated phase, and a second input terminal of the first adder is connected to the decimal part of the current accumulated phase; A second adder; a first input end of the second adder is connected to the integer part of the accumulated phase of the oscillation ring module in the previous sampling period, and a second input end of the second adder is connected to the decimal part of the accumulated phase of the oscillation ring module in the previous sampling period; A second subtractor; a first input end of the second subtractor is electrically connected to the output end of the first adder, a second input end of the second subtractor is electrically connected to the output end of the second adder, and the output end of the second subtractor outputs the phase change value of the oscillation ring module in the current sampling period.

9. The on-chip voltage measurement circuit according to claim 8, characterized in that: The phase subtractor also includes: A third comparator; a first input terminal of the third comparator is connected to the integer part of the current accumulated phase, and a second input terminal of the third comparator is connected to the integer part of the accumulated phase of the oscillation ring module in the previous sampling period; A third adder; a first input terminal of the third adder is connected to the integer part of the current accumulated phase, and a second input terminal of the third adder is connected to the phase integer adjustment value; A third selector; a first input end of the third selector is connected to the integer part of the current accumulated phase, and a second input end of the third selector is electrically connected to the output end of the third adder; An output terminal of the third selector is electrically connected to a first input terminal of the first adder.

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