Integrated circuit verification method, device, electronic device, and storage medium

Abstract

A verification method, device, electronic device, and storage medium for an integrated circuit. The verification method for the integrated circuit includes: obtaining multiple asynchronous timing device pairs; performing model building processing on the integrated circuit according to the multiple asynchronous timing device pairs to obtain a circuit to be simulated; performing front-end simulation verification on the circuit to be simulated; wherein the model building processing includes: for each asynchronous timing device pair: determining the response time according to the circuit characteristics between the first timing device and the second timing device; constructing a response model according to the response time; adding the response model to the data link determined based on the first timing device and the second timing device in the integrated circuit. The method can accurately inject metastable signals into each asynchronous timing device pair in the asynchronous interface, realize accurate and fast logic simulation with minor changes, and advance the verification of the asynchronous interface to the front-end simulation stage, which greatly reduces the difficulty of locating potential problems and shortens the verification time.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an integrated circuit verification method, an integrated circuit verification device, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] After the design of integrated circuits, especially large-scale integrated circuits, is completed, its functions need to be verified. Due to the system limitations of large-scale integrated circuits, it is often necessary to exchange data between multiple clock frequency systems, receive and send data or process asynchronous signals between different clock frequency systems through input interfaces and output interfaces, etc., that is, there may be multiple clock domains in the integrated circuit, and each clock domain is an area in the integrated circuit controlled by the same clock signal.

[0003] The clock signals corresponding to different clock domains are called asynchronous clocks. For two modules connected in an integrated circuit, for example, each module can be composed of some circuit logic that performs specific functions. If the two modules are driven by different clocks (that is, asynchronous clocks), the clock signals of the two modules are called asynchronous clock signals (AsynchronousInterface); if the two modules are driven by the same clock, the clock signals of the two modules are called synchronous clock signals (SynchronousInterface). Summary of the invention

[0004] At least one embodiment of the present disclosure provides a verification method for an integrated circuit, wherein the integrated circuit includes a plurality of asynchronous clock domains, and the verification method includes: obtaining a plurality of asynchronous sequential device pairs, wherein each asynchronous sequential device pair includes a first sequential device and a second sequential device, the first sequential device and the second sequential device are located in two different clock domains among the plurality of clock domains, and an electrical signal transmission relationship exists between a data output terminal of the first sequential device and a data input terminal of the second sequential device; performing model building processing on the integrated circuit according to the plurality of asynchronous sequential device pairs to obtain a circuit to be simulated; performing front-end simulation verification on the circuit to be simulated; and In the embodiment, the model building process includes: for each asynchronous timing device pair: determining the response time according to the circuit characteristics between the first timing device and the second timing device; building a response model according to the response time, wherein the response model includes an input terminal and an output terminal, and the response model is configured to output a metastable signal within the response time starting from a first moment, and output a steady-state response signal after the response time starting from the first moment, and the first moment is the moment when the input signal received by the input terminal jumps; adding the response model to the data link determined in the integrated circuit based on the first timing device and the second timing device.

[0005] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, in which a response time is determined according to circuit characteristics between the first timing device and the second timing device, including: determining a delay time according to the circuit characteristics; and determining the response time according to the delay time.

[0006] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, in which a delay time is determined according to the circuit characteristics, including: determining a constraint time according to the circuit characteristics, wherein the constraint time indicates that the second timing device collects a steady-state response signal at least at a second moment after the first moment, and the first moment and the second moment differ by the constraint time; determining the delay time according to the constraint time.

[0007] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, wherein the clock domain where the second timing device is located is determined based on a target clock signal, and the constraint time is determined according to the circuit characteristics, including: determining the constraint time to be x clock cycles according to the circuit characteristics, wherein the clock cycle is the clock cycle of the target clock signal, and x is a positive integer.

[0008] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, in which the delay time is determined according to the constraint time, including: determining a decision edge, wherein the decision edge is the first transition edge that appears in the target clock signal after the first moment; taking the decision edge as the first decision edge, counting y decision edges, wherein y is a positive number and is less than or equal to x; and taking the duration between the first moment and the yth decision edge as the delay time.

[0009] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, where y is a random value between 0 and x.

[0010] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, in which a constraint time is determined according to the circuit characteristics, including: determining a maximum delay between the first timing device and the second timing device according to the circuit characteristics, and using the maximum delay as the constraint time.

[0011] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, wherein the delay time is determined according to the constraint time, and the method includes: determining that the delay time is equal to the constraint time.

[0012] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, wherein the response time is determined according to the delay time, including: determining that the response time is less than or equal to the delay time.

[0013] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, wherein the second timing device performs synchronization processing on the signal sent by the first timing device, and the response model also includes a synchronization processing module, the synchronization processing module includes multiple timing devices, and the synchronization processing module is configured to perform synchronization processing on the signal sent by the first timing device, and determine the delay time according to the circuit characteristics, including: determining a constraint time according to the circuit characteristics, wherein the constraint time indicates that a third timing device collects a steady-state response signal at least at a second moment after the first moment, and the first moment differs from the second moment by the constraint time, and the third timing device represents a timing device among the multiple timing devices that is directly connected to the data signal input terminal of the synchronization processing module; and determining the delay time according to the constraint time.

[0014] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, in which the response time is determined according to the delay time, including: determining the processing delay corresponding to the synchronous processing module; and determining the response time according to the processing delay and the delay time.

[0015] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, wherein the response time is determined according to the processing delay and the delay time, including: determining that the response time is less than or equal to the sum of the processing delay and the delay time.

[0016] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, in response to the signal received by the third timing device being a metastable signal, the response time is determined according to the processing delay and the delay time, including: determining that the response time is less than or equal to the sum of the processing delay, the metastable delay and the delay time.

[0017] For example, in at least one embodiment of the present disclosure, there is provided a verification method for an integrated circuit, wherein the model building process further includes: naming the simulation model according to the constraint time, so that the name of the simulation model corresponds to the constraint time.

[0018] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, in which the response model is added to a data link determined in the integrated circuit based on the first timing device and the second timing device, including: inserting the response model between the second timing device and a device directly connected to the second timing device, and the output end of the response model is directly connected to the data input end of the second timing device.

[0019] For example, at least one embodiment of the present disclosure provides a verification method for an integrated circuit, which also includes: obtaining a circuit to be planned that has passed the simulation verification, wherein the circuit to be planned includes the multiple asynchronous timing device pairs; performing planning processing on the circuit to be planned; wherein the planning processing includes: replacing at least one response model corresponding to at least one asynchronous timing device pair among the multiple asynchronous timing device pairs with a corresponding physical device, wherein the naming of the physical device is the same as the naming of the corresponding response model; and obtaining multiple constraint times based on the naming of the physical device.

[0020] For example, in at least one embodiment of the present disclosure, there is provided a verification method for an integrated circuit, wherein the planning process further includes: performing layout and routing optimization on the circuit to be planned according to the multiple constraint times.

[0021] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, wherein the planning process further includes: setting a virtual clock domain; and setting timing constraints for multiple asynchronous timing device pairs in the circuit to be planned according to the multiple constraint times.

[0022] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, wherein the planning process also includes: setting a virtual clock domain, including: determining at least one virtual clock based on the multiple asynchronous timing device pairs and the multiple clock domains; for each virtual clock, setting at least one timing path determined based on the multiple asynchronous timing device pairs to belong to the same virtual clock domain, wherein the same virtual clock domain is determined based on each virtual clock.

[0023] For example, in at least one embodiment of the present disclosure, there is provided a verification method for an integrated circuit, wherein the planning process further comprises: performing timing checks on the plurality of asynchronous sequential device pairs according to timing constraints set for the plurality of asynchronous sequential device pairs.

[0024] For example, in at least one embodiment of the present disclosure, a verification method for an integrated circuit is provided, wherein the metastable signal includes a random signal and an uncertain signal, and when the response model executes to output the metastable signal within the response time starting from the first moment, the following operations are included: obtaining a signal configuration parameter; and according to the signal configuration parameter, outputting one of the random signal or the uncertain signal within the response time starting from the first moment.

[0025] At least one embodiment of the present disclosure provides a verification device for an integrated circuit, wherein the integrated circuit includes a plurality of asynchronous clock domains, and the verification device includes: an acquisition unit, configured to acquire a plurality of asynchronous sequential device pairs, wherein each asynchronous sequential device pair includes a first sequential device and a second sequential device, the first sequential device and the second sequential device are located in two different clock domains among the plurality of clock domains, and an electrical signal transmission relationship exists between a data output terminal of the first sequential device and a data input terminal of the second sequential device; a processing unit, configured to perform model building processing on the integrated circuit according to the plurality of asynchronous sequential device pairs to obtain a circuit to be simulated; and a simulation verification unit, configured to perform model building processing on the circuit to be simulated. The front-end simulation verification is performed on the real circuit; wherein the model building process includes: for each asynchronous timing device pair: determining the response time according to the circuit characteristics between the first timing device and the second timing device; building a response model according to the response time, wherein the response model includes an input end and an output end, and the response model is configured to output a metastable signal within the response time starting from a first moment, and output a steady-state response signal after the response time starting from the first moment, and the first moment is the moment when the input signal received by the input end jumps; adding the response model to the data link determined in the integrated circuit based on the first timing device and the second timing device.

[0026] At least one embodiment of the present disclosure provides an electronic device, comprising: a memory, which non-transitorily stores computer-executable instructions; and a processor, configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the integrated circuit verification method according to any embodiment of the present disclosure.

[0027] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the integrated circuit verification method according to any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0029] Figure 1 is a schematic diagram of an asynchronous interface;

[0030] Figure 2 A schematic flow chart of a verification method of an integrated circuit provided for at least one embodiment of the present disclosure;

[0031] Figure 3 A schematic flow chart of a model building process provided for at least one embodiment of the present disclosure;

[0032] Figure 4 A schematic diagram of delay time provided for at least one embodiment of the present disclosure;

[0033] Figure 5A A schematic diagram of a response model provided by an embodiment of the present disclosure;

[0034] Figure 5B A schematic diagram of an output signal of a response model provided by an embodiment of the present disclosure;

[0035] Figure 5C A schematic diagram of an output signal of a response model provided by another embodiment of the present disclosure;

[0036] Fig. 6A A schematic diagram of a response model provided for another embodiment of the present disclosure;

[0037] Figure 6B A schematic diagram of an output signal of a response model provided by another embodiment of the present disclosure;

[0038] Fig. 7A A schematic block diagram of a verification device for an integrated circuit provided in at least one embodiment of the present disclosure;

[0039] Figure 7B A schematic block diagram of a processing unit provided for at least one embodiment of the present disclosure;

[0040] Figure 7C A schematic block diagram of a planning processing unit provided for at least one embodiment of the present disclosure;

[0041] Figure 8 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0042] Fig. 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0045] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components.

[0046] With the development of semiconductor technology, the process of integrated circuits is becoming more and more advanced, the scale is getting larger, the verification cycle is getting longer and longer, and the difficulty of verification is getting higher and higher. For projects and products using large-scale integrated circuits with advanced processes, verification is becoming an increasingly important consideration for project progress.

[0047] There are often multiple clock domains in large-scale integrated circuits. Signals in different clock domains are interrelated, forming a large number of data links across clock domains. These data links are called asynchronous interfaces because the sender and receiver belong to different clock domains.

[0048] Figure 1 is a schematic diagram of an asynchronous interface. Figure 1 As shown, sequential devices A1 to An are sequential devices driven by the first clock signal Clk_1, wherein point p1 is the clock input terminal of sequential device A1, and point p2 is the data output terminal of sequential device A1; sequential devices B1 to Bn are sequential devices driven by the second clock signal Clk_2, wherein point p3 is the data input terminal of sequential device B1. There may be multiple combinatorial logic devices (Combinatorial Logics) between an asynchronous sequential device pair (any sequential device from sequential devices A1 to An and any sequential device from sequential devices B1 to Bn) to form a data link, the sender of the data link is a sequential device from sequential devices A1 to An, and the receiver of the data link is a sequential device from sequential devices B1 to Bn. For example, the data link can be a timing path.

[0049] For example, more clock domains may be included on an asynchronous interface. For example, the sender may include a timing device driven by a third clock signal Clk_3 and a fourth clock signal Clk_4; the receiver may include a timing device driven by a fifth clock signal Clk_5 and a sixth clock signal Clk_6. For example, an asynchronous timing device pair may include a timing device driven by a third clock signal Clk_3 and a timing device driven by a sixth clock signal Clk_6, etc.

[0050] Because the phase relationship between data and clock is uncertain in asynchronous interfaces, setup time or hold time may not be met, resulting in the receiver seeing a metastable state.

[0051] In addition, due to the uncertainty of the clock relationship between the sender and the receiver, the integrated circuit cannot perform static timing analysis, and thus cannot be covered and verified in the early stage of front-end simulation. Instead, it can only wait until the back-end timing converges, and then reverse the timing information in the sdf (Standard Delay Format) file to the back-end netlist for back-end verification (also known as post-simulation or post-simulation). However, due to the difficulty of setting up the post-simulation verification environment, the large number of corners that need to be covered, the long verification time, and the difficulty in locating errors, this is increasingly becoming a bottleneck for verification.

[0052] If design problems are found in the post-simulation stage, they can only be resolved through engineering changes (Engineering Change Order), which is difficult. In addition, if engineering changes are performed, the layout and wiring may need to be re-laid out, which increases the number of iterations, greatly delaying the project progress and causing the project to lag behind.

[0053] For example, in addition to verification in the post-simulation stage, you can also introduce fully random or fixed-cycle metastable outputs in the pre-simulation stage. However, since the asynchronous interface has no timing constraints and the length of the metastable state is completely decoupled from the actual signal delay, this method cannot reflect the specific characteristics of the asynchronous interface, resulting in overly pessimistic or overly optimistic verification results. In addition, if metastable states are introduced in the front-end simulation, it is easy to cause metastable state propagation in the logic simulation before synthesis, resulting in the failure of the test case to pass, wasting a lot of time to locate the source of the metastable state, and resulting in overly pessimistic verification results.

[0054] At least one embodiment of the present disclosure provides a verification method for an integrated circuit, a verification device for an integrated circuit, an electronic device, and a non-transitory computer-readable storage medium. The verification method for the integrated circuit includes: obtaining a plurality of asynchronous sequential device pairs, wherein each asynchronous sequential device pair includes a first sequential device and a second sequential device, the first sequential device and the second sequential device are located in two different clock domains among a plurality of clock domains, and there is an electrical signal transmission relationship between the data output terminal of the first sequential device and the data input terminal of the second sequential device; performing model building processing on the integrated circuit according to the plurality of asynchronous sequential device pairs to obtain a circuit to be simulated; performing front-end simulation verification on the circuit to be simulated; wherein the model building processing includes: for each asynchronous sequential device pair: determining a response time according to the circuit characteristics between the first sequential device and the second sequential device; constructing a response model according to the response time, wherein the response model includes an input terminal and an output terminal, and the response model is configured to output a metastable signal within a response time starting from a first moment, and output a steady-state response signal after the response time starting from the first moment, and the first moment is the moment when the input signal received by the input terminal jumps; adding the response model to the data link determined based on the first sequential device and the second sequential device in the integrated circuit.

[0055] The verification method of the integrated circuit provided by at least one embodiment of the present disclosure determines the response time according to the circuit characteristics between the asynchronous timing device pairs. This method is closer to the actual situation of the circuit, accurately injects metastable signals into each asynchronous timing device pair in the asynchronous interface, and realizes accurate and fast logic simulation with relatively small changes. The verification of the asynchronous interface is advanced to the front-end simulation stage. The front-end simulation verification is fast and saves the time for setting up the back-end simulation environment, thereby reducing the time cost required for verification. In addition, the general back-end simulation needs to wait for the timing to converge before it can start execution, while the verification method provided by the present disclosure can be executed in the early stage of the project, which greatly reduces the difficulty of locating potential problems, facilitates modification, and greatly shortens the project development time and the number of later iterations, thereby improving the project development efficiency.

[0056] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0057] Figure 2 A schematic flowchart of a verification method for an integrated circuit provided in at least one embodiment of the present disclosure.

[0058] For example, the integrated circuit verification method is applied to the design of the integrated circuit. For example, after the front-end design (logic design) stage of the circuit is completed, the integrated circuit verification method is applied to simulate and verify the asynchronous clock in the circuit design.

[0059] For example, the integrated circuit includes multiple asynchronous clock domains, for example, the multiple asynchronous clock domains include clock domains controlled by multiple asynchronous clock signals. For example, two clock signals may be asynchronous clock signals in which the clock frequencies of the two clock signals are different, for example, the clock frequency of one clock signal is 100 MHz, and the clock frequency of the other clock signal is 120 MHz. For example, two clock signals may be asynchronous clock signals in which the initial phases of the two clock signals are different but the clock frequencies are the same. That is, the multiple asynchronous clock signals in the present disclosure do not have a definite phase relationship with each other.

[0060] For example, refer to Figure 1 The asynchronous interface shown in the figure is specifically described by taking the number of multiple clock domains as 2 as an example. Figure 1As shown, the multiple clock domains may include a first clock domain determined based on the first clock signal Clk_1 and a second clock domain determined based on the second clock signal Clk_2. For example, the first clock domain is a region controlled by the first clock signal Clk_1, and the first clock domain includes a plurality of sequential devices driven by the first clock signal Clk_1, such as sequential devices A1 to An. The second clock domain is a region controlled by the second clock signal Clk_2, and the second clock domain includes a plurality of sequential devices driven by the second clock signal Clk_2, such as sequential devices B1 to Bn.

[0061] In the present disclosure, devices include logic devices, and logic devices include timing devices and combinational logic devices. Timing devices refer to devices such as triggers, registers, latches, etc. in digital circuit design. Timing devices have storage and memory functions for input signals. When receiving the valid edge or valid level of the clock signal, it can trigger the storage of the input signal and the change of the state of the output signal of the timing device. Combinational logic devices refer to devices such as AND gates and OR gates in digital circuit design that implement logical operations. Combinational logic devices do not have storage and memory functions for input signals. At any time, the state of the output signal of the combinational logic device depends on the state of the input signal at the current time.

[0062] For example, Figure 2 As shown, the integrated circuit verification method provided by at least one embodiment of the present disclosure includes steps S10 to S30.

[0063] In step S10, a plurality of asynchronous sequential device pairs are obtained.

[0064] For example, each asynchronous timing device pair includes a first timing device and a second timing device, the first timing device and the second timing device are located in two different clock domains among multiple clock domains, and there is an electrical signal transmission relationship between the data output end of the first timing device and the data input end of the second timing device.

[0065] For example, two different clock domains include a first clock domain and a second clock domain, the first timing device is the "end timing device" in the first clock domain, and the second timing device is the "starting timing device" in the second clock domain, that is, there is an electrical signal transmission relationship between the data output end of the first timing device and any timing device in the second clock domain, and the electrical signal transmission relationship is realized by at least one combinational logic device. At this time, any timing device in the second clock domain is the second timing device.

[0066] For example, Figure 1For example, there is an electrical signal transmission relationship between the timing device A1 and the timing device B1. For example, the data signal output by the timing device A1 is transmitted to the timing device B1 through the combinational logic, and the timing device B1 samples the data signal according to the second clock signal Clk_2. At this time, the timing device A1 and the timing device B1 constitute an asynchronous timing device pair, the first timing device is A1, and the second timing device is B1.

[0067] For example, in some examples, the signal sent by the first timing device is a quasi-static signal. For example, the quasi-static signal indicates that the signal can be regarded as a steady-state signal. For example, the signal is a stable signal for a long period of time before sampling, and the receiver will not sample the change of the signal, or the receiver does not pay attention to the metastable state generated by the signal. For example, the quasi-static signal can be an enable signal, a reset signal at the source, etc. At this time, the second timing device does not need to perform synchronous processing on the signal, and there are no other timing devices in the electrical signal transmission relationship. The data link formed by the first timing device to the second timing device is a timing path.

[0068] For example, in some other examples, the signal sent by the first timing device is not a quasi-static signal. In this case, the second timing device needs to perform synchronization processing on the signal. For example, the synchronization processing can be implemented by a synchronization processing module, for example, the synchronization processing module includes multiple cascaded timing devices. Then, there are also multiple timing devices for synchronization processing in the electrical signal transmission relationship, and the data link formed from the first timing device to the second timing device includes multiple timing paths. For example, the first timing device and the first-level timing device in the synchronization processing module form a timing path, and the first-level timing device here is the first timing device among the multiple cascaded timing devices to receive the signal sent by the first timing device.

[0069] In step S20, a model building process is performed on the integrated circuit according to the plurality of asynchronous sequential device pairs to obtain a circuit to be simulated.

[0070] Figure 3 A schematic flowchart of a model building process provided for at least one embodiment of the present disclosure.

[0071] For example, Figure 3 As shown, the model building process provided by at least one embodiment of the present disclosure includes steps S201 to S203.

[0072] For example, steps S201 - S203 are respectively performed for each asynchronous sequential device pair.

[0073] In step S201, a response time is determined according to circuit characteristics between a first sequential device and a second sequential device.

[0074] For example, the circuit characteristics between the first sequential device and the second sequential device may include the sequential logic requirements of the second sequential device. For example, the constraint value to be applied to the data link between the first sequential device and the second sequential device may be determined according to the sequential logic requirements of the second sequential device. The specific process is described below.

[0075] In step S202, a response model is constructed according to the response time.

[0076] For example, the response model includes an input end and an output end. The response model is configured to output a metastable signal within a response time starting from a first moment, and to output a steady-state response signal after the response time starting from the first moment. The first moment is the moment when the input signal received by the input end changes.

[0077] For example, after obtaining the response model corresponding to each asynchronous sequential device pair, step S203 is performed to insert the response model into the integrated circuit.

[0078] In step S203, a response model is added to a data link determined based on the first sequential device and the second sequential device in the integrated circuit.

[0079] For example, step S203 may include: inserting the response model between the second sequential device and a device directly connected to the second sequential device, and the output end of the response model is directly connected to the data input end of the second sequential device.

[0080] For example, the device directly connected to the second sequential device in the original design of the integrated circuit is referred to as a source device in the following text. For example, the source device can be a combinational logic device or a first sequential device.

[0081] For example, a signal output by a source device is called a source signal, and the moment when the source signal changes is called the first moment.

[0082] For example, step S201 may include: determining a delay time according to circuit characteristics; and determining a response time according to the delay time.

[0083] For example, determining the delay time according to circuit characteristics may include: determining a constraint time according to the circuit characteristics; and determining the delay time according to the constraint time.

[0084] For example, according to the circuit characteristics between the first timing device and the second timing device, it can also be determined whether the second timing device needs to perform synchronization processing on the signal sent by the first timing device. For example, it can be determined whether the signal sent by the first timing device needs to be synchronized based on whether the signal sent by the first timing device is a quasi-static signal. Depending on whether the second timing device needs to perform synchronization processing on the signal sent by the first timing device, the processing methods of steps S201-S203 are slightly different. The processing process of steps S201-S203 is specifically described below for two situations.

[0085] For example, when the signal sent by the first sequential device is a quasi-static signal, the second sequential device does not need to perform synchronous processing on the signal. For example, the signal may be a single-bit signal or a bus signal including multiple bits, such as an enable signal, a reset signal, an address bus signal, etc. At this time, the constraint time indicates that the second sequential device collects a steady-state response signal at least at a second moment after the first moment, and the first moment and the second moment differ by the constraint time.

[0086] For example, the constraint time refers to the constraint value that the designer wants to impose on the data link between the first sequential device and the second sequential device. For example, when the data link is a timing path, this constraint value can be used as a timing constraint for the timing path in the back-end design process.

[0087] Since the constraint time is determined according to the circuit characteristics, it is closer to the actual situation of the asynchronous interface, accurately injecting metastable states into the asynchronous interface, reducing some unnecessary simulation scenarios, thereby helping the simulation model reduce the scenarios that need to be simulated, improving accuracy while reducing the workload of verification.

[0088] For example, the constraint time can be set from two perspectives: multi-cycle constraint or maximum delay constraint.

[0089] For example, when the constraint time is reflected as a multi-cycle constraint in the back end, the constraint time means that the designer expects the source signal to change and the output signal of the response model (that is, the data signal received by the second timing device) to respond, and the maximum delay between the two actions is x clock cycles of the receiver.

[0090] For example, the clock domain where the second timing device is located is determined based on the target clock signal, for example, the target clock signal here can be the second clock signal as described above. Determining the constraint time according to the circuit characteristics may include: determining the constraint time as x clock cycles according to the circuit characteristics, where the clock cycle is the clock cycle of the target clock signal, and x is a positive integer.

[0091] For example, when the constraint time is x clock cycles, the timing constraint imposed by the back-end design process is called a multi-cycle constraint, which means that the data is allowed to stabilize after x cycles, so that the wiring resources are released during the wiring process, and the wiring operation time is also reduced. Usually for designers, they usually consider the problem from the perspective of how many clock cycles the input signal needs to be used after. For example, the second timing device needs to collect a steady-state signal after 5 clock cycles, then the constraint time can be set to 4 clock cycles, so that the steady-state signal can be collected at the 5th clock cycle. This setting method is highly portable, and the constraint time is independent of the circuit process and clock signal frequency.

[0092] For example, based on the constraint time, it can be determined that the constraint value to be imposed on the design is x clock cycles.

[0093] For example, determining the delay time based on the constraint time may include: determining a decision edge, wherein the decision edge is the first transition edge that appears in the target clock signal after the first moment; taking the decision edge as the first decision edge, counting y decision edges, wherein y is a positive number and is less than or equal to x; and taking the duration between the first moment and the yth decision edge as the delay time.

[0094] Figure 4 A schematic diagram of delay time provided for at least one embodiment of the present disclosure.

[0095] like Figure 4 As shown, the first clock signal represents a clock signal driving a first sequential device, and the second clock signal represents a clock signal driving a second sequential device. Figure 4 It can be seen that the frequencies of the two clock signals are different, that is, the two clock signals are asynchronous clock signals.

[0096] like Figure 4 As shown, the source signal is a signal output by the source device, and the moment when the source signal jumps is the first moment.

[0097] For example, the constraint time is determined to be three clock cycles of the target clock signal (ie, the second clock signal) according to circuit characteristics.

[0098] like Figure 4 As shown in FIG. 1 , since the first transition edge in the second clock signal after the first moment is a falling edge, the determination edge is a falling edge. Taking the falling edge as the first determination edge, three falling edges are counted, that is, Figure 4 The labels in the figure are ①, ② and ③ falling edges.

[0099] like Figure 4 As shown, the time from the first moment to the falling edge marked as ③ is the delay time.

[0100] For example, in Figure 4In the case shown, y=x=3.

[0101] For example, in some embodiments, y may be less than x, eg, y=2, etc.

[0102] For example, in some embodiments, y may be a fixed value.

[0103] For example, in some embodiments, y may be a random value between 0 and x. At this time, each time a change in the source signal is detected, y may select a different random value, thereby obtaining a randomly changing delay time, so as to cover more simulation situations, obtain rich signal relationships, increase the diversity of scenarios, and more easily find boundary conditions, and the obtained simulation results are more accurate and reliable.

[0104] In the back-end design process, the timing constraint judgment starts from the source signal jump, and x clock cycles are recorded as the delay. However, in the front-end simulation process, if the trigger edge of the second clock device is used as the start, x clock cycles are counted, and Figure 4 For example, if the trigger edge is a rising edge, the delay time obtained in this way is greater than the delay recorded in the back-end design process. The constraint time used in the front-end simulation does not correspond to the timing constraint imposed by the back-end, resulting in some simulation scenarios being useless simulations, wasting some computing power and simulation resources.

[0105] For example, when the constraint time is reflected as a maximum delay constraint, the constraint time means that the designer expects the maximum delay between the source signal changing and the output signal of the response model (that is, the data signal received by the second timing device) to respond is p picoseconds.

[0106] It should be noted that the unit of the maximum delay in the present disclosure is described using picoseconds as an example. In practice, different time units may be selected as needed, such as nanoseconds, milliseconds, etc., and the present disclosure does not impose any limitation on this.

[0107] For example, for enable signals of some circuit modules in the circuit, reset signals at the source, and other signals similar to quasi-static signals, these signals have a large load, but the signals are completely stable when they are needed. For these signals, the maximum delay value can be set as needed.

[0108] For example, determining the constraint time according to the circuit characteristics may include: determining a maximum delay between the first sequential device and the second sequential device according to the circuit characteristics, and using the maximum delay as the constraint time.

[0109] For example, determining the delay time according to the constraint time may include: determining that the delay time is equal to the constraint time.

[0110] For example, after the delay time is obtained by the two methods described above, determining the response time according to the delay time may include: determining that the response time is less than or equal to the delay time.

[0111] For example, the constraint time specifies the worst case of the data link, that is, the longest delay required for the input signal to stabilize. The actual delay in the back-end physical implementation may be less than the constraint time. When simulating a circuit, it is usually necessary to verify whether the circuit can still work properly in the worst case. If the circuit can still work properly in the worst case, it means that the circuit is robust enough, so the response time of the response model can be selected as the delay time.

[0112] Of course, in practice, you can also choose a response time less than or equal to the delay time, or a response time of a random value between 0 and the delay time, etc., to cover more verification scenarios, obtain rich signal relationships, and obtain more accurate and reliable simulation results with less resource consumption and computing power consumption.

[0113] For example, in some embodiments, the model building process may further include: naming the simulation model according to the constraint time, so that the name of the simulation model corresponds to the constraint time.

[0114] For example, the response model can be made into a general module, and the constraint time desired by the designer can be obtained according to different names during the instantiation process, so as to obtain the response time by referring to the process of step S201. For example, the response time represents the time required from the change of the signal input at the input end of the response model to the response of the output signal of the response model. Within the response time, the output signal of the response model is a metastable signal, thereby constructing the response model.

[0115] For example, the response model is named Cx, which means that the constraint time of the expected response model is x clock cycles of the target clock signal, that is, the designer hopes to generate a timing constraint of x cycles in the back-end design process.

[0116] For example, the response model is named Dp, which means that the expected constraint time of the response model is p picoseconds, that is, the designer hopes to generate a timing constraint of p picoseconds in the back-end design process.

[0117] This method can synthesize the response model into a physical device with the name during the back-end design process. For example, the physical device can be a buffer. The back-end design process can obtain the timing constraints desired by the front-end designer through the name of the physical device, thereby automatically generating an sdc (Synopsys design constraints) file as a reference for wiring optimization and adding timing constraints to asynchronous interfaces. Therefore, the back-end automatically generates relevant constraints by obtaining the module name keyword, without the need for additional front-end provision, which not only reduces the workload of the front-end, but also conveys the design intent well. The understanding and constraints of the asynchronous interface in the front-end and back-end design processes are consistent, and a circuit that is more in line with the actual situation is obtained, which not only reduces the simulation workload and avoids invalid simulation, but also verifies the circuit efficiently as much as possible under limited computing power and time.

[0118] For example, the response model outputs a metastable signal within the response time after the first moment, and then outputs a steady-state signal, which is the response of the response model to the source signal. In other words, the response time indicates the time when the response model outputs the metastable state.

[0119] During logic simulation, uncertain states may spread due to the relationship between simulation tools, causing many subsequent signals to become uncertain states, which in turn leads to test case failures. At various stages or levels of circuit verification, the spread of uncertain states may cause a large number of test cases to fail or unexpected problems to occur, requiring a lot of time to locate the source of the uncertain state. In order to avoid this overly pessimistic scenario, the response model is set with signal configuration parameters, according to which the type of metastable signal output by the response model can be freely adjusted.

[0120] For example, metastable signals include random signals and uncertain signals (also called X-state signals). When the response model executes to output a metastable signal within a response time starting from a first moment, the response model includes performing the following operations: obtaining a signal configuration parameter; and outputting one of the random signal or the uncertain signal within a response time starting from the first moment according to the signal configuration parameter.

[0121] Generally speaking, the uncertain state signal corresponds to the worst case of the simulation, and can be used to determine whether the circuit can work normally under the worst simulation condition. Random signals include random 0 or 1, that is, the result obtained each time the same signal is sampled is not fixed. Therefore, the designer can freely select the form of the metastable signal according to the required simulation scenario and the signal configuration parameters. The verification method provided by the present disclosure can support a variety of simulation scenarios and is more in line with the actual circuit state.

[0122] For example, the constraint time can also be recorded through a configuration file and provided to the backend during the backend design process.

[0123] For example, the response model may be implemented using a behavioral level description language, such as a hardware programming language.

[0124] Figure 5A A schematic diagram of a response model provided in accordance with an embodiment of the present disclosure.

[0125] For example, the constraint time is obtained according to the name of the response model, and then the response time is obtained according to step S201. For example, the type of the metastable signal output by the response model is determined according to the signal configuration parameters of the response model, thereby constructing the response model.

[0126] like Figure 5A As shown, the response model constructed according to step S201 and step S202 is inserted between the source device and the second sequential device. The input end of the response model is connected to the data signal output end of the source device, and the output end of the response model is connected to the data signal input end of the second sequential device.

[0127] For example, Figure 5A The source devices shown are combinational logic devices.

[0128] Figure 5B A schematic diagram of an output signal of a response model provided by an embodiment of the present disclosure.

[0129] For example, if the name of the response model instantiation is "C3", it means that the constraint time is 3 clock cycles of the second clock signal. Figure 5B The description of the first clock signal, the second clock signal, and the source signal can refer to Figure 4 The relevant contents shown will not be repeated here.

[0130] For example, Figure 5B As shown, the output signal represents the output signal change of the response model, and the shaded part in the output signal represents that the output signal is in a metastable state, for example, it can be an uncertain state or a random signal.

[0131] For example, Figure 5B As shown, the response time is equal to the delay time. The output signal of the response model is in a stable low-level state before the first moment. After the source signal received at the input end of the response model jumps (that is, the first moment), the output signal becomes a metastable signal and lasts for the response time; afterwards, the output signal generates a rising edge, that is, the response corresponding to the output source signal of the response model; and then stabilizes to a high-level state.

[0132] Figure 5C A schematic diagram of an output signal of a response model provided by another embodiment of the present disclosure.

[0133] For example, if the name of the response model instantiation is "Dp", it means that the constraint time is p picoseconds. For example, the constraint time, delay time, and response time are equal to each other, so that Figure 5C As shown, the response time is picoseconds.

[0134] like Figure 5C As shown, the output signal of the response model is in a stable low-level state before the first moment. After the source signal received at the input end of the response model jumps (that is, the first moment), the output signal becomes a metastable signal and lasts for the response time; thereafter, the output signal of the response model generates a rising edge, that is, the response corresponding to the output source signal of the response model; and then stabilizes to a high-level state.

[0135] For example, the response model provided by at least one embodiment of the present disclosure sets a more accurate response time according to the actual situation of the circuit, and introduces metastable states of different durations that are consistent with the actual situation of the circuit, thereby more accurately reflecting the uncertainty of the asynchronous interface in the front-end logic simulation stage.

[0136] For example, when the signal sent by the first sequential device is not a quasi-static signal, the second sequential device needs to perform synchronization processing on the signal to ensure that the signals received by multiple receivers are unified.

[0137] For example, in some embodiments, the response model further includes a synchronization processing module, the synchronization processing module includes a plurality of sequential devices, and the synchronization processing module is configured to perform synchronization processing on the signal sent by the first sequential device. For example, the synchronization processing module can be a multi-stage cascade trigger.

[0138] For example, the response model can be configured to include a synchronization processing module according to a mode parameter. For example, when the mode parameter is a first value, the response model obtained includes the synchronization processing module, and when the mode parameter is a second value, the response model obtained does not include the synchronization processing module. In this way, response modules with different functions can be obtained conveniently and flexibly.

[0139] For example, determining the delay time according to the circuit characteristics may include: determining the constraint time according to the circuit characteristics, wherein the constraint time indicates that the third timing device collects the steady-state response signal at least at a second moment after the first moment, and the first moment differs from the second moment by the constraint time, and the third timing device indicates a timing device among multiple timing devices that is directly connected to the data signal input terminal of the synchronous processing module; determining the delay time according to the constraint time.

[0140] For example, the third sequential device here is the "first-order sequential device" in the aforementioned synchronous processing module. This constraint value can be used as a timing constraint for the timing path formed by the first sequential device and the first-order sequential device in the aforementioned synchronous processing unit during the back-end design process.

[0141] When the second sequential device needs to synchronously process the signal sent by the first sequential device, the constraint time refers to the constraint value that the designer wants to apply to the timing path between the first sequential device and the third sequential device. For example, this constraint value can be used as a timing constraint for the timing path in the back-end design process.

[0142] For example, the constraint time can also be set from two perspectives: multi-cycle constraint or maximum delay constraint. The specific constraint time setting method is the same as the above process when synchronization processing is not required, and will not be repeated here.

[0143] After the constraint time is obtained, the delay time is obtained according to the constraint time. The specific process and the corresponding technical effect are the same as the above process when synchronization processing is not required, and will not be repeated here.

[0144] When synchronization processing is required, the path delay from the source device to the second sequential device also includes the delay introduced by the synchronization processing process. For example, the introduced delay at least includes the processing delay corresponding to the synchronization processing module.

[0145] For example, determining the response time according to the delay time may include: determining the processing delay corresponding to the synchronization processing module; and determining the response time according to the processing delay and the delay time.

[0146] For example, determining the response time according to the processing delay and the delay time may include: determining that the response time is less than or equal to the sum of the processing delay and the delay time.

[0147] For example, the delay specified by the constraint time or the delay time is the delay of the source signal being transmitted from the output terminal of the source device to the third sequential device.

[0148] For example, since the phase relationship between the clock signal driving the first timing device and the clock signal driving the third timing device is uncertain, the output of the first timing device may be metastable for the third timing device. At this time, the delay introduced by the synchronization processing process includes metastable delay in addition to the processing delay of the synchronization processing module itself.

[0149] For example, determining the response time according to the processing delay and the delay time may include: determining that the response time is less than or equal to the sum of the processing delay, the metastable delay and the delay time.

[0150] For example, the metastable delay is usually one clock period of the target clock signal.

[0151] Fig. 6A A schematic diagram of a response model provided in accordance with an embodiment of the present disclosure.

[0152] For example, the constraint time is obtained according to the name of the response model, and then the response time is obtained according to step S201. For example, the type of the metastable signal output by the response model is determined according to the signal configuration parameters of the response model.

[0153] like Fig. 6A As shown, when the second sequential device needs to be synchronized, the response model constructed according to step S201 and step S202 is inserted between the source device and the second sequential device. The input end of the response model is connected to the data signal output end Q of the source device, and the output end of the response model is connected to the data signal input end D of the second sequential device.

[0154] For example, the response model includes a synchronous processing module, which includes three cascade triggers, and the three cascade triggers include: Fig. 6A The trigger reg1, trigger reg2 and trigger reg3 are shown. The trigger reg1 is a third sequential device, and the data input terminal D1 of the trigger reg1 receives the source signal received by the input terminal of the response model; the data output terminal Q1 of the trigger reg1 is directly connected to the data input terminal D2 of the trigger reg2, the data output terminal Q2 of the trigger reg2 is directly connected to the data input terminal D3 of the trigger reg3, and the data output terminal Q3 of the trigger reg3 is connected to the output terminal of the response model.

[0155] For example, the source signal output by the source device driven by the first clock signal is received by the trigger reg1. Since the phase relationship between the first clock signal and the second clock signal is uncertain, the output of the trigger reg1 may be metastable. However, after the subsequent two-stage cascade of triggers reg2 and reg3, the signal output by the data output terminal Q3 is likely to be stable.

[0156] Since the data input terminal of the trigger in the timing constraint is the end point of the timing path, the delay specified by the constraint time, that is, the delay time, only represents the delay from the output terminal of the source device to the data input terminal D1 of the trigger reg1.

[0157] For example, Fig. 6A The source device shown is a first sequential device.

[0158] From the simulation point of view, the delay of the entire response model is composed of the delay time, the delay of the synchronous processing module and the possible metastable delay.

[0159] Figure 6B Schematic diagram of the output signal of the response model provided in one embodiment of the present disclosure. The response model is Fig. 6A The response model in .

[0160] like Figure 6BAs shown, for example, assuming that the name of the response model instantiation is "C3", it means that the constraint time is 3 clock cycles of the second clock signal, that is, the delay of the source signal from the data output terminal of the source device to the data input terminal D1 of the trigger reg1 is 3 clock cycles of the second clock signal.

[0161] The processing delay generated by the synchronization processing module is three clock cycles of the second clock signal. If the signal output by the first timing device and received by the third timing device is a metastable signal, the metastable delay generated is one clock cycle of the second clock signal.

[0162] Taking into account the randomness of the metastable state, the delay of one clock cycle caused by the metastable state appears randomly. Therefore, the delay from the data output end of the source device to the data input end of the second timing device is 6 (the sum of the delay time and the processing delay) or 7 (the sum of the delay time, the processing delay and the metastable state delay) clock cycles of the second clock signal.

[0163] refer to Fig. 6A and 6B The first clock signal represents a clock signal driving a source device, the second clock signal represents a clock signal driving a second timing device, the source signal is a signal output by the source device, and the moment when the source signal jumps is the first moment.

[0164] The method for determining the falling edges numbered ①, ② and ③ in the second clock signal and the delay time can be referred to Figure 4 The relevant content will not be repeated here.

[0165] Afterwards, since the triggers in the synchronous processing module are all driven by rising edges, we start from the falling edge ③ and count 3 rising edges ( Figure 6B The rising edges numbered ④, ⑤ and ⑥ are processed with delay.

[0166] If the signal output by the trigger reg1 is in a metastable state, a metastable delay of one clock cycle needs to be added, such as Figure 6B The rising edge marked with ⑦.

[0167] Therefore, if Figure 6B As shown, the response time is equal to the sum of the aforementioned delay time, processing delay and metastable delay. It should be noted that the metastable delay should actually occur before the rising edge ④, that is, if the signal collected by the trigger reg1 is metastable when the rising edge ④ arrives, the metastable delay will occur. Figure 6B For the convenience of description, it is displayed after the processing delay.

[0168] For example, Figure 6BAs shown, the output signal of the response model is in a stable low-level state before the first moment. After the source signal received at the input end of the response model jumps (that is, the first moment), the output signal of the response model becomes a metastable signal and lasts for the response time; thereafter, the output signal of the response model generates a rising edge, that is, the response corresponding to the output source signal of the response model; and then stabilizes to a high-level state.

[0169] In summary, when building a response module, for example, a common module is created and a plurality of external interfaces are set for the common module for configuration.

[0170] For example, in a situation where synchronization processing needs to be performed, a response model including a synchronization processing module is obtained by configuring mode parameters; the metastable signal type of the response model is selected by configuring signal configuration parameters; the response time of the response model is obtained by setting the name of the response model; the output end of the constructed response model is connected to the input end of the second timing device, and the input end of the response model is connected to the data output end of the source device to complete the processing of a data link.

[0171] For situations where synchronization processing is not required, a response model without a synchronization processing module is obtained by configuring mode parameters; the metastable signal type of the response model is selected by configuring signal configuration parameters; the response time of the response model is obtained by setting the name of the response model; the output end of the constructed response model is connected to the input end of the second timing device, and the input end of the response model is connected to the data output end of the source device to complete the processing of a data link.

[0172] Therefore, the response model can be constructed according to the actual situation of the circuit, and the obtained response model is closer to the actual state of the circuit. In addition, a variety of external interfaces are provided for flexible configuration of the response model, which is highly portable and more flexible to use, and can easily obtain richer simulation scenarios.

[0173] In step S30, front-end simulation verification is performed on the circuit to be simulated.

[0174] The circuit to be simulated obtained in step S20 is subjected to logic simulation to confirm whether the circuit can work normally in various simulation scenarios, and the RTL file (Register Transfer Level, register transfer level description file) is modified and iterated according to the simulation results.

[0175] Therefore, the verification method of the integrated circuit provided by at least one embodiment of the present disclosure can achieve front-end simulation verification of the asynchronous interface with relatively small changes. The simulation scenario is closer to the actual situation of the circuit. The obtained simulation results are neither pessimistic nor optimistic, and can accurately reflect the specific delay of the asynchronous interface, thereby achieving relatively accurate and fast front-end simulation verification of the asynchronous interface. The important features of the asynchronous interface can be reflected in the front-end simulation stage, so that the asynchronous interface can be verified early in the project, which greatly shortens the project development time and the number of iterations and reduces the difficulty of verification.

[0176] The front-end netlist obtained by the above front-end simulation verification is used as the circuit to be planned, and the back-end design process is continued.

[0177] For example, the verification method of an integrated circuit provided by at least one embodiment of the present disclosure also includes: obtaining a circuit to be planned that has passed simulation verification, wherein the circuit to be planned includes multiple asynchronous timing device pairs; performing planning processing on the circuit to be planned; wherein the planning processing includes: replacing at least one response model corresponding to at least one asynchronous timing device pair among the multiple asynchronous timing device pairs with a corresponding physical device, wherein the naming of the physical device is the same as the naming of the corresponding response model; and obtaining multiple constraint times based on the naming of the physical device.

[0178] For example, in some embodiments, data links between some asynchronous sequential device pairs cannot be inserted into physical devices that respond to model replacement, and these data links do not perform subsequent optimization processing for asynchronous interfaces.

[0179] For example, in order to flexibly inject metastability through response models, the response models can be described in behavioral language. Since behavioral language description is a non-synthesizable language, these response models need to be replaced with synthesizable circuit descriptions during the synthesis stage.

[0180] For example, in the synthesis stage, the response model inserted in the data link composed of each asynchronous sequential device pair can be replaced with the corresponding physical device. For example, the name of the physical device is the same as the name of the response model.

[0181] For example, if the response model does not need to perform synchronous processing, the physical device corresponding to the response model is a buffer, and the timing constraints desired by the front-end designer are provided to the back-end designer through the naming of the buffer. For example, if the simulation model is named "Cx", it means that the constraint time corresponding to the asynchronous timing device corresponding to the simulation model is x clock cycles of the target clock signal.

[0182] For example, if the response model needs to perform synchronous processing, the physical device corresponding to the response model is a combination of a buffer and a synchronous processing circuit unit. The physically implemented response model can not only provide the timing constraints desired by the front-end designer to the back-end designer through the naming of the buffer, but also complete the synchronous processing function. For example, if the simulation model is named "Dy", it means that the constraint time corresponding to the asynchronous timing device pair corresponding to the simulation model is y picoseconds.

[0183] Here, the constraint time is defined the same as the constraint time in the aforementioned front-end simulation process, and will not be repeated here.

[0184] For example, after obtaining the constraint time expected by the front end, layout and routing optimization, timing constraints, timing checks, etc. can be performed based on this constraint time.

[0185] For example, based on the naming of the physical device, a timing constraint file, namely, an sdc file, can be generated to serve as a position reference for device layout, etc.

[0186] For example, when the constraint time is x clock cycles of the target clock signal, the timing constraint set for the asynchronous sequential device pair in the backend design is a multi-cycle constraint. For example, the multi-cycle constraint can be expressed by the set_multicycle_path command.

[0187] For example, when the constraint time is y picoseconds, the timing constraint set for the asynchronous sequential device pair in the backend design is a maximum delay constraint. For example, the maximum delay constraint can be represented by a set_max_delay command.

[0188] For example, the multi-cycle constraint or maximum delay constraint here is for a timing path formed from the first sequential device to the second sequential device, or for a timing path formed from the first sequential device and a third sequential device in the synchronous processing module.

[0189] For example, the integrated circuit verification method provided by at least one embodiment of the present disclosure further includes: optimizing the layout and routing of the circuit to be planned according to multiple constraint times.

[0190] For example, if the constraint time corresponding to the first sequential device and the second sequential device is shorter, the two sequential devices need to be placed closer to each other to meet the timing constraints desired by the front end. Therefore, the constraint time can be provided to the back end as a wiring delay reference, so that the understanding and constraints of the asynchronous interface in the front end and back end design process are consistent, and the physical implementation of the circuit that meets the front end design requirements is obtained.

[0191] For example, the planning process provided by at least one embodiment of the present disclosure may further include: setting a virtual clock domain; and setting timing constraints for multiple asynchronous sequential device pairs in the circuit to be planned according to multiple constraint times.

[0192] For example, setting a virtual clock domain may include: determining at least one virtual clock based on multiple asynchronous timing device pairs and multiple clock domains; for each virtual clock, setting at least one timing path determined based on multiple asynchronous timing device pairs to belong to the same virtual clock domain, wherein the same virtual clock domain is determined based on each virtual clock.

[0193] For example, if the asynchronous interface of the integrated circuit includes a smaller number of clock domains, such as 2 clock domains, the virtual clock domain is usually the clock domain of the receiver, such as the clock domain where the second sequential device is located.

[0194] For example, if the asynchronous interface of an integrated circuit includes a large number of clock domains, since the layout and routing adjustment is an overall adjustment, if routing optimization is performed once for every two clock domains, each optimization iteration may have a significant impact on each other, the number of iterations may be large, and it may be difficult to find the optimal routing result.

[0195] For example, a clock signal with the highest clock frequency or the largest number of receiving sequential devices driven on an asynchronous interface may be selected from multiple clock domains as a virtual clock domain.

[0196] For each virtual clock domain, assuming that all devices on the asynchronous interface belong to the virtual clock domain, multiple asynchronous sequential device pairs can be subjected to timing checks according to the timing constraints set for the multiple asynchronous sequential device pairs. Such timing checks can refer to the timing checks for synchronous circuits, which will not be described in detail here.

[0197] For example, the verification method provided by at least one embodiment of the present disclosure introduces a virtual clock to implement timing constraints on asynchronous interfaces, and limits the delay of input signals within a specified range based on the constraints during the back-end design process. In addition to providing a reference for layout and routing, it can also perform timing checks similar to synchronous paths by assuming that the entire timing path belongs to the same virtual clock domain.

[0198] For example, in a specific example, the back-end design process first performs initial layout and routing processing on the planned circuit to obtain an initial layout planning result. This process executes corresponding constraints according to an automatic layout and routing algorithm.

[0199] Afterwards, a timing check is performed on the initial layout planning results to identify multiple timing paths on the asynchronous interface that do not meet the timing constraints.

[0200] Afterwards, according to the specific conditions of the multiple timing paths, part or all of the response models are physically implemented as corresponding physical devices, and an sdc file is generated according to the naming of the physical devices.

[0201] Afterwards, perform layout and routing optimization iterations according to the sdc file, set the virtual clock domain, add corresponding timing constraints to the multiple timing paths that need to adjust the timing, perform timing checks, etc., and finally obtain a layout planning result that meets the conditions.

[0202] At least one embodiment of the present disclosure provides an integrated circuit verification method, which introduces a response model to obtain an asynchronous interface verification method that can run through the front-end design process and the back-end design process. The module conveys the designer's expected constraint time through module naming, and performs certain timing constraints on the asynchronous interface, performs timing checks, and performs layout and routing according to the constraint time during the back-end design process according to the constraint time required by the front-end. The resulting circuit can better reflect the front-end design intent.

[0203] Corresponding to the above-mentioned integrated circuit verification method, at least one embodiment of the present disclosure further provides an integrated circuit verification device. Fig. 7A A schematic block diagram of a verification device for an integrated circuit provided in at least one embodiment of the present disclosure.

[0204] For example, Fig. 7A As shown, the integrated circuit verification device 700 at least includes: an acquisition unit 701 , a processing unit 702 and a simulation verification unit 703 .

[0205] The acquisition unit 701 is configured to acquire multiple asynchronous timing device pairs, wherein each asynchronous timing device pair includes a first timing device and a second timing device, the first timing device and the second timing device are located in two different clock domains among multiple clock domains, and there is an electrical signal transmission relationship between the data output end of the first timing device and the data input end of the second timing device.

[0206] The processing unit 702 is configured to perform model building processing on the integrated circuit according to the plurality of asynchronous sequential device pairs to obtain a circuit to be simulated.

[0207] The simulation verification unit 703 is configured to perform front-end simulation verification on the circuit to be simulated.

[0208] Figure 7B A schematic block diagram of a processing unit provided for at least one embodiment of the present disclosure.

[0209] For example, Figure 7B As shown, the processing unit 702 includes: a determining subunit 7021, a constructing subunit 7022, an adding subunit 7023 and a naming subunit 7024.

[0210] The determining subunit 7021 is configured to determine the response time according to the circuit characteristics between the first sequential device and the second sequential device.

[0211] The construction subunit 7022 is configured to construct a response model according to the response time, wherein the response model includes an input terminal and an output terminal, and the response model is configured to output a metastable signal within the response time starting from a first moment, and output a steady-state response signal after the response time starting from the first moment, and the first moment is the moment when the input signal received by the input terminal jumps.

[0212] The adding subunit 7023 is configured to add the response model into the data link determined based on the first sequential device and the second sequential device in the integrated circuit.

[0213] For example, when the determination subunit 7021 determines the response time according to the circuit characteristics between the first sequential device and the second sequential device, the following operations are performed: determining the delay time according to the circuit characteristics; and determining the response time according to the delay time.

[0214] When the determination subunit 7021 determines the delay time according to the circuit characteristics, it includes performing the following operations: determining the constraint time according to the circuit characteristics, wherein the constraint time indicates that the second timing device collects a steady-state response signal at least at a second moment after the first moment, and the first moment and the second moment differ by the constraint time; determining the delay time according to the constraint time.

[0215] For example, the clock domain where the second timing device is located is determined based on the target clock signal, and the determination subunit 7021 determines the constraint time according to the circuit characteristics, including the following operations: according to the circuit characteristics, the constraint time is determined to be x clock cycles, where the clock cycle is the clock cycle of the target clock signal, and x is a positive integer.

[0216] For example, determining that subunit 7021 executes the delay time based on the constraint time includes performing the following operations: determining a decision edge, wherein the decision edge is the first transition edge that appears in the target clock signal after the first moment; taking the decision edge as the first decision edge, counting y decision edges, wherein y is a positive number and is less than or equal to x; and taking the duration between the first moment and the yth decision edge as the delay time.

[0217] For example, the determination subunit 7021 determines the constraint time according to the circuit characteristics, including performing the following operations: determining the maximum delay between the first sequential device and the second sequential device according to the circuit characteristics, and using the maximum delay as the constraint time.

[0218] For example, the determination subunit 7021 determines the delay time according to the constraint time, including performing the following operations: determining that the delay time is equal to the constraint time.

[0219] For example, the determination subunit 7021 determines the response time according to the delay time, including performing the following operations: determining that the response time is less than or equal to the delay time.

[0220] For example, the second timing device performs synchronous processing on the signal sent by the first timing device, and the response model also includes a synchronous processing module, which includes multiple timing devices. The synchronous processing module is configured to perform synchronous processing on the signal sent by the first timing device, and the determination subunit 7021 determines the delay time according to the circuit characteristics, including performing the following operations: determining the constraint time according to the circuit characteristics, wherein the constraint time indicates that the third timing device collects a steady-state response signal at least at a second moment after the first moment, and the first moment differs from the second moment by the constraint time, and the third timing device represents a timing device among the multiple timing devices that is directly connected to the data signal input end of the synchronous processing module; determining the delay time according to the constraint time.

[0221] For example, the determination subunit 7021 determines the response time according to the delay time, including the following operations: determining the processing delay corresponding to the synchronization processing module; and determining the response time according to the processing delay and the delay time.

[0222] For example, the determination subunit 7021 determines the response time according to the processing delay and the delay time, including performing the following operations: determining that the response time is less than or equal to the sum of the processing delay and the delay time.

[0223] For example, in response to the signal received by the third timing device being a metastable signal, when determining subunit 7021 to determine the response time based on the processing delay and the delay time, the following operations are included: determining that the response time is less than or equal to the sum of the processing delay, the metastable delay and the delay time.

[0224] For example, when the adding subunit 7023 executes the operation of adding the response model into the data link determined based on the first timing device and the second timing device in the integrated circuit, it includes performing the following operations: inserting the response model between the second timing device and the device directly connected to the second timing device, and the output end of the response model is directly connected to the data input end of the second timing device.

[0225] For example, the processing unit 702 also includes a naming subunit 7024.

[0226] The naming subunit 7024 is configured to name the simulation model according to the constraint time, so that the name of the simulation model corresponds to the constraint time.

[0227] For example, a metastable signal includes a random signal and an uncertain signal. When the response model executes to output a metastable signal within a response time starting from a first moment, the response model includes performing the following operations: obtaining a signal configuration parameter; and outputting one of a random signal or an uncertain signal within a response time starting from the first moment according to the signal configuration parameter.

[0228] For example, Fig. 7A As shown, the integrated circuit verification apparatus 700 further includes a planning processing unit 704 .

[0229] The planning processing unit 704 is configured to obtain a circuit to be planned that has passed simulation verification, wherein the circuit to be planned includes a plurality of asynchronous sequential device pairs; and perform planning processing on the circuit to be planned.

[0230] Figure 7C A schematic block diagram of a planning processing unit provided for at least one embodiment of the present disclosure.

[0231] For example, Figure 7C As shown, the planning processing unit 704 includes a constraint time acquisition unit 7041 , an optimization unit 7042 , a timing constraint setting unit 7043 and a timing checking unit 7044 .

[0232] For example, the constraint time acquisition unit 7041 is configured to replace at least one response model corresponding to at least one asynchronous timing device pair among multiple asynchronous timing device pairs with a corresponding physical device, wherein the naming of the physical device is the same as the naming of the corresponding response model; and obtain multiple constraint times according to the naming of the physical device.

[0233] For example, the optimization unit 7042 is configured to perform layout and routing optimization on the circuit to be planned according to multiple constraint times.

[0234] For example, the timing constraint setting unit 7043 is configured to set a virtual clock domain; and set timing constraints for multiple asynchronous sequential device pairs in the circuit to be planned according to multiple constraint times.

[0235] For example, when the timing constraint setting unit 7043 executes the setting of the virtual clock domain, it includes performing the following operations: determining at least one virtual clock based on multiple asynchronous timing device pairs and multiple clock domains; for each virtual clock, setting at least one timing path determined based on multiple asynchronous timing device pairs to belong to the same virtual clock domain, wherein the same virtual clock domain is determined based on each virtual clock.

[0236] For example, the timing check unit 7044 is configured to perform timing checks on the plurality of asynchronous sequential device pairs according to the timing constraints set for the plurality of asynchronous sequential device pairs.

[0237] For example, the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 include codes and programs stored in the memory; the processor can execute the code and program to implement some or all of the functions of the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 as described above. For example, the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 can be dedicated hardware devices, used to implement some or all of the functions of the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 as described above. For example, the acquisition unit 701, the processing unit 702, and the simulation verification unit 703 can be a circuit board or a combination of multiple circuit boards, used to implement the functions described above. In an embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processor; and (3) firmware stored in the memory that can be executed by the processor.

[0238] It should be noted that the acquisition unit 701 is used to implement Figure 2 In step S10 shown in FIG. 1 , the processing unit 702 is used to implement Figure 2 In step S20 shown in FIG. 1 , the simulation verification unit 703 is used to implement Figure 2 The step S30 shown in FIG. 7 is shown in FIG. 7 . Therefore, the specific description of the acquisition unit 701 can refer to the embodiment of the above-mentioned integrated circuit verification method. Figure 2 For the description of step S10 shown in FIG. 1 , the specific description of the processing unit 702 can refer to the embodiment of the verification method of the integrated circuit described above. Figure 2 For the description of step S20 shown in FIG. 1 , the specific description of the simulation verification unit 703 can be referred to in the embodiment of the verification method of the integrated circuit described above. Figure 2 In addition, the integrated circuit verification device can achieve the technical effect similar to the aforementioned integrated circuit verification method, which will not be described in detail here.

[0239] At least one embodiment of the present disclosure further provides an electronic device, Figure 8 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0240] For example, Figure 8 As shown, the electronic device includes a processor 1001, a communication interface 1002, a memory 1003 and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other through the communication bus 1004. The components such as the processor 1001, the communication interface 1002, and the memory 1003 can also communicate with each other through a network connection. The present disclosure does not limit the type and function of the network.

[0241] For example, the memory 1003 is used to store computer executable instructions non-transiently. When the processor 1001 is used to execute the computer executable instructions, the computer executable instructions are executed by the processor 1001 to implement the integrated circuit verification method according to any of the above embodiments. The specific implementation of each step of the integrated circuit verification method and related explanations can be found in the embodiments of the integrated circuit verification method described above, and will not be repeated here.

[0242] For example, the implementation manner of the integrated circuit verification method implemented by the processor 1001 executing the program stored in the memory 1003 is the same as the implementation manner mentioned in the embodiment of the integrated circuit verification method mentioned above, and will not be repeated here.

[0243] For example, the communication bus 1004 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industrial Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0244] For example, the communication interface 1002 is used to implement communication between the electronic device and other devices.

[0245] For example, the processor 1001 and the memory 1003 may be arranged on a server side (or a cloud side).

[0246] For example, the processor 1001 can control other components in the electronic device to perform the desired functions. The processor 1001 can be a central processing unit (CPU), a network processor (NP), etc., and can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The central processing unit (CPU) can be an X86 or ARM architecture, etc.

[0247] For example, the memory 1003 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer executable instructions may be stored on the computer-readable storage medium, and the processor 1001 may run the computer executable instructions to implement various functions of the electronic device. Various applications and various data may also be stored in the storage medium.

[0248] For example, for a detailed description of the process of an electronic device performing verification of an integrated circuit, reference may be made to the relevant description in the embodiment of the integrated circuit verification method, and repeated parts will not be repeated.

[0249] Fig. 9 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Fig. 9 As shown, one or more computer executable instructions 1101 may be non-transitorily stored on the storage medium 1100. For example, when the computer executable instructions 1101 are executed by a processor, one or more steps in the integrated circuit verification method described above may be performed.

[0250] For example, the storage medium 1100 may be applied to the verification device 1400 of the electronic device and / or integrated circuit. For example, the storage medium 1100 may include the memory 1003 in the electronic device.

[0251] For example, the description of the storage medium 1100 may refer to the description of the memory in the embodiment of the electronic device, and the repeated parts will not be repeated.

[0252] There are a few points to note about this disclosure:

[0253] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0254] (2) For the sake of clarity, the thickness and size of layers or structures are exaggerated in the drawings used to describe the embodiments of the present invention. It is understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be intervening elements.

[0255] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0256] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for verifying an integrated circuit, wherein: The integrated circuit includes a plurality of asynchronous clock domains, The verification method comprises: Acquire a plurality of asynchronous sequential device pairs, wherein each asynchronous sequential device pair comprises a first sequential device and a second sequential device, the first sequential device and the second sequential device are located in two different clock domains among the plurality of clock domains, and an electrical signal transmission relationship exists between a data output terminal of the first sequential device and a data input terminal of the second sequential device; According to the plurality of asynchronous sequential device pairs, a model building process is performed on the integrated circuit to obtain a circuit to be simulated; Performing front-end simulation verification on the circuit to be simulated; The model building process includes: For each asynchronous sequential device pair described: determining a response time according to circuit characteristics between the first sequential device and the second sequential device; According to the response time, construct a response model, wherein the response model includes an input end and an output end, and the response model is configured to output a metastable signal within the response time starting from a first moment, and output a steady-state response signal after the response time starting from the first moment, and the first moment is the moment when the input signal received by the input end changes; adding the response model into a data link determined in the integrated circuit based on the first sequential device and the second sequential device; The step of determining the response time according to the circuit characteristics between the first sequential device and the second sequential device includes: Determining a delay time according to the circuit characteristics; The response time is determined according to the delay time.

2. The verification method according to claim 1, wherein: Determining the delay time according to the circuit characteristics includes: Determine a constraint time according to the circuit characteristics, wherein the constraint time indicates that the second sequential device collects a steady-state response signal at least at a second moment after the first moment, and the first moment differs from the second moment by the constraint time; The delay time is determined according to the constraint time.

3. The verification method according to claim 2, wherein: The clock domain where the second timing device is located is determined based on the target clock signal, According to the circuit characteristics, the constraint time is determined, including: According to the circuit characteristics, the constraint time is determined to be x clock cycles, wherein the clock cycle is the clock cycle of the target clock signal, and x is a positive integer.

4. The verification method according to claim 3, wherein: Determining the delay time according to the constraint time includes: Determine a decision edge, wherein the decision edge is the first transition edge that appears in the target clock signal after the first moment; Taking the determination edge as the first determination edge, counting y determination edges, where y is a positive number and is less than or equal to x; The time length between the first moment and the yth determination edge is used as the delay time.

5. The verification method according to claim 4, wherein: y is a random value between 0 and x.

6. The verification method according to claim 2, wherein: According to the circuit characteristics, the constraint time is determined, including: According to the circuit characteristics, a maximum delay between the first sequential device and the second sequential device is determined, and the maximum delay is used as the constraint time.

7. The verification method according to claim 6, wherein: Determining the delay time according to the constraint time includes: Determine that the delay time is equal to the constraint time.

8. The verification method according to any one of claims 2 to 7, wherein: Determining the response time according to the delay time includes: Determine that the response time is less than or equal to the delay time.

9. The verification method according to claim 1, wherein: The second sequential device performs synchronization processing on the signal sent by the first sequential device, The response model further includes a synchronization processing module, the synchronization processing module includes a plurality of sequential devices, and the synchronization processing module is configured to perform synchronization processing on the signal sent by the first sequential device. Determining the delay time according to the circuit characteristics includes: Determine a constraint time according to the circuit characteristics, wherein the constraint time indicates that the third sequential device collects a steady-state response signal at least at a second moment after the first moment, the first moment differs from the second moment by the constraint time, and the third sequential device indicates a sequential device directly connected to the data signal input terminal of the synchronization processing module among the multiple sequential devices; The delay time is determined according to the constraint time.

10. The verification method according to claim 9, wherein: Determining the response time according to the delay time includes: Determining a processing delay corresponding to the synchronization processing module; The response time is determined according to the processing delay and the delay time.

11. The verification method according to claim 10, wherein: Determining the response time according to the processing delay and the delay time includes: It is determined that the response time is less than or equal to the sum of the processing delay and the delay time.

12. The verification method according to claim 11, wherein: In response to the signal received by the third timing device being a metastable signal, Determining the response time according to the processing delay and the delay time includes: It is determined that the response time is less than or equal to the sum of the processing delay, the metastable delay, and the delay time.

13. The verification method according to claim 2 or 9, wherein: The model building process also includes: The response model is named according to the constraint time, so that the name of the response model corresponds to the constraint time.

14. The verification method according to claim 1, wherein: Adding the response model into a data link determined in the integrated circuit based on the first sequential device and the second sequential device includes: The response model is inserted between the second sequential device and a device directly connected to the second sequential device, and the output end of the response model is directly connected to the data input end of the second sequential device.

15. The verification method according to claim 1, further comprising: Obtaining a circuit to be planned that passes the simulation verification, wherein the circuit to be planned includes the plurality of asynchronous sequential device pairs; Performing planning processing on the circuit to be planned; The planning process includes: replacing at least one response model corresponding to at least one asynchronous sequential device pair among the plurality of asynchronous sequential device pairs with a corresponding physical device, wherein the naming of the physical device is the same as the naming of the corresponding response model; According to the name of the physical device, a plurality of constraint times are obtained.

16. The verification method according to claim 15, wherein: The planning process also includes: Perform layout and routing optimization on the circuit to be planned according to the multiple constraint times.

17. The verification method according to claim 15, wherein: The planning process also includes: Set up the virtual clock domain; According to the plurality of constraint times, timing constraints are set for a plurality of asynchronous sequential device pairs in the circuit to be planned.

18. The verification method according to claim 17, wherein: Set up the virtual clock domain, including: Determine at least one virtual clock according to the plurality of asynchronous sequential device pairs and the plurality of clock domains; For each virtual clock, at least one timing path determined based on the multiple asynchronous timing device pairs is set to belong to the same virtual clock domain, wherein the same virtual clock domain is determined based on each virtual clock.

19. The verification method according to claim 17, wherein: The planning process also includes: According to the timing constraints set for the multiple asynchronous sequential device pairs, timing checks are performed on the multiple asynchronous sequential device pairs.

20. The verification method according to claim 1, wherein: The metastable signal includes a random signal and an uncertain signal. When the response model executes outputting a metastable signal within the response time starting from the first moment, the following operations are performed: Get signal configuration parameters; According to the signal configuration parameters, one of the random signal or the uncertain signal is output within a response time starting from the first moment.

21. An integrated circuit verification device, wherein: The integrated circuit includes a plurality of asynchronous clock domains, The verification device comprises: an acquisition unit configured to acquire a plurality of asynchronous sequential device pairs, wherein each asynchronous sequential device pair comprises a first sequential device and a second sequential device, the first sequential device and the second sequential device are located in two different clock domains among the plurality of clock domains, and an electrical signal transmission relationship exists between a data output terminal of the first sequential device and a data input terminal of the second sequential device; A processing unit configured to perform a model building process on the integrated circuit according to the plurality of asynchronous sequential device pairs to obtain a circuit to be simulated; A simulation verification unit, configured to perform front-end simulation verification on the circuit to be simulated; The model building process includes: For each asynchronous sequential device pair described: determining a response time according to circuit characteristics between the first sequential device and the second sequential device; According to the response time, construct a response model, wherein the response model includes an input end and an output end, and the response model is configured to output a metastable signal within the response time starting from a first moment, and output a steady-state response signal after the response time starting from the first moment, and the first moment is the moment when the input signal received by the input end changes; adding the response model into a data link determined in the integrated circuit based on the first sequential device and the second sequential device; The step of determining the response time according to the circuit characteristics between the first sequential device and the second sequential device includes: Determining a delay time according to the circuit characteristics; The response time is determined according to the delay time.

22. An electronic device, comprising: A memory non-transitorily stores computer executable instructions; a processor configured to execute the computer executable instructions, Wherein, when the computer executable instructions are executed by the processor, the verification method of the integrated circuit according to any one of claims 1-20 is implemented.

23. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the integrated circuit verification method according to any one of claims 1 to 20 is implemented.

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