A method and device for setting a fixed potential unit in a chip circuit

Abstract

The present application relates to a method and device for setting a fixed potential unit in a chip circuit, including: determining the redundant unit positions of redundant units on the chip circuit; dividing the chip circuit into at least two regional grids according to the preset division strategy based on the redundant unit positions; determining the setting positions of the fixed potential units in the regional grids such that the sum of the distances between the fixed potential units and the redundant units in the same regional grid meets the preset conditions; and determining the wiring information between the output terminals of the fixed potential units and the input terminals of the redundant units according to the setting positions. The method provided by the embodiments of the present application can optimize the setting positions of the fixed potential units, reduce the length of the wiring, thereby reducing the occupation of hardware resources and wiring resources, making the arrangement of the fixed potential units more reasonable, and effectively reducing the power consumption of the chip circuit.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and particularly to a method and device for setting a fixed potential unit in a chip circuit. Background Art

[0002] In chip design, a spare cell has basic logic functions, but its output floats and is not connected to the chip functional circuit. When making Functional ECO (Functional Engineering Change Order) and Metal ECO (Metal Engineering Change Order) changes to the chip, the spare cell becomes a key device. Using the spare cell to build a functional circuit can greatly reduce the workload of engineering change requirements.

[0003] Generally, the input terminal of the spare cell cannot float, otherwise it will cause uncertain states and leakage problems, posing risks to the chip, including: manufacturing violations, increased power consumption, and affecting the yield. Therefore, the input terminal of the spare cell needs to be connected to the output terminal of a tie cell to ensure the stability of the spare cell.

[0004] In the prior art, when physically implementing the chip (the logical function of the chip is realized by a circuit), some design libraries cannot insert a tie cell into the chip circuit diagram and connect the output terminal of the tie cell to the input terminal of the spare cell as required; for other design libraries, although a tie cell can be inserted into the chip circuit diagram, there will be a situation where the number of tie cells is large or the placement is unreasonable, resulting in excessive occupation of hardware resources and wiring resources.

[0005] Regarding the technical problem of being unable to reasonably insert a fixed potential unit in the related art, no effective solution has been provided yet. Summary of the Invention

[0006] To solve the technical problem of being unable to reasonably arrange the position of the tie cell in the prior art, the present application provides a method and device for setting a tie cell in a chip circuit.

[0007] In a first aspect, an embodiment of the present application provides a method for setting a tie cell in a chip circuit, including:

[0008] Determine the position of the spare cell on the chip circuit;

[0009] According to a preset partitioning strategy, partition the chip circuit based on the position of the spare cell to obtain at least two regional grids;

[0010] Determine the setting position of the fixed potential unit in the area grid such that the sum of the distances between the fixed potential unit and the redundant units within the same area grid meets a preset condition;

[0011] Determine the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit according to the setting position.

[0012] Optionally, as in the foregoing method, the partitioning of the chip circuit according to the redundant unit positions according to the preset partitioning strategy includes:

[0013] Determine the grid partitioning information of each area grid according to the preset partitioning strategy;

[0014] Determine the redundant area in the chip circuit where the redundant units are provided;

[0015] Partition the redundant area according to the grid partitioning information.

[0016] Optionally, as in the foregoing method, the determining the setting position of the fixed potential unit in the area grid includes:

[0017] Determine the total distance between each candidate position and each of the redundant units according to the redundant unit positions of the redundant units in the area grid;

[0018] Obtain the setting position according to the candidate position corresponding to the shortest distance among all the total distances.

[0019] Optionally, as in the foregoing method, before determining the correspondence between the fixed potential unit and the redundant unit, it includes:

[0020] Determine the input terminal type of the redundant unit;

[0021] Determine the output terminal type corresponding to the input terminal type;

[0022] Select the fixed potential unit from a preset set of fixed potential units according to the output terminal type.

[0023] Optionally, as in the foregoing method, before determining the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit according to the setting position, it further includes:

[0024] When the fixed potential unit does not meet the preset requirements, delete the original wiring information between the fixed potential unit and the input terminal of the redundant unit.

[0025] Optionally, as in the foregoing method, the determining the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit includes:

[0026] When the fixed potential unit includes a first output terminal and a second output terminal, determine a first redundant unit corresponding to the first output terminal and a second redundant unit corresponding to the second output terminal;

[0027] Determine first wiring information between the first output terminal and the first redundant unit, and second wiring information between the second output terminal and the second redundant unit.

[0028] Optionally, as in the foregoing method, the determining the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit includes:

[0029] Obtain attribute information of the fixed potential unit;

[0030] When the attribute information does not meet a preset integrity requirement, determine the output terminal type of the output terminal and the input terminal type of the redundant unit;

[0031] According to the output terminal type and the input terminal type, obtain a third redundant unit corresponding to the fixed potential unit;

[0032] Determine third wiring information between the output terminal of the fixed potential unit and the input terminal of the third redundant unit.

[0033] In a second aspect, an embodiment of the present application provides a device for setting a fixed potential unit in a chip circuit, including:

[0034] A determination module, configured to determine the position information of redundant units on the chip circuit;

[0035] A division module, configured to perform area division on the chip circuit according to the position information according to a preset division strategy to obtain at least two area grids;

[0036] A position module, configured to determine the setting position of the fixed potential unit in the area grid so that the sum of the distances between the fixed potential unit and the redundant units in the same area grid meets a preset condition;

[0037] A wiring module, configured to determine the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit according to the setting position.

[0038] In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0039] The memory is used to store a computer program;

[0040] When the processor executes the computer program, it implements the method described in any of the foregoing items.

[0041] In a fourth aspect, an embodiment of the present application provides a storage medium, which includes a stored program. When the program runs, it executes the method described in any of the previous items.

[0042] The above technical solutions provided by the embodiments of the present application have the following advantages compared with the prior art:

[0043] The method provided by the embodiment of the present application can optimize the setting position of the fixed potential unit, reduce the length of the wiring, and thus can occupy the hardware resources and wiring resources, make the layout of the fixed potential unit more reasonable, and can effectively reduce the power consumption of the chip circuit. Description of the Drawings

[0044] The drawings here are incorporated into the specification and form a part of this specification, showing the embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0046] Figure 1 It is a flowchart of a method for setting a fixed potential unit in a chip circuit provided by an embodiment of the present application;

[0047] Figure 2 It is a flowchart of a method for setting a fixed potential unit in a chip circuit provided by another embodiment of the present application;

[0048] Figure 3 It is a flowchart of a method for setting a fixed potential unit in a chip circuit provided by another embodiment of the present application;

[0049] Figure 4 It is a schematic diagram of a chip circuit provided by an embodiment of the present application;

[0050] Figure 5 It is a flowchart of a method for setting a fixed potential unit in a chip circuit in an application example of the present application;

[0051] Figure 6 It is a block diagram of a device for setting a fixed potential unit in a chip circuit provided by an embodiment of the present application;

[0052] Figure 7 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0053] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0054] Figure 1 A method for setting a fixed potential unit in a chip circuit provided by an embodiment of the present application includes the following steps S1 to S4:

[0055] Step S1. Determine the redundant unit positions of the redundant units on the chip circuit.

[0056] Specifically, the redundant unit position refers to the position where the redundant unit is set on the chip circuit. Generally, there are multiple redundant units in the chip circuit, and for the sake of the neatness of the chip circuit design, the redundant units are evenly arranged in the chip circuit (two adjacent redundant units are arranged in the same row or the same column, and the row spacing and the spacing generally remain fixed).

[0057] Furthermore, redundant units are not necessarily distributed on the entire chip circuit. Therefore, redundant units may only be set in some areas of some chip circuits.

[0058] Step S2. According to a preset partitioning strategy, partition the chip circuit based on the redundant unit positions to obtain at least two regional grids.

[0059] Specifically, the partitioning strategy may correspond to the layout of the redundant units on the chip circuit. For example, when two adjacent redundant units are arranged in the same row or the same column, the partitioning strategy may be: partitioning the chip circuit with a rectangular frame to obtain at least two regional grids and a plurality of redundant unit sets.

[0060] Generally, when the redundant units are evenly distributed, the number of redundant units in each regional grid is the same.

[0061] Step S3. Determine the setting positions of the fixed potential units in the regional grids such that the sum of the distances between the fixed potential units and the redundant units in the same regional grid meets a preset condition.

[0062] Specifically, the setting position is used to set the position of the fixed potential unit. When only one fixed potential unit needs to be set in a regional grid, the setting position can be the position corresponding to the fixed potential unit. When multiple fixed potential units need to be set, the setting position can be the positions corresponding to multiple fixed potential units.

[0063] The preset condition can be: among all the optional positions, when the fixed potential unit is arranged at the setting position, the sum of the distances corresponding to the connections between the output end of the fixed potential unit and the input ends of each redundant unit is the shortest.

[0064] Step S4. Determine the wiring information between the output end of the fixed potential unit and the input end of the redundant unit according to the setting position.

[0065] Specifically, the wiring information can include: within the same regional grid, the length of the wiring between the output end of the fixed potential unit and the input ends of each redundant unit, the wiring path and other information; and when there are multiple fixed potential units, determine the sub-wiring information corresponding to each fixed potential unit respectively, and finally obtain the wiring information according to each sub-wiring information.

[0066] Moreover, after the setting of the fixed potential unit and the determination of the wiring information are completed in all the regional grids, it is determined that the wiring connections of all the redundant units in the chip circuit are completed.

[0067] Through the method in this embodiment, the setting position of the fixed potential unit can be optimized, the length of the wiring can be reduced, and thus the occupation of hardware resources and wiring resources can be reduced. The arrangement of the fixed potential unit can be made more reasonable, and the power consumption of the chip circuit can be effectively reduced.

[0068] As Figure 2 shown, in some embodiments, like the aforementioned method, step S2 divides the chip circuit according to the redundant unit positions according to a preset division strategy, including the following steps S21 to S23:

[0069] Step S21. Determine the grid division information of each regional grid according to the preset division strategy.

[0070] Specifically, the grid division information can be information such as the shape, size, position, etc. used to define each divided regional grid.

[0071] Step S22. Determine the redundant area in the chip circuit where redundant units are provided.

[0072] Specifically, in the chip circuit, redundant units are not evenly distributed in all areas. Therefore, there is no need to set a fixed potential unit in the area where no redundant unit is provided, and there is no need to perform regional division.

[0073] Meanwhile, the method for determining the redundant area can be as follows: First, determine the setting areas of each redundant unit, then determine the setting positions of the outermost redundant units located in the redundant unit setting areas, and further obtain the redundant area based on the setting positions of the outermost redundant units; further, in order to prevent the redundant units from being divided on the edge of the area grid during area division, the redundant unit setting edge can be obtained based on the setting positions of the outermost redundant units, and then a preset length is extended outward from the center at the redundant unit setting edge, so that redundant units can be avoided on the edge of the obtained redundant area.

[0074] Step S23. Perform area division on the redundant area according to the grid division information.

[0075] Specifically, after determining the redundant area and the grid division information, the redundant area can be divided according to the grid division information starting from the edge or a certain vertex of the redundant area.

[0076] For example, when obtaining a rectangular redundant area according to the redundant unit positions:

[0077] Take the lower left corner coordinates of the redundant area as (XL0, YL0), and the upper right corner coordinates as (XR3, YR3). These two coordinates can specify the area.

[0078] When the shape of the grid in the grid division information is rectangular with a length of L and a width of W, take the lower left corner coordinates of a certain minimum area as (x1, y1), and the upper right corner coordinates as (x2, y2). These two coordinates can specify the area. Similarly, there is a relationship: the abscissa x2 - x1 = L, and the ordinate y2 - y1 = W. If the length and width of the redundant area are integer multiples of the length and width of the virtual rectangle, then the number of area grids obtained by division is (YR3 - YL0) × (XR3 - XL0) / (L × W); if the length is an integer multiple and the width is not an integer multiple, then the number of fixed potential units inserted is ([(YR3 - YL0) | / W] + 1) × ((XR3 - XL0) / L); if the width is an integer multiple and the length is not an integer multiple, then the number of area grids obtained by division is ([(XR3 - XL0) / L] + 1) × ((YR3 - YL0) / W); if neither the width nor the length is an integer multiple, then the number of area grids obtained by division is ([(XR3 - XL0) / L)] + 1) × ([(YR3 - YL0) / W] + 1).

[0079] As Figure 3 shown, in some embodiments, as in the foregoing method, step S3 for determining the setting positions of the fixed potential units in the area grid includes the following steps S31 and S32:

[0080] Step S31. Determine the total distance between each candidate position and each redundant cell according to the redundant cell positions of the redundant cells in the regional grid.

[0081] Specifically, after obtaining the regional grid, the redundant cells included in the regional grid can be determined.

[0082] The candidate position can be any position in the regional grid. In a chip circuit, generally, redundant cells and fixed potential cells are arranged among many basic device cells (for implementing arithmetic logic), such as Figure 4 As shown, the setting position of each redundant cell, fixed potential cell or basic device cell is within the smallest rectangle. Therefore, the candidate positions in the regional grid are the positions of each smallest rectangle.

[0083] The candidate positions are selected from other smallest rectangles outside the redundant cell positions in the regional grid.

[0084] After determining the candidate positions, the positions of the input ends on the redundant cells and the positions of the output ends on the fixed potential cells can be determined; then, when the fixed potential cell is arranged at each candidate position, the connection lengths after the output ends on the fixed potential cell are connected to the input ends on each redundant cell in the same regional grid are determined; finally, the total distance is obtained according to each connection length.

[0085] Step S32. Obtain the setting position according to the candidate position corresponding to the shortest distance among all the total distances.

[0086] Specifically, after obtaining the total distances corresponding to each candidate position in the regional grid, the shortest distance among them can be determined, and the candidate position corresponding to the shortest distance is used as the setting position of the fixed potential cell in the regional grid.

[0087] For example, on the basis of the examples given in Steps S21 to S23, when the redundant area of the rectangle is obtained according to the redundant cell positions, and each redundant cell is arranged in a uniform row and column pattern as Figure 4 As shown:

[0088] One optional implementation method can be: draw a virtual rectangle starting from the origin at the lower left corner of the redundant area, and the coordinates of the regional grids corresponding to the obtained rectangles are in turn:

[0089] {(XL0,YL0)(XL0+L,YL0+W)},{(XL0,YL0+W)(XL0+L,YL0+2W)},{(XL0,YL0+2W)(XL0+L,YL0+3W)}...{(XL0+L,YL0)(XL0+2L,YL0+W)},{(XL0+L,YL0+W)(XL0+2L,YL0+2W)},{(XL0+L,YL0+2W)(XL0+2L,YL0+3W)}...

[0090] After obtaining the rectangular area grid, the central coordinate points of the virtual rectangle are obtained through its horizontal and vertical coordinate points, and the smallest rectangle where the central coordinate points are located is used as the setting position of the fixed potential unit;

[0091] Another optional implementation method may be:

[0092] According to the positions of each redundant unit in the redundant area, the shape formed by the redundant units is obtained. As Figure 4 shown, in this case, the shape is rectangular; therefore, the setting position of the fixed potential unit can be obtained according to the center of this rectangle.

[0093] In some embodiments, such as the foregoing method, before determining the correspondence between the fixed potential unit and the redundant unit, the following steps P11 to P13 are included:

[0094] Step P11. Determine the input terminal type of the redundant unit.

[0095] Specifically, the input terminal type can be divided according to the levels (which can be 0 or 1) acceptable at the input terminals of different redundant units. Therefore, the input terminal types can be defined as: type 0 input terminal and type 1 input terminal.

[0096] Step P12. Determine the output terminal type corresponding to the input terminal type.

[0097] Specifically, the fixed potential unit can also be divided into multiple different types according to the output potential, and the output levels can be: output level is 0, output level is 1, and both output levels 0 and 1 can be output simultaneously.

[0098] Therefore, the output terminal types can be defined as: type 0 output terminal, type 1 output terminal, and dual-type output terminal.

[0099] Since different input terminal types require different output terminal types to output their levels, the input terminal types can have corresponding output terminal types: type 0 input terminal can correspond to type 0 output terminal and dual-type output terminal; type 1 input terminal can correspond to type 1 output terminal and dual-type output terminal.

[0100] Step P13. Select a fixed potential unit from a preset set of fixed potential units according to the output terminal type.

[0101] Specifically, the set of fixed potential units may include fixed potential units of different output terminal types. Therefore, after the output terminal type corresponding to the input terminal type has been determined in the foregoing step, the fixed potential unit corresponding to the input terminal type can be determined.

[0102] Through the method in this embodiment, the fixed potential units applicable to each redundant area can be automatically screened, which can improve the efficiency of setting the fixed potential units and can effectively prevent errors and other situations during manual design.

[0103] In some embodiments, as in the foregoing method, before determining the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit according to the setting position, the following step P21 is further included:

[0104] Step P21. When the fixed potential unit does not meet the preset requirements, delete the original wiring information between the fixed potential unit and the input terminal of the redundant unit.

[0105] Specifically, the solution of this application is generally applied to EDA chip design software. Therefore, the situation where the fixed potential unit does not meet the preset requirements may be: a specific type of fixed potential unit that cannot be recognized in the existing EDA chip design software, resulting in the inability of the specific type of fixed potential unit to be connected to the redundant unit, or unable to be accurately connected to the redundant unit, or unable to be connected to the redundant unit in an optimal connection manner.

[0106] Therefore, in the above situation, it is necessary to delete the connection between the redundant unit and the fixed potential unit established by the existing EDA chip design software to avoid wiring chaos.

[0107] In some embodiments, as in the foregoing method, step S4 of determining the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit includes the following steps S411 and S412:

[0108] Step S411. When the fixed potential unit includes a first output terminal and a second output terminal, determine a first redundant unit corresponding to the first output terminal and a second redundant unit corresponding to the second output terminal.

[0109] Specifically, the first output terminal and the second output terminal may be output terminals respectively used for outputting two different levels (for example: level 0 and level 1).

[0110] The first redundant unit and the second redundant unit can be one of the levels 0 or 1 acceptable at the input end, and the levels acceptable by the first redundant unit and the second redundant unit are different.

[0111] Moreover, the level output at the first output end is consistent with the level input at the input end of the first redundant unit; the level output at the second output end is consistent with the level input at the input end of the second redundant unit.

[0112] In the EDA chip design software in the prior art, a fixed potential unit that can output two levels simultaneously cannot be accurately identified, which may lead to the incorrect connection of each output end to the input end of a non-corresponding redundant unit. For example, in the prior art, due to the inability to accurately identify the fixed potential unit of the type in this embodiment, it may cause the output end with an output level of 0 to be connected to a redundant unit that can only accept a level of 1.

[0113] In one optional implementation, the number of output ends included in the fixed potential unit can be obtained. When the number is 2, the output end types of the first output end and the second output end are respectively obtained; then the types of each redundant unit in the same area grid are determined; furthermore, the first redundant unit corresponding to the first output end and the second redundant unit corresponding to the second output end are obtained.

[0114] Step S411. Determine the first wiring information between the first output end and the first redundant unit, and the second wiring information between the second output end and the second redundant unit.

[0115] Specifically, after obtaining the first redundant unit corresponding to the first output end and the second redundant unit corresponding to the second output end, the method in the foregoing embodiment can be followed: by obtaining the connection lines between the first output end and each first redundant unit and the connection lines between the second output end and each second redundant unit when the fixed potential unit is placed at different positions in the area grid, the sum of the distances corresponding to different positions is obtained, and when the sum of the distances is the shortest, the first wiring information between the first output end and the first redundant unit and the second wiring information between the second output end and the second redundant unit can be obtained.

[0116] Through the method in this embodiment, when the EDA chip design software in the prior art cannot identify a fixed potential unit including two types of output ends, resulting in the connection of the output end to an incompatible redundant unit, it can effectively supplement the prior art to adapt to more application scenarios and improve the accuracy of wiring.

[0117] In the EDA chip design software in the prior art, only virtual units with complete attributes and existing in a preset design library can be recognized; for virtual units in a special database or virtual units with incomplete attributes, due to the inability to accurately recognize them, the wiring between the fixed potential unit and the redundant unit is chaotic. To solve this technical problem, in some embodiments, as described in the foregoing method, the wiring information between the output end of the fixed potential unit and the input end of the redundant unit is determined, including the following steps S421 to S424:

[0118] Step S421. Obtain the attribute information of the fixed potential unit.

[0119] Specifically, the attribute information is information used to characterize the characteristics of the fixed potential unit, such as: information such as color, size, etc.

[0120] Step S422. When the attribute information does not meet the preset integrity requirements, determine the output end type of the output end and the input end type of the redundant unit.

[0121] Specifically, the integrity requirement may be consistent with the information of the attributes required for the EDA chip design software in the prior art to accurately recognize the fixed potential unit.

[0122] That is: when the attribute information cannot meet the recognition requirements of the existing EDA chip design software, it can be input into the existing EDA chip design software through the script implementing the method of this embodiment, so as to be able to recognize the fixed potential unit and determine the output end type of the output end.

[0123] In order to connect the input end of the redundant unit to the corresponding output end, it is therefore necessary to obtain the input end type of the redundant unit. In one optional implementation, the input end type can be obtained by recognizing the attributes of the redundant unit.

[0124] Step S423. According to the output end type and the input end type, obtain the third redundant unit corresponding to the fixed potential unit.

[0125] Specifically, each output end type has a corresponding input end type, and a corresponding relationship can be established between the two. Therefore, according to the output end type, among all the redundant units, the third redundant unit corresponding to the fixed unit can be determined.

[0126] Step S424. Determine the third wiring information between the output end of the fixed potential unit and the input end of the third redundant unit.

[0127] Specifically, after obtaining the third redundant unit corresponding to the fixed potential unit, the method in the foregoing embodiment can be followed: by obtaining the connection lines between the output end of the fixed potential unit and each third redundant unit when the fixed potential unit is set at different positions in the regional grid, obtaining the sum of distances corresponding to different positions, and when the sum of distances is the shortest, the third wiring information between the third redundant units corresponding to the fixed potential unit can be obtained.

[0128] Through the method in this embodiment, when the attribute information of the fixed potential unit is incomplete or does not correspond to the design library in the existing EDA chip design software, the fixed potential unit can be accurately identified, thereby ensuring accurate wiring.

[0129] As Figure 5 shown, the application examples of applying any of the foregoing embodiments are as follows:

[0130] A1. Redundant area determination: Determine the redundant area in the chip circuit according to the distribution of redundant units.

[0131] A2. Determine the minimum area of the fixed potential unit: Divide the redundant area according to the division strategy and determine the finally divided minimum area (i.e., the regional grid).

[0132] A3. Grid the redundant unit area: After dividing the entire redundant area, at least two regional grids are obtained.

[0133] A4. Insert the fixed potential unit into the regional grid.

[0134] A5. Whether it is a special fixed potential unit, that is, the fixed potential unit includes two types of output ends, or the attribute information of the fixed potential unit does not meet the preset integrity requirements; if so, jump to A6, otherwise jump to A7.

[0135] A6. Interrupt the original input connection of the redundant unit: When the fixed potential unit is a special fixed potential unit, the EDA chip design software will make an incorrect connection between the fixed potential unit and the redundant unit, so the original input connection in the redundant unit needs to be deleted.

[0136] A7. Connect the corresponding redundant unit and the fixed potential unit, determine the corresponding relationship between the redundant unit and the fixed potential unit, and then make the connection.

[0137] A8. Whether all regional grids are completed: Judge whether the redundant units in each regional grid are all connected to the fixed potential unit. If not, jump to step A4 and perform the operation of inserting the fixed potential unit in the regional grid where the fixed potential unit has not been inserted; if so, go to step A9.

[0138] A9. Chip circuit wiring, wiring the chip circuit according to the wiring design.

[0139] As Figure 6 shown, according to an embodiment of another aspect of the present application, there is also provided a device for setting a fixed potential unit in a chip circuit, including:

[0140] Determination module 1, configured to determine the position information of redundant units on the chip circuit;

[0141] Partitioning module 2, configured to partition the chip circuit into at least two regional grids according to the preset partitioning strategy based on the position information;

[0142] Position module 3, configured to determine the setting position of the fixed potential unit in the regional grid such that the sum of the distances between the fixed potential unit and the redundant units within the same regional grid meets the preset conditions;

[0143] Wiring module 4, configured to determine the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit according to the setting position.

[0144] Specifically, for the specific process of each module in the device of the embodiment of the present invention to implement its function, reference can be made to the relevant description in the method embodiment, which will not be elaborated here.

[0145] According to another embodiment of the present application, there is also provided an electronic device, including: As Figure 7 shown, the electronic device may include: a processor 1501, a communication interface 1502, a memory 1503, and a communication bus 1504. Among them, the processor 1501, the communication interface 1502, and the memory 1503 communicate with each other through the communication bus 1504.

[0146] The memory 1503 is used to store computer programs;

[0147] The processor 1501, when executing the programs stored on the memory 1503, implements the steps of the above method embodiment.

[0148] The bus mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of simplicity, only a thick line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0149] The communication interface is used for communication between the above electronic device and other devices.

[0150] The memory may include a Random Access Memory (RAM), or may also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located far from the aforementioned processor.

[0151] The aforementioned processor may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0152] The embodiments of the present application also provide a storage medium, where the storage medium includes a stored program, and when the program runs, it executes the method steps of the above method embodiments.

[0153] It should be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0154] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for setting a fixed potential unit in a chip circuit, characterized in that, it includes: Determine the redundant unit positions of redundant units on the chip circuit; According to a preset partitioning strategy, partition the chip circuit based on the redundant unit positions to obtain at least two regional grids; Determine the setting positions of the fixed potential units in the regional grids such that the sum of the distances between the fixed potential units and the redundant units in the same regional grid meets a preset condition. Determining the setting positions of the fixed potential units in the regional grids includes: determining the total distance between each candidate position and each of the redundant units according to the redundant unit positions of the redundant units in the regional grid; obtaining the setting position according to the candidate position corresponding to the shortest distance among all the total distances; Determine the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit according to the setting position.

2. The method according to claim 1, characterized in that, the partitioning the chip circuit according to the redundant unit positions according to a preset partitioning strategy includes: Determine the grid partitioning information of each regional grid according to the preset partitioning strategy; Determine the redundant regions in the chip circuit where the redundant units are provided; Partition the redundant regions according to the grid partitioning information.

3. The method according to claim 1, characterized in that, before determining the correspondence between the fixed potential unit and the redundant unit, it includes: Determine the input terminal type of the redundant unit; Determine the output terminal type corresponding to the input terminal type; Select the fixed potential unit from a preset set of fixed potential units according to the output terminal type.

4. The method according to claim 1, characterized in that, before determining the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit according to the setting position, it further includes: When the fixed potential unit does not meet the preset requirements, delete the original wiring information between the fixed potential unit and the input terminal of the redundant unit.

5. The method according to claim 1, characterized in that, the determining the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit includes: When the fixed potential unit includes a first output terminal and a second output terminal, determine a first redundant unit corresponding to the first output terminal and a second redundant unit corresponding to the second output terminal; Determine the first wiring information between the first output terminal and the first redundant unit and the second wiring information between the second output terminal and the second redundant unit.

6. The method according to claim 1, characterized in that, the determining the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit includes: Obtain the attribute information of the fixed potential unit; When the attribute information does not meet the preset integrity requirements, determine the output terminal type of the output terminal and the input terminal type of the redundant unit; Obtain a third redundant unit corresponding to the fixed potential unit according to the output terminal type and the input terminal type; Determine the third wiring information between the output terminal of the fixed potential unit and the input terminal of the third redundant unit.

7. A device for setting a fixed potential unit in a chip circuit, characterized in that, it includes: a determination module, configured to determine the position information of redundant units on the chip circuit; a division module, configured to divide the chip circuit into at least two regional grids according to a preset division strategy based on the position information; a position module, configured to determine the installation position of the fixed potential unit in the regional grid so that the sum of the distances between the fixed potential unit and the redundant units in the same regional grid meets a preset condition. Determining the installation position of the fixed potential unit in the regional grid includes: determining the total distance between each candidate position and each of the redundant units according to the redundant unit positions of the redundant units in the regional grid; obtaining the installation position according to the candidate position corresponding to the shortest distance among all the total distances; a wiring module, configured to determine the wiring information between the output terminal of the fixed potential unit and the input terminal of the redundant unit according to the installation position.

8. An electronic device, characterized in that, it includes: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory complete communication with each other through the communication bus; the memory is used for storing a computer program; the processor is configured to implement the method according to any one of claims 1-6 when executing the computer program.

9. A storage medium, characterized in that, the storage medium includes a stored program, wherein the program executes the method according to any one of claims 1-6 when running.

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