Display panel

Abstract

The application provides a display panel, which comprises a display area and a non-display area, and comprises a shielding structure and a thin film transistor, the shielding structure comprises a shielding part located in the display area and an in-plane wire, and a peripheral wire located in the non-display area, the shielding part is arranged below the thin film transistor, and the projection of the channel of the thin film transistor on the shielding part falls in the shielding part, the shielding part is electrically connected with the in-plane wire, and the in-plane wire at least at one position is electrically connected with the peripheral wire through an electrostatic protection circuit. The electrostatic protection circuit is additionally arranged between the in-plane wire and the peripheral wire, the electrostatic protection circuit protects the electrostatic safety of the connection between the peripheral wire and the in-plane wire, and the problem that the display panel is damaged by static electricity due to instantaneous large current is avoided.

Description

Technical Field

[0001] This application relates to the field of displays, and more particularly to a display panel. Background Technology

[0002] In existing display panels, a metal shielding layer (BSM) is typically placed at the location corresponding to the channel region of the thin-film transistor to protect the channel of the thin-film transistor.

[0003] like Figure 1 As shown, the metal shielding layer includes in-plane traces and peripheral traces. The in-plane traces are arranged in a grid pattern across the entire surface, while the peripheral traces are single loop lines. The in-plane traces and peripheral traces connect at the boundary between the display area and the non-display area. The in-plane traces accumulate electrostatic charge and conduct this charge to the single peripheral trace. As the electrostatic charge accumulates on the single peripheral trace, when it reaches a certain amount, it generates a sudden large current, causing electrostatic discharge damage to the display panel. Summary of the Invention

[0004] This invention provides a display panel to solve the problem of electrostatic damage to the metal shielding layer in existing display panels.

[0005] To solve the above problems, the technical solution provided by the present invention is as follows:

[0006] This invention provides a display panel comprising a display area and a non-display area. The display panel includes a shielding structure and a thin-film transistor (TFT). The shielding structure includes a shielding portion and in-plane traces located within the display area, and peripheral traces located within the non-display area. The shielding portion is disposed below the TFT, and the projection of the TFT channel onto the shielding portion falls within the shielding portion. The shielding portion is electrically connected to the in-plane traces.

[0007] At least one of the in-plane traces is electrically connected to the peripheral traces via an electrostatic discharge protection circuit.

[0008] Optionally, in some embodiments of the present invention, the electrostatic protection circuit includes a diode and a capacitor, the diode and the capacitor are connected in parallel, the anode of the diode is connected to the in-plane trace, and the cathode of the diode is connected to the peripheral trace.

[0009] Optionally, in some embodiments of the present invention, the display panel includes an active layer, the active layer including the channel and the diode.

[0010] Optionally, in some embodiments of the present invention, the display panel further includes a substrate and a metal layer, the active layer is disposed between the substrate and the metal layer, the active layer further includes a first electrode plate of the capacitor, and the metal layer includes a second electrode plate of the capacitor.

[0011] Optionally, in some embodiments of the present invention, the diode and the first electrode plate have the same structure.

[0012] Optionally, in some embodiments of the present invention, the first electrode plate is in direct contact with the positive electrode of the diode.

[0013] Optionally, in some embodiments of the present invention, the second electrode plate is electrically connected to the peripheral wiring through a via.

[0014] Optionally, in some embodiments of the present invention, the second electrode plate is electrically connected to the negative electrode of the diode through a via.

[0015] Optionally, in some embodiments of the present invention, the metal layer is a gate metal layer or a source / drain metal layer.

[0016] Optionally, in some embodiments of the present invention, the display panel further includes a substrate, a gate metal layer, and a source / drain metal layer, wherein the active layer is disposed between the substrate and the gate metal layer, the gate metal layer is disposed between the active layer and the source / drain metal layer, the gate metal layer includes a first electrode plate of the capacitor, and the source / drain metal layer includes a second electrode plate of the capacitor.

[0017] This invention provides a display panel that incorporates an electrostatic discharge (ESD) protection circuit between the in-plane traces and the peripheral traces. This ESD protection circuit safeguards the connection between the peripheral traces and the in-plane traces from ESD, preventing the display panel from being damaged by ESD due to instantaneous high current. Attached Figure Description

[0018] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0019] Figure 1 A simplified planar schematic diagram of the metal shielding layer of a display panel provided for the prior art;

[0020] Figure 2 A simplified planar schematic diagram of the metal shielding layer of the display panel provided in an embodiment of the present invention;

[0021] Figure 3 An enlarged schematic diagram of the electrostatic protection circuit provided in an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of a first structure of a display panel provided in an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of a second structure of a display panel provided in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of a third structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions in the embodiments and / or examples of the present invention will be clearly and completely described below with reference to specific implementation schemes. Obviously, the embodiments and / or examples described below are only a part of the embodiments and / or examples of the present invention, and not all of them. Based on the embodiments and / or examples of the present invention, all other embodiments and / or examples obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0026] The directional terms used in this invention, such as [up], [down], [left], [right], [front], [back], [inside], [outside], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrating and understanding this invention, and not for limiting it. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0027] To address the problem of electrostatic discharge damage to the metal shielding layer in existing display panels, this invention provides a display panel that can solve this problem.

[0028] In one embodiment, please refer to Figure 2 , Figure 2 A simplified planar schematic diagram of a display panel provided in an embodiment of the present invention is shown. Figure 2 As shown, the display panel provided in this embodiment of the invention includes a display area AA and a non-display area NA. The display panel includes a shielding structure and a thin-film transistor (not shown). The shielding structure includes a shielding portion (not shown) and an in-plane trace 11 located in the display area, and a peripheral trace 12 located in the non-display area. The shielding portion is disposed below the thin-film transistor, and the projection of the channel of the thin-film transistor onto the shielding portion falls within the shielding portion. The shielding portion is electrically connected to the in-plane trace.

[0029] At least one of the in-plane traces 11 and the peripheral traces 12 are electrically connected through an electrostatic protection circuit.

[0030] This invention provides an electrostatic discharge (ESD) protection circuit between the in-plane traces and the peripheral traces. This circuit protects the connection between the peripheral traces and the in-plane traces from ESD, preventing electrostatic damage to the display panel caused by a sudden surge in current.

[0031] In one embodiment, such as Figure 2 As shown, the in-plane traces 11 are typically configured as a grid. These grid-shaped in-plane traces are electrically connected to the shielding portions, thereby connecting all the shielding portions within the display area AA together and uniformly distributing the electrostatic charge on the shielding portions to the peripheral traces 12. The grid-shaped in-plane traces include, for example... Figure 2 As shown, there are vertical in-plane traces extending upwards and downwards, and horizontal in-plane traces extending left and right, which connect at their intersections. The peripheral trace 12 is a single loop trace surrounding the display area AA. Therefore, all the horizontal in-plane traces are electrically connected to the peripheral traces 12 located on the left and right sides of the display area AA, and all the vertical in-plane traces are electrically connected to the peripheral traces 12 located on the top and bottom sides of the display area AA. In other embodiments, the arrangement of the in-plane traces 11 and the peripheral traces 12 can be adjusted according to the specific structure of the display panel, and is not limited here.

[0032] In one embodiment, such as Figure 2 As shown, all the in-plane traces 11 are electrically connected to the peripheral traces 12 through the electrostatic discharge (ESD) protection circuit 13. That is, all the horizontal in-plane traces are electrically connected to the peripheral traces 12 located on the left and right sides of the display area AA through the ESD protection circuit 13. In this way, all the in-plane traces 11 and peripheral traces 12 are protected against electrostatic discharge (ESD) through the ESD protection circuit, ensuring ESD safety at each connection point between the in-plane traces 11 and peripheral traces 12 on the display panel and preventing ESD damage to the display panel caused by instantaneous high current. In other embodiments, only a portion of the in-plane traces 11 and peripheral traces 12 can be electrically connected through the ESD protection circuit, while the remaining in-plane traces 11 are directly electrically connected to the peripheral traces. This can also alleviate the problem of ESD damage to the display panel caused by instantaneous high current to some extent, even when space is limited.

[0033] In one embodiment, such as Figure 3As shown, the electrostatic discharge (ESD) protection circuit 13 includes a diode D and a capacitor C, which are connected in parallel. The positive terminal of the diode D is connected to the in-plane trace 11, and the negative terminal of the diode D is connected to the peripheral trace 12. When there is not much static charge accumulation on the peripheral trace 12, the static charge accumulated on the in-plane trace 11 flows through the diode D, is conducted to the peripheral trace 12, and is released. When a large static charge accumulates on the peripheral trace 12, a momentary large current is generated, which is conducted to the in-plane trace 11. The diode D prevents the peripheral trace 12 from forming a path to the in-plane trace 11. At this time, the capacitor C can store the charge on the peripheral trace 12. Subsequently, the capacitor C can slowly release the stored charge, eliminating the charge on the peripheral trace 12. The ESD protection circuit 13 returns to its normal operating state, and the charge accumulated on the in-plane trace 11 flows through the diode D, is conducted to the peripheral trace 12, and is released. This invention provides an electrostatic protection circuit in which the diode and the capacitor are connected in parallel. When the current in the peripheral traces is greater than the current in the in-plane traces, the electrostatic protection circuit is disconnected, preventing the accumulated charge in the peripheral traces from forming a large current path. This avoids the problem of electrostatic damage to the display panel caused by a sudden large current.

[0034] In one embodiment, please refer to Figure 4 , Figure 4 This diagram illustrates a first structural schematic of a display panel provided in an embodiment of the present invention. Figure 5 A schematic diagram of a second structure of a display panel provided in an embodiment of the present invention is shown. For example... Figure 4 and Figure 5 As shown, the display panel includes a substrate 20, a shielding layer 10, an active layer 50, and a metal layer 70. The shielding layer 10 is disposed between the substrate 20 and the active layer 50. The shielding layer 10 is patterned to form the shielding portion (not shown), the in-plane trace 11, and the peripheral trace 12. The in-plane trace 11 and the peripheral trace 12 are not in contact. The active layer 50 is disposed between the shielding layer 10 and the metal layer 70. The active layer 50 is patterned to form the first electrode plate of the diode D and the capacitor C. The diode D includes a P-type region and an N-type region. The P-type region and the N-type region are in contact. The P-type region is the positive electrode of the diode D, and the N-type region is the negative electrode of the diode D. The metal layer 70 is patterned to form the second electrode plate 71 of the capacitor C. The positive electrode of the diode D is electrically connected to the first electrode plate and the in-plane trace 11, and the negative electrode of the diode D is electrically connected to the second electrode plate 71 and the peripheral trace 12.

[0035] In one implementation scheme, such as Figure 4 and Figure 5 As shown, the diode D is reused as the first electrode plate of the capacitor C, which simplifies the fabrication process of the active layer 50 and reduces the space occupied by the electrostatic protection circuit 13. In other embodiments, the diode D and the first electrode plate of the capacitor C can be two independent parts, and the positive terminal of the diode is electrically connected to the first capacitor.

[0036] The display panel further includes a buffer layer 30, a first insulating layer 40, and a second insulating layer 60. The buffer layer 30 is disposed between the substrate 20 and the shielding layer 10. The first insulating layer 40 is disposed between the shielding layer 10 and the active layer 50. The second insulating layer 60 is disposed between the active layer 50 and the metal layer 70. The anode of the diode D is electrically connected to the in-plane trace 11 through a via penetrating the first insulating layer 40, and the cathode of the diode D is electrically connected to the peripheral trace 12 through a via penetrating the first insulating layer 40. In one embodiment, as... Figure 4 As shown, the second electrode plate 71 is electrically connected to the peripheral trace 12 through a via penetrating the second insulating layer 60 and the first insulating layer 40, thereby being electrically connected to the negative electrode of the diode D. In this way, the diode D and the second electrode plate 71 are directly connected to the peripheral trace 12 through vias, achieving better electrical conductivity between the second electrode plate 71 and the peripheral trace 12. In another embodiment, as... Figure 4 As shown, the second electrode plate 71 is electrically connected to the negative electrode of the diode D through a via penetrating the second insulating layer 60, thereby being electrically connected to the peripheral trace 12. In this way, the depth of the via is small, which reduces the difficulty of via fabrication and improves the connection yield between the second electrode plate 71 and the peripheral trace 12.

[0037] In one embodiment, the metal layer 70 is a gate metal layer, which is patterned within the display area AA to form the gate of a thin-film transistor and / or gate traces. In another embodiment, the metal layer 70 is a source-drain metal layer, which is patterned within the display area AA to form the source-drain of a thin-film transistor and / or signal traces such as data lines. In other embodiments, the metal layer 70 may also be other conductive film layers in the display panel besides the gate metal layer and the source-drain metal layer. With a fixed relative area between the first electrode plate and the second electrode plate 71, the greater the distance between the metal layer 70 and the source-drain metal layer 50, the larger the capacitance of the capacitor C. The metal layer 70 can be designed according to the actual capacitance requirements.

[0038] In another embodiment, please refer to Figure 6 , Figure 6 A schematic diagram of a third structure of a display panel provided in an embodiment of the present invention is shown. For example... Figure 6 As shown, the display panel includes a substrate 20, a shielding layer 10, an active layer 50, a gate metal layer 70, and source / drain metal layers 90. The shielding layer 10 is disposed between the substrate 20 and the active layer 50, and is patterned to form in-plane traces 11 and peripheral traces 12, which are not in contact. The active layer 50 is disposed between the shielding layer 10 and the metal layer 70, and is patterned to form a diode D. The diode D includes a P-type region and an N-type region, which are in contact. The P-type region is the positive electrode of the diode D. The N-type region is the negative electrode of the diode D; the gate metal layer 70 is disposed between the active layer 50 and the source / drain metal layer 90, and the gate metal layer 70 is patterned to form the second electrode plate 71 of the capacitor C; the source / drain metal layer 90 is patterned to form the first electrode plate 91 of the capacitor C; the positive electrode of the diode D is electrically connected to the first electrode plate 91 and the in-plane trace 11, and the negative electrode of the diode D is electrically connected to the second electrode plate 71 and the peripheral trace 12. The display panel also includes a buffer layer 30, a first insulating layer 40, a second insulating layer 60, and a third insulating layer 80. The buffer layer 30 is disposed between the substrate 20 and the shielding layer 10, the first insulating layer 40 is disposed between the shielding layer 10 and the active layer 50, the second insulating layer 60 is disposed between the active layer 50 and the gate metal layer 70, and the third insulating layer 80 is disposed between the gate metal layer 70 and the source / drain metal layer 90. The positive terminal of diode D is electrically connected to the in-plane trace 11 through a via penetrating the first insulating layer 40, and the negative terminal of diode D is electrically connected to the peripheral trace 12 through a via penetrating the first insulating layer 40. Similarly, the second electrode plate 71 can be electrically connected to the negative terminal of diode D through a via penetrating the second insulating layer 60, or to the peripheral trace 12 through a via penetrating the second insulating layer 60 and the first insulating layer 40; the first electrode plate 91 can be electrically connected to the positive terminal of diode D through a via penetrating the second insulating layer 60 and the third insulating layer 80, or to the in-plane trace 11 through a via penetrating the first insulating layer 40, the second insulating layer 60, and the third insulating layer 80.

[0039] In summary, the present invention provides a display panel that, by adding an electrostatic discharge (ESD) protection circuit between the in-plane traces and the peripheral traces, protects the connection between the peripheral traces and the in-plane traces from ESD, thus avoiding the problem of ESD damage to the display panel caused by instantaneous high current.

[0040] The display panel provided in the embodiments of the present invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area. It comprises a shielding structure and thin-film transistors (TFTs). The shielding structure includes a shielding portion and in-plane traces located within the display area, and peripheral traces located within the non-display area. The shielding portion is positioned below the TFTs, and the projection of the TFT channel onto the shielding portion falls within the shielding portion. The shielding portion is electrically connected to the in-plane traces. At least one of the in-plane traces is electrically connected to the peripheral traces via an electrostatic discharge protection circuit; The electrostatic discharge protection circuit includes a diode and a capacitor, the diode and the capacitor are connected in parallel, the anode of the diode is connected to the in-plane trace, and the cathode of the diode is connected to the peripheral trace. The display panel includes an active layer, which includes the channel and the diode, and the diode and the first electrode plate of the capacitor have the same structure; The in-plane traces are in a grid pattern; the diode includes a P-type region and an N-type region formed in the active layer; the P-type region is electrically connected to the in-plane traces, and the N-type region is electrically connected to the peripheral traces; the display panel also includes a metal layer, which includes the second electrode plate of the capacitor.

2. The display panel as described in claim 1, characterized in that, The display panel further includes a substrate, and the active layer is disposed between the substrate and the metal layer.

3. The display panel as described in claim 2, characterized in that, The first electrode plate is electrically connected to the positive terminal of the diode.

4. The display panel as described in claim 2, characterized in that, The second electrode plate is electrically connected to the peripheral wiring through a via.

5. The display panel as described in claim 2, characterized in that, The second electrode plate is electrically connected to the negative electrode of the diode through a via.

6. The display panel as described in claim 2, characterized in that, The metal layer is either a gate metal layer or a source / drain metal layer.

7. The display panel as described in claim 1, characterized in that, The display panel further includes a substrate, a gate metal layer, and a source / drain metal layer. The active layer is disposed between the substrate and the gate metal layer, and the gate metal layer is disposed between the active layer and the source / drain metal layer. The gate metal layer includes a first electrode plate of the capacitor, and the source / drain metal layer includes a second electrode plate of the capacitor.

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