Storage device and method for manufacturing the same

Abstract

A memory device and a method for manufacturing the memory device are provided. The memory device includes: a peripheral circuit arranged on a substrate; and a gate stack structure overlapping the peripheral circuit. The gate stack structure includes: a plurality of first unit plugs having a substantially cylindrical structure; and a plurality of second unit plugs having a substantially hexagonal prism structure.

Description

Technical Field

[0001] The present disclosure generally relates to a storage device and a method for manufacturing the storage device, and more particularly, to a three-dimensional storage device and a method for manufacturing the three-dimensional storage device. Background Art

[0002] Recently, the paradigm of computer environment has shifted to a ubiquitous computing environment where computing systems can be used anywhere, anytime. This has promoted the increase in the use of portable electronic devices (such as mobile phones, digital cameras, notebook computers, etc.). Such portable electronic devices may generally include a storage system using a storage device (i.e., a data storage device). The data storage device is used as a primary storage device or a secondary storage device of the portable electronic device.

[0003] The data storage device using the storage device has excellent stability and durability, high information access speed and low power consumption due to the absence of a mechanical drive part. In an embodiment of a storage system having such advantages, the data storage device includes a universal serial bus (USB) storage device, a memory card with various interfaces, a solid state drive (SSD), etc.

[0004] Storage devices are generally classified into volatile storage devices and nonvolatile storage devices.

[0005] A nonvolatile memory device has a relatively slow writing and reading speed, but can retain stored data even when the power supply is interrupted. Therefore, a nonvolatile memory device is used to store data to be retained regardless of whether the power is supplied. Examples of nonvolatile memories include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is divided into NOR-type flash memory and NAND-type flash memory.

[0006] As the improvement of the integration degree of a semiconductor device in which memory cells are formed in a single layer on a substrate reaches a limit, a three-dimensional nonvolatile memory device in which memory cells are vertically stacked on a substrate has recently been proposed.

[0007] A three-dimensional non-volatile memory device includes: interlayer insulating layers and gate electrodes alternately stacked; and a channel layer penetrating the interlayer insulating layers and the gate electrodes; and memory cells are stacked along the channel layer. In order to improve the operational reliability of such a non-volatile memory device having a three-dimensional structure and to increase manufacturing yield, various structures and manufacturing methods have been developed. Summary of the invention

[0008] According to one aspect of the present disclosure, a storage device may be provided, comprising: a peripheral circuit arranged on a substrate; and a gate stack structure overlapping the peripheral circuit, wherein the gate stack structure comprises: a plurality of first unit plugs having a roughly cylindrical structure; and a plurality of second unit plugs having a roughly hexagonal prism structure.

[0009] According to another aspect of the present disclosure, a method for manufacturing a storage device can be provided, the method comprising the following steps: forming a stacked structure in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked; forming a plurality of first unit plugs penetrating the stacked structure; forming a first contact plug pattern on top of the plurality of first unit plugs; opening an upper portion of the stacked structure in an area where a plurality of second unit plugs are to be formed by forming a hard mask pattern on a side wall of the first contact plug pattern; forming holes penetrating the stacked structure by performing an etching process using the hard mask pattern and the first contact plug pattern; removing the plurality of sacrificial layers exposed through the holes, and forming a plurality of plate electrodes by filling a conductive layer in the space from which the plurality of sacrificial layers are removed; and forming the plurality of second unit plugs in the holes.

[0010] According to another aspect of the present disclosure, a method for manufacturing a storage device can be provided, the method comprising the following steps: forming a stacked structure in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked; forming a plurality of first unit plugs penetrating the stacked structure, wherein six first unit plugs among the plurality of first unit plugs are formed approximately along a circle to be spaced apart from each other at a certain distance; forming a first contact plug pattern on top of the plurality of first unit plugs; defining an area by forming a hard mask pattern on the sidewall of the first contact plug pattern, in which an upper portion of the stacked structure is opened in a substantially hexagonal shape in a central area of ​​the circle; forming a plurality of holes having a substantially hexagonal prism shape by etching the stacked structure in the opened area, the plurality of holes penetrating the stacked structure; forming a plurality of plate electrodes by removing the plurality of sacrificial layers exposed through the plurality of holes and filling a conductive layer in the space from which the plurality of sacrificial layers are removed; and forming a plurality of second unit plugs in the plurality of holes.

[0011] According to another aspect of the present disclosure, a storage device may be provided, comprising: a peripheral circuit arranged on a substrate; and a first gate stack structure and a second gate stack structure overlapping the peripheral circuit, wherein each of the first gate stack structure and the second gate stack structure comprises a plurality of first unit plugs having a substantially cylindrical structure and a plurality of second unit plugs having a substantially hexagonal prism structure, and wherein an isolation region between the first gate stack structure and the second gate stack structure has a plurality of interlayer insulating layers and a plurality of sacrificial layers, and the plurality of interlayer insulating layers and the plurality of sacrificial layers are alternately stacked in the isolation region.

[0012] According to another aspect of the present disclosure, a method for manufacturing a storage device may be provided, the method comprising: forming a stacked structure on a substrate region, the substrate region comprising a first gate stacked structure region and a second gate stacked structure region, wherein the stacked structure comprises a plurality of sacrificial layers and a plurality of interlayer insulating layers, the plurality of sacrificial layers and the plurality of interlayer insulating layers being alternately stacked; forming a plurality of first unit plugs penetrating the stacked structure in the first gate stacked structure region and the second gate stacked structure region, wherein six first unit plugs of the plurality of first unit plugs are formed approximately along a circle to be spaced apart from each other at a certain distance; forming a first contact plug pattern on top of the plurality of first unit plugs; and forming a hard plug pattern on the sidewalls of the first contact plug pattern. A mask pattern defines an area in which the upper portion of the stacked structure is opened in a roughly hexagonal shape in the central area of ​​the circle; a plurality of holes having a roughly hexagonal prism shape are formed by etching the stacked structure in the opened area, the plurality of holes penetrating the stacked structure; the plurality of sacrificial layers exposed through the plurality of holes are removed, wherein the plurality of sacrificial layers remain in a boundary area between the first gate stacked structure area and the second gate stacked structure area; a plurality of plate electrodes are formed by filling a conductive layer in the space in the first gate stacked structure area where the plurality of sacrificial layers are removed and in the space in the second gate stacked structure area where the plurality of sacrificial layers are removed; and a plurality of second unit plugs are formed in the plurality of holes. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Examples of embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments described herein.

[0014] In the drawings, dimensions may be exaggerated for clarity of illustration. It is understood that when an element is referred to as being between two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. Similar reference numerals refer to similar elements throughout the text.

[0015] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0016] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure.

[0017] Figure 3 and Figure 4 is a perspective view showing a storage device according to an embodiment of the present disclosure.

[0018] Figure 5A and Figure 5B are a plan view and a cross-sectional view showing a gate stack structure according to an embodiment of the present disclosure.

[0019] Fig. 6A , Figure 6B , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig. 9 and Fig.10 is a view showing a process of forming a gate stack structure according to an embodiment of the present disclosure.

[0020] Fig.11 It is shown Fig.10 A horizontal cross-sectional view of the second unit plug shown in FIG.

[0021] Fig.12 is a cross-sectional view showing a gate stack structure according to another embodiment of the present disclosure.

[0022] Fig.13A , Fig. 13B , Fig.14 , Fig.15A , Fig. 15B and Fig.16 is a view showing a process of forming a gate stack structure according to another embodiment of the present disclosure.

[0023] Fig.17 is a block diagram showing a configuration of a storage system according to an embodiment of the present disclosure.

[0024] Fig.18 is a block diagram showing a configuration of a storage system according to an embodiment of the present disclosure.

[0025] Fig.19 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure.

[0026] Fig. 20 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Hereinafter, examples of embodiments of the present disclosure will be described. In the figures, thickness and distance are indicated for ease of description and may be shown enlarged compared to actual physical thickness and distance. In this specification, known structures not related to the present disclosure may be omitted. In this specification, when reference numerals are assigned to components in the figures, it should be noted that even if similar elements are drawn in several figures, these similar elements are represented by similar reference numerals.

[0028] The present embodiment provides a memory device having a simple manufacturing process, a stable structure, and improved integration, and provides a method for manufacturing the memory device.

[0029] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0030] Reference Figure 1 , the memory device 10 may include a peripheral circuit PC and a memory cell array 20 .

[0031] The peripheral circuit PC may be configured to control a program operation for storing data in the memory cell array 20 , a read operation for outputting data stored in the memory cell array 20 , and an erase operation for erasing data stored in the memory cell array 20 .

[0032] In an embodiment, the peripheral circuit PC may include a voltage generator 31, a row decoder 33, a control logic 35, and a page buffer group 37. The control logic 35 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 35 may be a control logic circuit operating according to an algorithm and / or a processor executing a control logic code.

[0033] The memory cell array 20 may include a plurality of memory blocks, and each memory block may include a plurality of memory cells in which data is stored. The memory cells may be arranged three-dimensionally.

[0034] The memory cell array 20 may be connected to the row decoder 33 through word lines WL, and connected to the page buffer group 37 through bit lines BL.

[0035] The control logic 35 may control the peripheral circuit PC in response to the command CMD and the address ADD.

[0036] The voltage generator 31 may generate various operating voltages for program operations, read operations, and erase operations under the control of the control logic 35. The operating voltages may include a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, and the like.

[0037] The row decoder 33 may provide the operating voltage generated by the voltage generator to the memory cell array 20 under the control of the control logic 35. For example, the row decoder 33 may provide the operating voltage generated by the voltage generator 31 to at least one selected memory block among a plurality of memory blocks included in the memory cell array 20.

[0038] The page buffer group 37 may be connected to the memory cell array 20 via the bit line BL. The page buffer group 37 may temporarily store data received from an input / output circuit (not shown) in a program operation under the control of the control logic 35, and control the potential of the bit line BL based on the temporarily stored data. The page buffer group 37 may sense the voltage or current of the bit line BL in a read operation or a verification operation under the control of the control logic 35.

[0039] From a structural point of view, the memory cell array 20 may be arranged on the peripheral circuit PC. The memory cell array 20 may overlap a portion of the peripheral circuit PC.

[0040] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure.

[0041] Reference Figure 2 , the memory cell array 20 may include a plurality of cell strings CS1 and CS2 connected between a source line SL and a plurality of bit lines BL. The plurality of cell strings CS1 and CS2 may be commonly connected to a plurality of word lines WL1 to WLn.

[0042] "N" can be an integer greater than 1.

[0043] Each of the plurality of cell strings CS1 and CS2 may include: at least one source select transistor SST connected to a source line SL; at least one drain select transistor DST connected to a bit line BL; and a plurality of memory cells MC1 to MCn connected in series between the source select transistor SST and the drain select transistor DST.

[0044] Gates of the plurality of memory cells MC1 to MCn may be respectively connected to a plurality of word lines WL1 to WLn stacked to be spaced apart from each other. Two or more drain selection lines DSL1 and DSL2 may be spaced apart from each other at the same height.

[0045] A gate of the source select transistor SST may be connected to a source select line SSL. A gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST.

[0046] The source line SL may be connected to the source of the source selection transistor SST. The drain of the drain selection transistor DST may be connected to a bit line corresponding to the drain of the drain selection transistor DST.

[0047] A plurality of cell strings CS1 and CS2 may be divided into string groups connected to two or more drain selection lines DSL1 and DSL2, respectively. Cell strings connected to the same word line and the same bit line may be independently controlled by different drain selection lines. In addition, cell strings connected to the same drain selection line may be independently controlled by different bit lines.

[0048] In an embodiment, the two or more drain selection lines DSL1 and DSL2 may include a first drain selection line DSL1 and a second drain selection line DSL2. The plurality of cell strings CS1 and CS2 may include: a first cell string CS1 of a first cell string group connected to the first drain selection line DSL1; and a second cell string CS2 of a second string group connected to the second drain selection line DSL2.

[0049] Figure 3 and Figure 4 is a perspective view showing a storage device according to an embodiment of the present disclosure.

[0050] Reference Figure 3 and Figure 4 , each of the memory devices 10A and 10B may include: a peripheral circuit PC disposed on a substrate SUB; and a gate stack structure GST overlapping with the peripheral circuit PC.

[0051] Each of the gate stack structures GST may include a source select line SSL, a plurality of word lines WL1 to WLn, and two or more drain select lines DSL1 and DSL2 which are isolated from each other at the same height by a first slit S1 .

[0052] The source selection line SSL and the plurality of word lines WL1 to WLn may form a plate shape extending in a first direction X and a second direction Y and parallel to the top surface of the substrate SUB. The first direction X may be a direction facing an X-axis in an XYZ coordinate system, and the second direction Y may be a direction facing a Y-axis in the XYZ coordinate system.

[0053] The plurality of word lines WL1 to WLn may be stacked to be spaced apart from each other in a third direction Z. The third direction Z may be a direction faced by a Z axis in an XYZ coordinate system. The plurality of word lines WL1 to WLn may be arranged between two or more drain selection lines DSL1 and DSL2 and a source selection line SSL.

[0054] The gate stack structures GST may be isolated from each other by the second slits S2 . The first slits S1 may be formed to be shorter than the second slits S2 in the third direction Z and overlap the plurality of word lines WL1 to WLn.

[0055] Each of the first slit S1 and the second slit S2 may extend in a linear shape, extend in a zigzag shape, or extend in a wavy shape. The width of each of the first slit S1 and the second slit S2 may be variously changed according to a design rule.

[0056] Reference Figure 3 According to an embodiment, the source select line SSL may be arranged closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL2.

[0057] The memory device 10A may include a source line SL disposed between the gate stack structure GST and the peripheral circuit PC, and a plurality of bit lines BL spaced farther apart from the peripheral circuit PC than the source line SL. The gate stack structure GST may be disposed between the source line SL and the plurality of bit lines BL.

[0058] Reference Figure 4 According to an embodiment, two or more drain select lines DSL1 and DSL2 may be arranged closer to the peripheral circuit PC than the source select line SSL.

[0059] The memory device 10B may include a plurality of bit lines BL disposed between the gate stack structure GST and the peripheral circuit PC, and a source line SL spaced farther from the peripheral circuit PC than the plurality of bit lines BL. The gate stack structure GST may be disposed between the source line SL and the plurality of bit lines BL.

[0060] Figure 5A and Figure 5B are a plan view and a cross-sectional view showing a gate stack structure according to an embodiment of the present disclosure.

[0061] Reference Figure 5A , the gate stack structure may include a plurality of first cell plugs CP1 and a plurality of second cell plugs CP2 arranged between the second slits S2. For example, the plurality of first cell plugs CP1 may be arranged to surround the periphery of one second cell plug CP2. For example, six first cell plugs CP1 may be arranged to be spaced apart from each other at a certain distance at the periphery of one second cell plug CP2. Figure 5A , six first unit plugs CP1 are arranged around one second unit plug CP2, but the present disclosure is not limited thereto, and at least four first unit plugs CP1 may be arranged around one second unit plug CP2. The first unit plug CP1 may have a cylindrical shape, and the second unit plug CP2 may have a hexagonal prism structure.

[0062] Figure 5B is along Figure 5A A cross-sectional view of the gate stack structure taken along line AA′ shown in FIG.

[0063] Reference Figure 5B The gate stack structure may include: a stack structure ST in which a plurality of plate electrodes 41 and a plurality of interlayer insulating layers 12 are alternately stacked; and a first cell plug CP1 and a second cell plug CP2 which penetrate the stack structure ST.

[0064] The first cell plug CP1 may include: a core insulating layer 23 vertically extending in a stacking direction of the stack structure ST; a channel layer 22 surrounding the core insulating layer 23 ; and a memory layer 21 surrounding the channel layer 22 .

[0065] The core insulating layer 23 may extend from the central region of the first cell plug CP1 in the vertical direction and be formed as an insulating layer such as an oxide layer. The channel layer 22 may be used as a channel region of the cell string. The channel layer 22 may include a semiconductor layer. In an embodiment, the channel layer 22 may include silicon. The storage layer 21 may store data. The storage layer 21 may be formed as a multilayer and include, for example, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. The tunnel insulating layer may surround the sidewalls of the channel layer 22. The tunnel insulating layer may be formed as a silicon oxide layer through which charges may tunnel. The charge storage layer may surround the sidewalls of the tunnel insulating layer. The charge storage layer may be formed as a material layer capable of storing data that varies using the Fowler-Nordheim tunneling technique. In an embodiment, the charge storage layer may be formed as a charge trapping nitride layer. The blocking insulating layer may surround the sidewalls of the charge storage layer. The blocking insulating layer may include an oxide layer capable of blocking charges.

[0066] A first contact plug pattern 24 may be formed on the top of the first cell plug CP1 .

[0067] One second cell plug CP2 may be disposed between two first cell plugs CP1 The second cell plug CP2 may include: a core insulating layer 53 vertically extending in the stacking direction of the stack structure ST; a channel layer 52 surrounding the core insulating layer 53; and a memory layer 51 surrounding the channel layer 52.

[0068] The core insulating layer 53 may extend from the central region of the second cell plug CP2 in the vertical direction and be formed as an insulating layer such as an oxide layer. The channel layer 52 may be used as a channel region of the cell string. The channel layer 52 may include a semiconductor layer. In an embodiment, the channel layer 52 may include silicon. The storage layer 51 may store data. The storage layer 51 may be formed as a multilayer and include, for example, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. The tunnel insulating layer may surround the sidewalls of the channel layer 52. The tunnel insulating layer may be formed as a silicon oxide layer through which charges may tunnel. The charge storage layer may surround the sidewalls of the tunnel insulating layer. The charge storage layer may be formed as a material layer capable of storing data that varies using the Fowler-Nordheim tunneling technique. In an embodiment, the charge storage layer may be formed as a charge trapping nitride layer. The blocking insulating layer may surround the sidewalls of the charge storage layer. The blocking insulating layer may include an oxide layer capable of blocking charges.

[0069] A second contact plug pattern 61 may be formed on the top of the second cell plug CP2 .

[0070] Fig. 6A , Figure 6B , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig. 9 and Fig.10 is a view showing a process of forming a gate stack structure according to an embodiment of the present disclosure.

[0071] Reference Fig. 6A and Figure 6B , a stacked structure ST in which sacrificial layers 11 and interlayer insulating layers 12 are alternately stacked may be formed. The stacked structure ST may be formed on a substrate (not shown) including a peripheral circuit.

[0072] The sacrificial layer 11 may be formed of a material different from that of the interlayer insulating layer 12. For example, the interlayer insulating layer 12 may be formed of an oxide such as silicon oxide. The sacrificial layer 11 may be formed of a material having an etching rate different from that of the interlayer insulating layer 12. For example, the sacrificial layer 11 may be formed of a nitride such as silicon nitride.

[0073] Subsequently, a first hard mask pattern 13 in which a region OP1 where a first cell plug is to be formed is opened is formed on the stack structure ST.

[0074] For example, in the first hard mask pattern 13, the regions OP1 where six first cell plugs are to be formed may be arranged along a circle. The regions OP1 where six first cell plugs are to be formed may be formed to be spaced apart from each other by a certain distance.

[0075] Reference Figure 7 , a plurality of first holes H1 penetrating the stack structure ST are formed by performing an etching process using the first hard mask pattern 13. Subsequently, a first cell plug CP1 is formed in the first hole H1. The first cell plug CP1 may be formed by sequentially stacking a memory layer 21, a channel layer 22, and a core insulating layer 23 on the sidewall of the first hole H1.

[0076] The storage layer 21 may be formed as a multilayer. For example, the storage layer 21 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer. The blocking insulating layer may be formed on the sidewalls of the first hole H1. The blocking insulating layer may include an oxide layer capable of blocking charges. In an embodiment, the blocking insulating layer may be formed of Al2O3. The charge storage layer may be formed on the sidewalls of the blocking insulating layer. The charge storage layer may be formed as a charge capture layer, may be formed as a material layer including conductive nanodots, or may be formed as a phase change material layer. For example, the charge storage layer may store data changed using Fowler-Nordheim tunneling technology. To this end, the charge storage layer may be formed as a silicon nitride layer in which charges may be captured. The tunnel insulating layer may be formed on the sidewalls of the charge storage layer. The tunnel insulating layer may be formed as a silicon oxide layer through which charges may tunnel.

[0077] The channel layer 22 may include a semiconductor layer. In an implementation, the channel layer 22 may include silicon.

[0078] The core insulating layer 23 may be formed by filling the central region of the first hole H1. The core insulating layer may be formed as an oxide layer.

[0079] Reference Fig. 8A and Figure 8B For example, the upper portion of the first cell plug CP1 may be etched to a certain thickness so that the upper surface of the first cell plug CP1 is higher than the upper surface of the sacrificial layer 11 at the uppermost portion and lower than the upper surface of the interlayer insulating layer 12 at the uppermost portion.

[0080] Subsequently, a first contact plug pattern 24 may be formed in a space where the first cell plug CP1 is etched and removed. In an implementation, the first contact plug pattern 24 may be formed as a doped semiconductor layer.

[0081] Subsequently, the first hard mask pattern is removed. Therefore, the first contact plug pattern 24 protrudes further than the stack structure ST. Subsequently, the second hard mask pattern 31 is formed on the sidewall of the protruding first contact plug pattern 24.

[0082] A method of forming the second hard mask pattern 31 will be described below.

[0083] A hard mask layer is formed on the entire structure including the protruding first contact plug pattern 24. Subsequently, a second hard mask pattern 31 is formed on the sidewalls of the protruding first contact plug pattern 24 by completely etching the hard mask layer. As a result of the entire etching process, the hard mask layer remains on the sidewalls of the protruding first contact plug pattern 24, and thus, the upper surface of the first contact plug pattern 24 and the portion of the stacked structure ST between the first cell plugs CP1 are exposed. That is, the region OP2 where the second cell plug is to be formed is open between the first cell plugs CP1. Figure 8B As shown in FIG. 1 , the region OP2 where the second cell plugs are to be formed may be defined in a hexagonal shape. That is, an open region having a hexagonal shape is defined in the central region of the six first cell plugs CP1 arranged in a circular shape.

[0084] Figure 8C is along Figure 8B A cross-sectional view of the gate stack structure taken along line BB′ shown in FIG.

[0085] Reference Figure 8B and Figure 8C , when the distance between the first cell plugs CP1 adjacent to each other is less than 2 times the lateral thickness of the second hard mask pattern 31, the upper portion of the stacked structure ST between the first cell plugs CP1 adjacent to each other is not open due to the second hard mask pattern 31. That is, the spaces between the first contact plug patterns 24 respectively formed on the tops of the first cell plugs CP1 adjacent to each other are filled with the second hard mask pattern 31, and therefore, the upper portion of the stacked structure ST between the first cell plugs CP1 is covered by the second hard mask pattern 31.

[0086] Reference Fig. 9 , a second hole H2 penetrating the stack structure ST is formed by performing an etching process using the second hard mask pattern 31 and the first contact plug pattern 24 as an etching mask. That is, the second hole H2 is formed by etching the stack structure ST in the region where the second cell plug is to be formed. The sidewall of the sacrificial layer is exposed by the second hole H2.

[0087] The sacrificial layer exposed through the second hole H2 is removed. Subsequently, the plate electrode 41 is formed by filling a conductive material in the space where the sacrificial layer is removed.

[0088] Reference Fig.10 , a second cell plug CP2 is formed in the second hole H2. The second cell plug CP2 may be formed by sequentially stacking a memory layer 51, a channel layer 52, and a core insulating layer 53 on a sidewall of the second hole H2.

[0089] The storage layer 51 may be formed as a multilayer. For example, the storage layer 51 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer. The blocking insulating layer may be formed on the sidewalls of the second hole H2. The blocking insulating layer may include an oxide layer capable of blocking charges. In an embodiment, the blocking insulating layer may be formed of Al5O3. The charge storage layer may be formed on the sidewalls of the blocking insulating layer. The charge storage layer may be formed as a charge capture layer, may be formed as a material layer including conductive nanodots, or may be formed as a phase change material layer. For example, the charge storage layer may store data changed using Fowler-Nordheim tunneling technology. To this end, the charge storage layer may be formed as a silicon nitride layer in which charges may be captured. The tunnel insulating layer may be formed on the sidewalls of the charge storage layer. The tunnel insulating layer may be formed as a silicon oxide layer through which charges may tunnel.

[0090] The channel layer 52 may include a semiconductor layer. In an implementation, the channel layer 52 may include silicon.

[0091] The core insulating layer 53 may be formed by filling the central region of the second hole H2. The core insulating layer 53 may be formed as an oxide layer.

[0092] The memory layer 51 , the channel layer 52 , and the core insulating layer 53 constituting the second cell plug CP2 may be formed as the same layers as the memory layer 21 , the channel layer 22 , and the core insulating layer 23 constituting the first cell plug CP1 .

[0093] Subsequently, the second hard mask pattern may be removed. When the second hard mask pattern is formed of a non-conductive material, a process of removing the second hard mask pattern may be skipped.

[0094] Fig.11 It is shown Fig.10 A horizontal cross-sectional view of the second unit plug shown in FIG.

[0095] Reference Fig.11 The second cell plug CP2 may include a storage layer 51, a channel layer 52 and a core insulating layer 53, which are sequentially formed on Fig. 9 On the surface of the second hole H2 shown in FIG. And the memory layer 51 may include a blocking insulating layer 51A, a charge storage layer 51B and a tunnel insulating layer 51C.

[0096] according to Figure 8B The second hole H2 is formed in a hexagonal prism shape in the open area of ​​the second hard mask pattern 31 shown in FIG. 1 , and thus, the second cell plug CP2 formed in the second hole H2 is formed in a hexagonal prism shape.

[0097] In the formation process of the blocking insulating layer 51A formed on the sidewall of the second hole H2 having the hexagonal prism shape, a nitride layer is deposited on the sidewall of the second hole H2 having the hexagonal prism shape, and the nitride layer is replaced with an oxide layer through an oxidation process to form the blocking insulating layer 51A. The outer wall of the blocking insulating layer 51A in contact with the sidewall of the second hole H2 is formed in the hexagonal prism shape, but the inner wall of the blocking insulating layer 51A in contact with the charge storage layer 51B may be formed in a cylindrical shape in a subsequent process.

[0098] Subsequently, the storage layer 51 is formed by sequentially depositing a charge storage layer 51B and a tunnel insulating layer 51C on the inner wall of the blocking insulating layer 51A, a channel layer 52 is formed on the sidewall of the tunnel insulating layer 51, and a central area of ​​the second hole H2 is filled with the core insulating layer 53. Therefore, the horizontal cross-section of the blocking insulating layer 51A may be formed in a hexagonal shape, and the horizontal cross-section of each of the charge storage layer 51B, the tunnel insulating layer 51C, the channel layer 52, and the core insulating layer 53 may be formed in a circular shape.

[0099] As described above, according to an embodiment of the present disclosure, after forming the first cell plugs CP1, the second holes H2 for removing the sacrificial layer 11 are formed in the spaces between the first cell plugs CP1. Subsequently, after removing the sacrificial layer 11 through the second holes H2, the second cell plugs CP2 are formed in the second holes H2.

[0100] Fig.12 is a cross-sectional view showing a gate stack structure according to another embodiment of the present disclosure.

[0101] Reference Fig.12 , the first gate stack structure GST1 and the second gate stack structure GST2 may be arranged adjacent to each other. The space between the first gate stack structure GST1 and the second gate stack structure GST2 may be defined as an isolation region ISO, and the plate electrode of the first gate stack structure GST1 and the plate electrode of the second gate stack structure GST2 may be electrically isolated from each other by means of the isolation region ISO.

[0102] The first gate stack structure GST1 and the second gate stack structure GST2 may include a plurality of first cell plugs CP1 and a plurality of second cell plugs CP2. For example, the plurality of first cell plugs CP1 may be arranged to surround the periphery of one second cell plug CP2. For example, six first cell plugs CP1 may be arranged to be spaced apart from each other at a certain distance at the periphery of one second cell plug CP2. Fig.12, the case where six first cell plugs CP1 are arranged on the periphery of one second cell plug CP2 is shown, but the present disclosure is not limited thereto, and at least four first cell plugs CP1 may be arranged on the periphery of one second cell plug CP2. The first cell plug CP1 may have a cylindrical structure, and the second cell plug CP2 may have a hexagonal prism structure. The first cell plugs adjacent to each other in the first cell plugs CP1 included in the first gate stack structure GST1 may be arranged to be spaced apart from each other by a first distance d1, and the first cell plugs adjacent to each other in the first cell plugs CP1 included in the second gate stack structure GST2 may be arranged to be spaced apart from each other by a first distance d1. In addition, the first cell plugs adjacent to the second gate stack structure GST2 in the first cell plug CP1 included in the first gate stack structure GST1 and the first cell plugs adjacent to the first gate stack structure GST1 in the first cell plug CP1 included in the second gate stack structure GST2 may be arranged to be spaced apart from each other by a second distance d2. The second distance d2 may be longer than the first distance d1.

[0103] The plurality of first cell plugs CP1 and the plurality of second cell plugs CP2 included in each of the first gate stack structure GST1 and the second gate stack structure GST2 may have the same Figure 5B The gate stack structures are the same as those shown in FIG.

[0104] Fig.13A , Fig. 13B , Fig.14 , Fig.15A , Fig. 15B and Fig.16 is a view showing a process of forming a gate stack structure according to another embodiment of the present disclosure.

[0105] Fig.13A is along Fig.12 FIG. 1 is a cross-sectional view of the stacked structure cut along line CC′ shown in FIG. The line CC′ may be a boundary region between the first gate stacked structure GST1 and the second gate stacked structure GST2 .

[0106] Reference Fig.13A and Fig. 13B , a stacked structure ST in which sacrificial layers 11 and interlayer insulating layers 12 are alternately stacked may be formed. The stacked structure ST may be formed on a substrate (not shown) including a peripheral circuit.

[0107] The sacrificial layer 11 may be formed of a material different from that of the interlayer insulating layer 12. For example, the interlayer insulating layer 12 may be formed of an oxide such as silicon oxide. The sacrificial layer 11 may be formed of a material having an etching rate different from that of the interlayer insulating layer 12. For example, the sacrificial layer 11 may be formed of a nitride such as silicon nitride.

[0108] Subsequently, a first hard mask pattern 13 in which a region OP1 where a first cell plug is to be formed is opened is formed on the stack structure ST.

[0109] For example, in the first hard mask pattern 13, the regions OP1 where six first cell plugs are to be formed may be arranged along a circle. The regions OP1 where six first cell plugs are to be formed may be formed to be spaced apart from each other by a certain distance.

[0110] like Fig. 13B As shown in , the region OP1 to be formed of the first cell plug formed on the first gate stack structure GST1 may be arranged to be spaced apart from each other by the first distance d1, and the region OP1 to be formed of the first cell plug formed on the second gate stack structure GST2 may be arranged to be spaced apart from each other by the first distance d1. In addition, the region OP1 to be formed of the first cell plug adjacent to the second gate stack structure GST2 among the regions OP1 to be formed of the first cell plug on the first gate stack structure GST1 and the region OP1 to be formed of the first cell plug adjacent to the first gate stack structure GST1 among the regions OP1 to be formed of the first cell plug on the second gate stack structure GST2 may be arranged to be spaced apart from each other by the second distance d2. The second distance d2 may be longer than the first distance d1.

[0111] Reference Fig.14 , a plurality of first holes H1 penetrating the stack structure ST are formed by performing an etching process using the first hard mask pattern 13. Subsequently, a first cell plug CP1 is formed in the first hole H1. The first cell plug CP1 may be formed by sequentially stacking a memory layer 21, a channel layer 22, and a core insulating layer 23 on the sidewall of the first hole H1.

[0112] The storage layer 21 may be formed as a multilayer. For example, the storage layer 21 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer. The blocking insulating layer may be formed on the sidewalls of the first hole H1. The blocking insulating layer may include an oxide layer capable of blocking charges. In an embodiment, the blocking insulating layer may be formed of Al2O3. The charge storage layer may be formed on the sidewalls of the blocking insulating layer. The charge storage layer may be formed as a charge capture layer, may be formed as a material layer including conductive nanodots, or may be formed as a phase change material layer. For example, the charge storage layer may store data changed using Fowler-Nordheim tunneling technology. To this end, the charge storage layer may be formed as a silicon nitride layer in which charges may be captured. The tunnel insulating layer may be formed on the sidewalls of the charge storage layer. The tunnel insulating layer may be formed as a silicon oxide layer through which charges may tunnel.

[0113] The channel layer 22 may include a semiconductor layer. In an implementation, the channel layer 22 may include silicon.

[0114] The core insulating layer 23 may be formed by filling the central region of the first hole H1. The core insulating layer may be formed as an oxide layer.

[0115] Reference Fig.15A and Fig. 15B For example, the upper portion of the first cell plug CP1 may be etched to a certain thickness so that the upper surface of the first cell plug CP1 is higher than the upper surface of the sacrificial layer 11 at the uppermost portion and lower than the upper surface of the interlayer insulating layer 12 at the uppermost portion.

[0116] Subsequently, a first contact plug pattern 24 may be formed in a space where the first cell plug CP1 is etched and removed. In an implementation, the first contact plug pattern 24 may be formed as a doped semiconductor layer.

[0117] Subsequently, the first hard mask pattern is removed. Therefore, the first contact plug pattern 24 protrudes further than the stack structure ST. Subsequently, after forming a hard mask layer on the entire structure including the protruding first contact plug pattern 24, a protection pattern 32 is formed on the hard mask layer at the boundary region between the first gate stack structure GST1 and the second gate stack structure GST2. Subsequently, a second hard mask pattern 31 is formed by allowing the hard mask layer to remain on the sidewall of the first contact plug pattern 24 through an etching process. Therefore, etching of the boundary region between the first gate stack structure GST1 and the second gate stack structure GST2 is blocked by the protection pattern 32.

[0118] A method of forming the second hard mask pattern 31 will be described below.

[0119] A hard mask layer is formed on the entire structure including the protruding first contact plug pattern 24, and a protection pattern 32 is formed on the hard mask layer at the boundary region between the first gate stack structure GST1 and the second gate stack structure GST2. Subsequently, a second hard mask pattern 31 is formed on the sidewall of the protruding first contact plug pattern 24 by completely etching the hard mask layer. As a result of the entire etching process, the hard mask layer remains on the sidewall of the protruding first contact plug pattern 24, and thus, the upper surface of the first contact plug pattern 24 and the portion of the stack structure ST between the first cell plugs CP1 are exposed. That is, the region OP2 where the second cell plug is to be formed is open between the first cell plugs CP1. As shown in FIG. Fig. 15B As shown in FIG. 1 , the region OP2 where the second cell plugs are to be formed may be defined in a hexagonal shape. That is, an open region having a hexagonal shape is defined in the central region of the six first cell plugs CP1 arranged in a circular shape.

[0120] Subsequently, the protection pattern 32 may be removed.

[0121] Reference Fig.16 , a second hole H2 penetrating the stack structure ST is formed by performing an etching process using the second hard mask pattern 31 and the first contact plug pattern 24 as an etching mask. That is, the second hole H2 is formed by etching the stack structure ST in the region where the second cell plug is to be formed. The sidewall of the sacrificial layer is exposed by the second hole H2.

[0122] The sacrificial layer exposed through the second hole H2 is removed. By controlling conditions such as etching time in the etching process for removing the sacrificial layer, the sacrificial layer 11 formed in the boundary region between the first gate stack structure and the second gate stack structure is retained. That is, the sacrificial layer in the region of the first gate stack structure and the sacrificial layer in the region of the second gate stack structure are removed, while the sacrificial layer 11 in the boundary region between the first gate stack structure and the second gate stack structure is retained. The region between the first gate stack structure and the second gate stack structure may be defined as an isolation region ISO.

[0123] Subsequently, the plate electrode 41 is formed by filling a conductive material in the space where the sacrificial layer is removed. The plate electrodes 41 are electrically isolated from each other by the sacrificial layer 11 remaining in the boundary region between the first gate stack structure and the second gate stack structure.

[0124] Subsequently, as mentioned above Fig.10 As described above, the second cell plug CP2 may be formed in the second hole H2.

[0125] Fig.17 is a block diagram showing a configuration of a storage system according to an embodiment of the present disclosure.

[0126] Reference Fig.17 , a storage system 1000 according to an embodiment of the present disclosure includes a storage device 1200 and a controller 1100 .

[0127] The storage device 1200 is used to store data information in various data formats such as text, graphics, and software codes. The storage device 1200 may be a non-volatile memory, and according to the reference Fig. 6A , Figure 6B , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig. 9 and Fig.10 A method for manufacturing a storage device described herein or a reference Fig.13A , Fig. 13B , Fig.14 , Fig.15A , Fig. 15B and Fig.16 The structure and manufacturing method of the memory device 1200 are the same as those of the above-described memory device, and thus, a detailed description will be omitted.

[0128] The controller 1100 is connected to the host and the storage device 1200, and accesses the storage device 1200 in response to a request from the host. For example, the controller 1100 controls reading, writing, erasing, and background operations of the storage device 1200.

[0129] The controller 1100 includes a random access memory (RAM) 1110 , a central processing unit (CPU) 1120 , a host interface 1130 , an error correction code (ECC) circuit 1140 , a memory interface 1150 , and the like.

[0130] The RAM 1110 may be used as a working memory of the CPU 1120, a cache memory between the storage device 1200 and the host, and a buffer memory between the storage device 1200 and the host. The RAM 1110 may be replaced with a static random access memory (SRAM), a read only memory (ROM), or the like.

[0131] The CPU 1120 controls the overall operation of the controller 1100. For example, the CPU 1120 is configured to operate firmware such as a flash translation layer (FTL) stored in the RAM 1110.

[0132] The host interface 1130 is configured to interface with a host. For example, the controller 1100 communicates with the host using at least one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a dedicated protocol.

[0133] The ECC circuit 1140 is configured to detect and correct an error included in data read from the memory device 1200 using an error correction code (ECC).

[0134] The memory interface 1150 may be configured to interface with the memory device 1200. For example, the memory interface 1150 includes a NAND interface or a NOR interface.

[0135] The controller 1100 may further include a buffer memory (not shown) for temporarily storing data. The buffer memory may be used to temporarily store data transmitted to the outside via the host interface 1130 or data transmitted from the storage device 1200 via the memory interface 1150. The controller 1100 may further include a ROM storing code data for interfacing with the host.

[0136] As described above, the memory system 1000 according to the embodiment of the present disclosure includes the memory device 1200 having improved integration and improved characteristics, and thus, the integration and characteristics of the memory system 1000 may be improved.

[0137] Fig.18 is a block diagram showing a configuration of a storage system according to an embodiment of the present disclosure. Hereinafter, descriptions of parts overlapping with the above parts will be omitted.

[0138] Reference Fig.18 , a storage system 1000' according to an embodiment of the present disclosure includes a storage device 1200' and a controller 1100. The controller 1100 includes a RAM 1110, a CPU 1120, a host interface 1130, an ECC circuit 1140, a memory interface 1150, and the like.

[0139] The storage device 1200' may be a non-volatile memory and may be configured according to the reference Fig. 6A , Figure 6B , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig. 9 and Fig.10A method for manufacturing a storage device described herein or a reference Fig.13A , Fig. 13B , Fig.14 , Fig.15A , Fig. 15B and Fig.16 The structure and manufacturing method of the memory device 1200' are the same as those of the above-described memory device, and thus, a detailed description will be omitted.

[0140] The memory device 1200' may be a multi-chip package including a plurality of memory chips. The plurality of memory chips are divided into a plurality of groups, and the plurality of groups are configured to communicate with the controller 1100 via the first to k-th channels (CH1 to CHk). In addition, the memory chips included in one group may be configured to communicate with the controller 1100 via a common channel. For reference, the memory system 1000' may be modified so that one memory chip is connected to one channel.

[0141] As described above, the memory system 1000' according to the embodiment of the present disclosure includes the memory device 1200' having improved integration and improved characteristics, and thus, the integration and characteristics of the memory system 1000' can be improved. In particular, the memory device 1200' is configured as a multi-chip package, and thus the data storage capacity of the memory system 1000' can be increased, and the operation speed of the memory system 1000' can be improved.

[0142] Fig.19 is a block diagram showing a configuration of a computing system according to one embodiment of the present disclosure. Hereinafter, descriptions of parts overlapping with the above parts will be omitted.

[0143] Reference Fig.19 , the computing system 2000 according to an embodiment of the present disclosure includes a storage device 2100, a CPU 2200, a RAM 2300, a user interface 2400, a power supply 2500, a system bus 2600, and the like.

[0144] The storage device 2100 stores data provided via the user interface 2400, data processed by the CPU 2200, and the like. In addition, the storage device 2100 is electrically connected to the CPU 2200, the RAM 2300, the user interface 2400, the power supply 2500, and the like via the system bus 2600. For example, the storage device 2100 may be connected to the system bus 2600 via a controller (not shown) or directly. When the storage device 2100 is directly connected to the system bus 2600, the function of the controller may be performed by the CPU 2200, the RAM 2300, and the like.

[0145] The storage device 2100 may be a non-volatile memory and may be configured according to the reference Fig. 6A , Figure 6B , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig. 9 and Fig.10 A method for manufacturing a storage device described herein or a reference Fig.13A , Fig. 13B , Fig.14 , Fig.15A , Fig. 15B and Fig.16 The structure and manufacturing method of the memory device 2100 are the same as those of the above-described memory device, and thus, a detailed description will be omitted.

[0146] As reference Fig.18 As described above, the memory device 2100 may be a multi-chip package including a plurality of memory chips.

[0147] The computing system 2000 configured as described above may be a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device for communicating information in a wireless environment, one of the various electronic devices constituting a home network, one of the various electronic devices constituting a computer network, one of the various electronic devices constituting a remote information network, an RFID device, and the like.

[0148] As described above, the computing system 2000 according to the embodiment of the present disclosure includes the memory device 2100 having improved integration and improved characteristics, and thus the characteristics of the computing system 2000 may also be improved.

[0149] Fig. 20 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure.

[0150] Reference Fig. 20 The computing system 3000 according to an embodiment of the present disclosure includes a software layer including an operating system 3200 , an application 3100 , a file system 3300 , a conversion layer 3400 , etc. In addition, the computing system 3000 includes a hardware layer including a storage device 3500 , etc.

[0151] The operating system 3200 may manage software resources, hardware resources, etc. of the computing system 3000 and control program execution of the central processing unit. The application 3100 is one of various application programs running on the computing system 3000 and may be a utility program executed by the operating system 3200.

[0152] The file system 3300 refers to a logical structure for managing data, files, etc. in the computing system 3000, and organizes the data or files stored in the storage device 3500 according to rules. The file system 3300 can be determined according to the operating system 3200 used in the computing system 3000. For example, when the operating system 3200 is one of Microsoft's Windows operating systems, the file system 3300 can be a file allocation table (FAT) or an NT file system (NTFS). When the operating system 3200 is one of the Unix / Linux operating systems, the file system 3300 can be an extended file system (EXT), a Unix file system (UFS), or a journaling file system (JFS).

[0153] In the drawing, the operating system 3200 , the application 3100 , and the file system 3300 are shown as separate blocks. However, the application 3100 and the file system 3300 may be included in the operating system 3200 .

[0154] The translation layer 3400 converts the address into a form suitable for the storage device 3500 in response to a request from the file system 3300. For example, the translation layer 3400 converts the logical address generated by the file system 3300 into a physical address of the storage device 3500. The mapping information between the logical address and the physical address can be stored as an address translation table. For example, the translation layer 3400 can be a flash translation layer (FTL), a universal flash link layer (ULL), etc.

[0155] The storage device 3500 may be a non-volatile memory and may be configured according to the reference Fig. 6A , Figure 6B , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig. 9 and Fig.10 A method for manufacturing a storage device described herein or a reference Fig.13A , Fig. 13B , Fig.14 , Fig.15A , Fig. 15B and Fig.16 The structure and manufacturing method of the memory device 3500 are the same as those of the above-described memory device, and thus, a detailed description will be omitted.

[0156] The computing system 3000 configured as described above can be divided into an operating system layer performed in an upper layer area and a controller layer performed in a lower layer area. Application 3100, operating system 3200, and file system 3300 are included in the operating system layer and can be driven by a working memory of the computing system 3000. In addition, conversion layer 3400 can be included in the operating system layer or the controller layer.

[0157] As described above, the computing system 3000 according to the embodiment of the present disclosure includes the memory device 3500 having improved integration and improved characteristics, and thus the characteristics of the computing system 3000 may also be improved.

[0158] According to the present disclosure, a hole is formed in a space between first cell plugs, so that a process of forming a gate conductive pattern can be more easily performed. In addition, a second cell plug is formed in the hole, so that the integration of a memory device can be improved.

[0159] Although the present disclosure has been shown and described with reference to certain examples of the embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the examples of the embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

[0160] In the above-mentioned embodiments, all steps may be selectively performed, or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, and the steps may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only for the purpose of facilitating the understanding of the embodiments of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0161] Meanwhile, examples of the embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, those terms are only for explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, and many changes can be made within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can also be made based on the technical scope of the present disclosure.

[0162] CROSS-REFERENCE TO RELATED APPLICATIONS

[0163] This application claims the priority of Korean Patent Application No. 10-2020-0150234 filed in the Korean Intellectual Property Office on November 11, 2020, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A storage device, comprising: A peripheral circuit is arranged on the substrate; as well as a gate stack structure, wherein the gate stack structure overlaps with the peripheral circuit, The gate stack structure includes: a plurality of first unit plugs having a cylindrical structure; and a plurality of second unit plugs having a hexagonal prism structure, and The plurality of second cell plugs include a channel layer vertically extending in a stacking direction of the gate stack structure and a storage layer surrounding the channel layer.

2. The storage device according to claim 1, wherein: A periphery of each of the plurality of second unit plugs is surrounded by at least six first unit plugs of the plurality of first unit plugs.

3. The storage device according to claim 1, wherein: A periphery of each of the plurality of second unit plugs is surrounded by at least four first unit plugs of the plurality of first unit plugs.

4. The storage device according to claim 1, wherein: The plurality of second cell plugs further include a core insulating layer vertically extending in the channel layer.

5. The storage device according to claim 1, wherein: The storage layer includes: a tunnel insulating layer surrounding the sidewalls of the channel layer; a charge storage layer surrounding a sidewall of the tunnel insulating layer; and a blocking insulating layer surrounding a sidewall of the charge storage layer, and The tunnel insulating layer and the charge storage layer have circular shapes, and the blocking insulating layer has a hexagonal shape.

6. The storage device according to claim 1, further comprising: a first contact plug pattern arranged on top of the plurality of first unit plugs; a second contact plug pattern disposed on top of the plurality of second unit plugs; as well as A hard mask pattern is disposed on a sidewall of the first contact plug pattern.

7. The storage device according to claim 6, wherein: A space between the first contact plug patterns arranged on top of two first cell plugs adjacent to each other among the plurality of first cell plugs is filled with the hard mask pattern.

8. A method for manufacturing a storage device, the method comprising the following steps: forming a stacked structure in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked; forming a plurality of first unit plugs penetrating the stacked structure; forming a first contact plug pattern on top of the plurality of first unit plugs; opening an upper portion of the stacked structure in a region where a plurality of second unit plugs are to be formed by forming a hard mask pattern on a sidewall of the first contact plug pattern; forming a hole penetrating the stacked structure by performing an etching process using the hard mask pattern and the first contact plug pattern; removing the plurality of sacrificial layers exposed through the holes, and forming a plurality of plate electrodes by filling a conductive layer in spaces where the plurality of sacrificial layers are removed; as well as forming the plurality of second unit plugs in the holes, Wherein, each of the plurality of second unit plugs has a hexagonal prism structure.

9. The method according to claim 8, wherein: In the step of forming the plurality of first unit plugs, six first unit plugs are formed along a circle to be spaced apart from each other at a certain distance.

10. The method according to claim 9, wherein: In the step of opening the upper portion of the stacked structure in the region where the plurality of second unit plugs are to be formed, central regions of the six first unit plugs arranged in a circular shape are opened in a hexagonal shape.

11. The method according to claim 10, wherein: The holes are formed in a hexagonal prism shape.

12. The method according to claim 11, wherein: The step of forming the plurality of second unit plugs comprises the following steps: sequentially forming a memory layer and a channel layer on a sidewall of the hole having the hexagonal prism shape; and The central region of the hole is filled with a core insulation layer.

13. The method according to claim 12, wherein: The step of forming the storage layer comprises the following steps: forming a blocking insulating layer by depositing a nitride layer on the sidewall of the hole having the hexagonal prism shape and then oxidizing the nitride layer; and forming a charge storage layer and a tunnel insulating layer in sequence on the sidewalls of the blocking insulating layer, The blocking insulating layer has a hexagonal shape in a horizontal cross section, and the charge storage layer and the tunnel insulating layer have a circular shape in a horizontal cross section.

14. The method according to claim 8, wherein: The step of forming the hard mask pattern on the sidewall of the first contact plug pattern comprises the following steps: forming a hard mask layer on top of the entire structure including the first contact plug pattern; and The hard mask pattern is formed by allowing the hard mask layer to remain only on the sidewall of the first contact plug pattern through an entire surface etching process.

15. The method according to claim 8, wherein: In the step of forming the plurality of first unit plugs, after forming circular holes penetrating the stacked structure, the first unit plugs having a cylindrical shape are formed in the corresponding circular holes.

16. A method for manufacturing a storage device, the method comprising the steps of: forming a stacked structure in which a plurality of sacrificial layers and a plurality of interlayer insulating layers are alternately stacked; forming a plurality of first unit plugs penetrating the stacked structure, wherein six first unit plugs among the plurality of first unit plugs are formed along a circle to be spaced apart from each other at a certain distance; forming a first contact plug pattern on top of the plurality of first unit plugs; defining a region in which an upper portion of the stack structure is opened in a hexagonal shape in a central region of the circle by forming a hard mask pattern on a sidewall of the first contact plug pattern; forming a plurality of holes having a hexagonal prism shape by etching the stacked structure in the opened region, the plurality of holes penetrating the stacked structure; forming a plurality of plate electrodes by removing the plurality of sacrificial layers exposed through the plurality of holes and filling a conductive layer in spaces where the plurality of sacrificial layers are removed; as well as A plurality of second unit plugs are formed in the plurality of holes.

17. The method according to claim 16, wherein: The step of forming the plurality of second unit plugs comprises the following steps: sequentially forming a memory layer and a channel layer on a sidewall of the hole having the hexagonal prism shape; and The central region of the hole is filled with a core insulation layer.

18. The method according to claim 17, wherein: The step of forming the storage layer comprises the following steps: forming a blocking insulating layer by depositing a nitride layer on the sidewall of the hole having the hexagonal prism shape and then oxidizing the nitride layer; and A charge storage layer and a tunnel insulating layer are sequentially formed on the sidewalls of the blocking insulating layer.

19. The method according to claim 18, wherein: The blocking insulating layer has a hexagonal shape in a horizontal cross-section, and the charge storage layer and the tunnel insulating layer have a circular shape in a horizontal cross-section.

20. The method according to claim 16, wherein: The step of forming the hard mask pattern on the sidewall of the first contact plug pattern comprises the following steps: forming a hard mask layer on top of the entire structure including the first contact plug pattern; and The hard mask pattern is formed by allowing the hard mask layer to remain only on the sidewall of the first contact plug pattern through an entire surface etching process.

21. A storage device, comprising: A peripheral circuit arranged on the substrate; as well as a first gate stacked structure and a second gate stacked structure overlapping the peripheral circuit, Each of the first gate stack structure and the second gate stack structure includes a plurality of first unit plugs having a cylindrical structure and a plurality of second unit plugs having a hexagonal prism structure, The isolation region between the first gate stack structure and the second gate stack structure has a plurality of interlayer insulating layers and a plurality of sacrificial layers, and the plurality of interlayer insulating layers and the plurality of sacrificial layers are alternately stacked in the isolation region, and Wherein, the plurality of second unit plugs include: A channel layer extending vertically in a stacking direction of the gate stack structure; and A storage layer surrounds the channel layer.

22. The storage device according to claim 21, wherein: Each of the first gate stacked structure and the second gate stacked structure has a plurality of interlayer insulating layers and a plurality of plate electrodes, and the plurality of interlayer insulating layers and the plurality of plate electrodes are alternately stacked in the first gate stacked structure and the second gate stacked structure.

23. The storage device according to claim 21, wherein: A periphery of each of the plurality of second unit plugs is surrounded by six first unit plugs of the plurality of first unit plugs.

24. The storage device according to claim 21, wherein: The plurality of second cell plugs further include a core insulating layer vertically extending in the channel layer.

25. The storage device according to claim 21, wherein: The storage layer includes: a tunnel insulating layer surrounding the sidewalls of the channel layer; a charge storage layer surrounding a sidewall of the tunnel insulating layer; and a blocking insulating layer surrounding a sidewall of the charge storage layer, and The tunnel insulating layer and the charge storage layer have circular shapes, and the blocking insulating layer has a hexagonal shape.

26. A method for manufacturing a storage device, the method comprising the steps of: Forming a stacked structure on a substrate region, the substrate region including a first gate stacked structure region and a second gate stacked structure region, wherein the stacked structure includes a plurality of sacrificial layers and a plurality of interlayer insulating layers, the plurality of sacrificial layers and the plurality of interlayer insulating layers being alternately stacked; forming a plurality of first cell plugs penetrating the stacked structure in the first gate stacked structure region and the second gate stacked structure region, wherein six first cell plugs among the plurality of first cell plugs are formed along a circle to be spaced apart from each other at a certain distance; forming a first contact plug pattern on top of the plurality of first unit plugs; defining a region in which an upper portion of the stack structure is opened in a hexagonal shape in a central region of the circle by forming a hard mask pattern on a sidewall of the first contact plug pattern; forming a plurality of holes having a hexagonal prism shape by etching the stacked structure in the opened region, the plurality of holes penetrating the stacked structure; removing the plurality of sacrificial layers exposed through the plurality of holes, wherein the plurality of sacrificial layers remain in a boundary region between the first gate stack structure region and the second gate stack structure region; forming a plurality of plate electrodes by filling a conductive layer in the spaces in the first gate stack structure region where the plurality of sacrificial layers are removed and in the spaces in the second gate stack structure region where the plurality of sacrificial layers are removed; as well as A plurality of second unit plugs are formed in the plurality of holes.

27. The method according to claim 26, wherein: The step of forming the plurality of second unit plugs comprises the following steps: sequentially forming a memory layer and a channel layer on a sidewall of the hole having the hexagonal prism shape; and The central region of the hole is filled with a core insulation layer.

28. The method according to claim 27, wherein: The step of forming the storage layer comprises the following steps: forming a blocking insulating layer by depositing a nitride layer on the sidewall of the hole having the hexagonal prism shape and then oxidizing the nitride layer; and A charge storage layer and a tunnel insulating layer are sequentially formed on the sidewalls of the blocking insulating layer.

29. The method according to claim 28, wherein: The blocking insulating layer has a hexagonal shape in a horizontal cross-section, and the charge storage layer and the tunnel insulating layer have a circular shape in a horizontal cross-section.

30. The method of claim 26, wherein: The step of forming the hard mask pattern on the sidewall of the first contact plug pattern comprises the following steps: forming a hard mask layer on top of the entire structure including the first contact plug pattern; and The hard mask pattern is formed by allowing the hard mask layer to remain only on the sidewall of the first contact plug pattern through an entire surface etching process.

31. The method of claim 26, wherein: The plurality of plate electrodes of the first gate stack structure and the plurality of plate electrodes of the second gate stack structure are electrically isolated from each other by the plurality of sacrificial layers remaining in the boundary region between the first gate stack structure region and the second gate stack structure region.

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