High electron mobility transistor and manufacturing method thereof

Abstract

The present invention discloses a high electron mobility transistor and a manufacturing method thereof, wherein the high electron mobility transistor includes a first III-V compound layer, a second III-V compound layer disposed on the first III-V compound layer, the composition of the second III-V compound layer being different from that of the first III-V compound layer, a trench disposed in the second III-V compound layer and the first III-V compound layer, wherein the trench has a first corner and a second corner, both of which are located in the first III-V compound layer, a first dielectric layer contacts the sidewall of the first corner, a second dielectric layer contacts the sidewall of the second corner, the first dielectric layer and the second dielectric layer are both located outside the trench, a gate is disposed in the trench, a source electrode is disposed on one side of the gate, a drain electrode is disposed on the other side of the gate, and a gate electrode is disposed directly above the gate.

Description

Technical Field

[0001] The invention relates to a manufacturing method and structure for preventing gate leakage of a high electron mobility transistor. Background Art

[0002] Due to their semiconducting properties, III-V semiconductor compounds can be used to form many types of integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, and high electron mobility transistors (HEMTs). In HEMTs, two semiconductor materials with different band gaps are combined at the junction to form a heterojunction, providing a pathway for carriers. In recent years, gallium nitride (GaN) materials have become suitable for high-power and high-frequency applications due to their wide band gap and high saturation velocity. GaN-based HEMTs generate a two-dimensional electron gas (2DEG) through the piezoelectric effect of the material itself. Compared to traditional transistors, HEMTs have higher electron speed and density, thus increasing switching speed.

[0003] However, leakage current often occurs at the corner of the bottom of the gate of the HEMT, which affects the performance of the HEMT. Summary of the Invention

[0004] In view of this, the present invention provides a structure of a high electron mobility transistor and a manufacturing method thereof to prevent leakage current.

[0005] According to a preferred embodiment of the present invention, a high electron mobility transistor includes a first III-V compound layer, a second III-V compound layer disposed on the first III-V compound layer, the composition of the second III-V compound layer being different from that of the first III-V compound layer, a trench disposed in the second III-V compound layer and the first III-V compound layer, wherein the trench has a first corner and a second corner both located in the first III-V compound layer, the first corner consisting of a first sidewall and a bottom surface, the second corner consisting of a second sidewall and the bottom surface, a first dielectric layer contacting the first sidewall, a second dielectric layer contacting the second sidewall, and the first dielectric layer and the second dielectric layer both located outside the trench, a gate disposed in the trench, a source electrode disposed on one side of the gate, a drain electrode disposed on the other side of the gate, and a gate electrode disposed directly above the gate.

[0006] According to another preferred embodiment of the present invention, a method for manufacturing a high electron mobility transistor includes providing a first III-V compound layer, then forming a groove in the first III-V compound layer, then forming a dielectric layer to fill the groove, and then forming a second III-V compound layer on the first III-V compound layer and contacting the dielectric layer, the composition of the second III-V compound layer is different from that of the first III-V compound layer, and then forming a trench in the first III-V compound layer and the second III-V compound layer, wherein the trench cuts off the dielectric layer so that the dielectric layer is divided into a first dielectric layer and a second dielectric layer respectively located on both sides of the trench, forming a gate in the trench, forming a source electrode, a drain electrode and a gate electrode, wherein the gate electrode is located directly above the gate, and the source electrode and the drain electrode are respectively located on both sides of the gate.

[0007] To make the above-mentioned objectives, features, and advantages of the present invention more readily apparent, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1 to 8 A schematic diagram of a method for manufacturing a high electron mobility transistor according to a preferred embodiment of the present invention;

[0009] Figure 9 A schematic diagram of a high electron mobility transistor according to another preferred embodiment of the present invention;

[0010] Figure 10 FIG2 is a schematic diagram of a high electron mobility transistor according to another preferred embodiment of the present invention.

[0011] Description of main component symbols

[0012] 10: Base

[0013] 12: First III-V compound layer

[0014] 14: Groove

[0015] 16: Dielectric layer

[0016] 16a: first dielectric layer

[0017] 16b: second dielectric layer

[0018] 18: Second III-V compound layer

[0019] 20: Protective layer

[0020] 22: Groove

[0021] 22a: bottom

[0022] 22b: first side wall

[0023] 22c: Second side wall

[0024] 24: First corner

[0025] 26: Second corner

[0026] 27: Dielectric layer

[0027] 28: Third III-V compound layer

[0028] 30: Gate

[0029] 32: Source electrode

[0030] 34: Drain electrode

[0031] 36: Gate electrode

[0032] 38: Two-dimensional electron gas

[0033] 100: High Electron Mobility Transistor

[0034] 161a: first surface

[0035] 162a: Second surface

[0036] 163b: Third surface

[0037] 164b: Fourth surface

[0038] D: Depth

[0039] D1: First distance

[0040] D2: Second distance

[0041] T:Thickness DETAILED DESCRIPTION

[0042] Figures 1 to 8 FIG1 is a method for manufacturing a high electron mobility transistor according to a preferred embodiment of the present invention. Figure 1 As shown, a substrate 10 is first provided, and then a first III-V compound layer 12 is formed to cover the substrate 10. The substrate 10 can be a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate, or a silicon-on-insulator substrate. The first III-V compound layer 12 is preferably gallium nitride, particularly undoped gallium nitride, which is the preferred material in this embodiment. However, depending on other circumstances, the first III-V compound layer 12 can also be other III-V compounds, such as aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride.

[0043] like Figure 2 As shown, a groove 14 is formed in the first III-V compound layer 12, as shown in FIG. Figure 3 As shown, a dielectric layer 16 is formed to cover the first III-V compound layer 12 and fill the recess 14. The dielectric layer 16 is preferably formed by a deposition method such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other deposition methods. Furthermore, the dielectric layer 16 may include SiN, SiO2, SiON, SiOCN, AlN, Al2O3, or AlON. In this embodiment, the dielectric layer 16 is preferably AlN.

[0044] like Figure 4 As shown, the dielectric layer 16 outside the groove 14 is removed, and the dielectric layer 16 is retained in the groove 14. At this time, the upper surface of the dielectric layer 16 is aligned with the upper surface of the first III-V compound layer 12. According to a preferred embodiment of the present invention, the dielectric layer 16 can be removed by dry etching or wet etching. Figure 5 As shown, a second III-V compound layer 18 is formed on the first III-V compound layer 12 and contacts the dielectric layer 16. The composition of the second III-V compound layer 18 differs from that of the first III-V compound layer 12. The second III-V compound layer 18 comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride. Next, depending on the product design, a protective layer 20 may be selectively formed over the second III-V compound layer 18. The protective layer 20 may be a dielectric material such as silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, silicon oxycarbon nitride, or aluminum nitride. According to a preferred embodiment of the present invention, the protective layer 20 is preferably a nitrogen-containing compound. The subsequent steps will be described using the formation of the protective layer 20 as an example.

[0045] like Figure 6As shown, a trench 22 is formed in the protective layer 20, the first III-V compound layer 12, and the second III-V compound layer 18. The trench 22 interrupts the dielectric layer 16, thereby dividing the dielectric layer 16 into a first dielectric layer 16a and a second dielectric layer 16b, respectively located on either side of the trench 22. The trench 22 is preferably formed using an etching process, and the dielectric layer 16 can be used as an etching stop layer. Specifically, during the process of forming the trench 22, the protective layer 20, the second III-V compound layer 18, the dielectric layer 16, and the first III-V compound layer 12 are etched in sequence. Since the trench 22 is only disposed shallowly in the first III-V compound layer 12, the etching process can stop when the dielectric layer 16 is reached, and then stop after etching a little deeper, thus avoiding over-etching. In addition, if the trench 22 has a high aspect ratio, the shape of the trench 22 is easily deformed or etched to an incorrect position during the etching process. At this time, the dielectric layer 16 can provide a buffer to compensate for the shape of the trench 22 or allow the etching deviation to occur within the range of the dielectric layer 16 without etching other materials.

[0046] According to a preferred embodiment of the present invention, the bottom of the trench 22 is preferably located in the first III-V compound layer 12. Furthermore, the trench 22 has a first corner 24 and a second corner 26, both of which are located in the first III-V compound layer 12. The bottom surface 22a of the trench 22 is flush with the bottom surfaces of the first dielectric layer 16a and the second dielectric layer 16b, but is not limited thereto. The depth of the bottom surface 22a of the trench 22 can be deeper than the bottom surfaces of the first dielectric layer 16a and the second dielectric layer 16b, while maintaining the first dielectric layer 16a and the second dielectric layer 16b around the first corner 24 and the second corner 26 of the trench 22.

[0047] like Figure 7 As shown, a dielectric layer 27 is selectively formed to cover the protective layer 20 and conformally cover the groove 22. The dielectric layer 27 is preferably aluminum nitride. In the subsequent manufacturing process, the formation of the dielectric layer 27 is taken as an example to continue the description. After the dielectric layer 27 is formed, a third III-V compound layer 28 is formed on the dielectric layer 27, covering the protective layer 20 and conformably covering the groove 22. The composition of the third III-V compound layer 28 is different from that of the first III-V compound layer 12. The third III-V compound layer 28 contains aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride or aluminum nitride. According to a preferred embodiment of the present invention, the third III-V compound layer 28 is aluminum gallium nitride. In addition, before forming the third III-V compound layer 28, a dielectric layer (not shown) can be selectively formed to cover the protective layer 20 and conformably cover the groove 22, as shown in FIG. Figure 8As shown, a gate 30 is formed within trench 22. Gate 30 is a p-type doped III-V compound layer. The p-type doped III-V compound layer and the first III-V compound layer 12 are preferably composed of the same Group III and Group V elements. For example, when the first III-V compound layer 12 is gallium nitride, gate 30 is p-type gallium nitride. A source electrode 32, a drain electrode 34, and a gate electrode 36 are then formed. Gate electrode 36 is located directly above and contacts gate 30. Source electrode 32 and drain electrode 34 are located on either side of gate 30, and both contact second III-V compound layer 18. The normally-off high electron mobility transistor 100 of the present invention is now complete.

[0048] Figure 8 A high electron mobility transistor is shown according to a preferred embodiment of the present invention. Figure 9 A high electron mobility transistor is shown according to another preferred embodiment of the present invention. Figure 10 A high electron mobility transistor is shown according to another preferred embodiment of the present invention. Figure 9 and Figure 10 Components with the same function will use Figure 8 Component marking in .

[0049] Please also see Figure 6 and Figure 8The high electron mobility transistor 100 includes a substrate 10, a first III-V compound layer 12 disposed on the substrate 10, a second III-V compound layer 18 disposed on the first III-V compound layer 12, wherein the composition of the second III-V compound layer 18 is different from that of the first III-V compound layer 12, a two-dimensional electron gas 38 is disposed in the first III-V compound layer 12, and a trench 22 is disposed in the second III-V compound layer 18 and the first III-V compound layer 12, wherein the trench 22 has a first corner 24 and a second corner 26, both of which are located in the first III-V compound layer 12, the first corner 24 is formed by a first sidewall 22b of the trench 22 and a bottom surface 22a of the trench 22, and the second corner 26 is formed by a second sidewall 22c and the bottom surface 22a of the trench 22. In addition, the bottom surfaces 22a of all trenches 22 contact the first III-V compound layer 12. A first dielectric layer 16a contacts the first sidewall 22b, a second dielectric layer 16b contacts the second sidewall 22c, and both the first dielectric layer 16a and the second dielectric layer 16b are located outside the trench 22. A gate 30 is disposed in the trench 22. A source electrode 32 is disposed on one side of the gate 30 and contacts the second III-V compound layer 18. A drain electrode 34 is disposed on the other side of the gate 30 and contacts the second III-V compound layer 18. A gate electrode 36 is disposed directly above the gate 30 and contacts the gate 30.

[0050] In addition, a third III-V compound layer 28 is disposed in the trench 22 and between the trench 22 and the gate 30. A dielectric layer 27 may be selectively disposed between the third III-V compound layer 28 and the trench 22. If the dielectric layer 27 is not disposed, the Figure 9 As shown, a portion of the third III-V compound layer 28 contacts the first III-V compound layer 12. The third III-V compound layer 28 disposed on the bottom surface 22a of the trench 22 is intended to increase the current of the high electron mobility transistor 100. A protective layer 20 is optionally disposed on the second III-V compound layer 18. When the protective layer 20 is disposed, the trench 22 is also disposed in the protective layer 20.

[0051] The first dielectric layer 16a has a first surface 161a and a second surface 162a. The first surface 161a contacts the first sidewall 22b, and the first surface 161a and the second surface 162a are opposite each other. The second dielectric layer 16b has a third surface 163b and a fourth surface 164b. The third surface 163b contacts the second sidewall 22c, and the third surface 163b and the fourth surface 164b are opposite each other. A first distance D1 is defined between the first surface 161a and the third surface 163b, and a second distance D2 is defined between the second surface 162a and the fourth surface 164b. The second distance D2 is 1.01 to 1.2 times the first distance D1. The width of the first dielectric layer 16a and the width of the second dielectric layer 16b can be the same or different. In other words, the size of the first dielectric layer 16a and the second dielectric layer 16b is not limited, as long as the first dielectric layer 16a and the second dielectric layer 16b are located near the first corner 24 and the second corner 26 of the trench 22. Figure 8 The width of the first dielectric layer 16a and the width of the second dielectric layer 16b are the same, but in Figure 10 In the embodiment, the width of the first dielectric layer 16a is smaller than the width of the second dielectric layer 16b, that is, the width of the second dielectric layer 16b closer to the drain is larger. The materials of the first dielectric layer 16a and the second dielectric layer 16b include SiN, SiO2, SiON, SiOCN, AlN, Al2O3, AlON, or GaON. According to a preferred embodiment of the present invention, the first dielectric layer 16a and the second dielectric layer 16b are made of the same material, such as AlN.

[0052] Because charge is easily accumulated around the two corners at the bottom of gate 30, causing leakage, the present invention specifically provides a first dielectric layer 16a and a second dielectric layer 16b around the two corners at the bottom of gate 30 to prevent leakage. Furthermore, stress is easily accumulated at the first corner 24 and the second corner 26 of trench 22, causing cracks. The first dielectric layer 16a and the second dielectric layer 16b prevent cracks at these corners.

[0053] It is worth noting that the entire bottom surface 22 a of the trench 22 contacts the first III-V compound layer 12 , that is, there is no dielectric layer between the bottom surface 22 a and the first III-V compound layer 12 . If there is a dielectric layer on the bottom surface 22 a of the trench 22 , the on-resistance (Ron) of the high electron mobility transistor 100 will increase.

[0054] Also, see Figure 6The trench 22 in the second III-V compound layer 18 and the first III-V compound layer 12 has a depth D. The second III-V compound layer 18 has a thickness T. The depth D affects the channel resistance of the high electron mobility transistor 100. As the depth D increases, the voltage required to turn on the channel of the high electron mobility transistor 100 increases, resulting in higher power consumption of the high electron mobility transistor 100. According to a preferred embodiment of the present invention, when the depth D is 1.05 to 1.8 times the thickness T, the performance of the high electron mobility transistor 100 is better.

[0055] The first III-V compound layer 12 comprises gallium nitride, aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride. The second III-V compound layer 18 comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride. The third III-V compound layer 28 comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride. The gate 30 is a III-V compound layer with a p-type dopant. The p-type dopant and the first III-V compound layer 12 are preferably composed of the same Group III and Group V elements.

[0056] In this embodiment, the first III-V compound layer 12 is gallium nitride, the second III-V compound layer 18 is aluminum gallium nitride, the third III-V compound layer 28 is aluminum gallium nitride, and the gate 30 is p-type gallium nitride. The protective layer 20 comprises silicon oxide, silicon nitride, silicon carbon nitride, silicon oxynitride, or silicon carbon nitride, or aluminum nitride. In this embodiment, the protective layer 20 is preferably a nitrogen-containing compound such as silicon nitride. In other embodiments, the first III-V compound layer 12, the second III-V compound layer 18, and the third III-V compound layer 28 may be composed of the same Group III and Group V elements, but with different ratios of Group III and Group V elements in the compound layers. The source electrode, the drain electrode, and the gate electrode each comprise titanium, aluminum, nickel, platinum, or gold.

[0057] The present invention specifically disposes a first dielectric layer 16a and a second dielectric layer 16b on both sides of the trench 22 accommodating the gate 30 to prevent leakage current from occurring at the bottom corner of the gate 30. Furthermore, the first dielectric layer 16a and the second dielectric layer 16b can compensate for defects that may occur in the manufacturing process at the first corner 24 and the second corner 26 of the trench and disperse stress around the first corner 24 and the second corner 26.

[0058] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A high electron mobility transistor, characterized in that Include: a first III-V compound layer; a second III-V compound layer disposed on the first III-V compound layer, wherein the composition of the second III-V compound layer is different from that of the first III-V compound layer; a trench disposed in the second III-V compound layer and the first III-V compound layer, wherein the trench has a first corner and a second corner both located in the first III-V compound layer, the first corner consisting of a first sidewall and a bottom surface, and the second corner consisting of a second sidewall and the bottom surface; a first dielectric layer contacting the first sidewall and located at the first corner, a second dielectric layer contacting the second sidewall and located at the second corner, and both the first dielectric layer and the second dielectric layer are located outside the trench, wherein both the first dielectric layer and the second dielectric layer are buried in the first III-V compound layer; a gate disposed in the trench; a source electrode, disposed on one side of the gate; a drain electrode, disposed on the other side of the gate; as well as The gate electrode is provided directly above the gate. 2 . The high electron mobility transistor as claimed in claim 1 , wherein the entire bottom surface contacts the first III-V compound layer.

3. The high electron mobility transistor as claimed in claim 1, wherein the gate is a group III-V compound layer with P-type dopant, and the group III-V compound layer with P-type dopant and the first group III-V compound layer are composed of the same group III and group V elements. 4 . The high electron mobility transistor of claim 1 , further comprising a third III-V compound layer disposed in the trench and between the trench and the gate. 5 . The high electron mobility transistor of claim 4 , wherein a portion of the third III-V compound layer contacts the first III-V compound layer. 6 . The high electron mobility transistor of claim 4 , wherein the third III-V compound layer and the second III-V compound layer are composed of the same Group III and Group V elements. 7 . The high electron mobility transistor of claim 1 , wherein the first III-V compound layer comprises gallium nitride, and the second III-V compound layer comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride.

8. The high electron mobility transistor of claim 1 , wherein the first dielectric layer has a first surface and a second surface, the first surface contacts the first sidewall, the first surface and the second surface are opposite to each other, the second dielectric layer has a third surface and a fourth surface, the third surface contacts the second sidewall, the third surface and the fourth surface are opposite to each other, a first distance exists between the first surface and the third surface, a second distance exists between the second surface and the fourth surface, and the second distance is 1.01 to 1.2 times the first distance. 9 . The high electron mobility transistor of claim 1 , wherein the trench in the second III-V compound layer and the first III-V compound layer has a depth, the second III-V compound layer has a thickness, and the depth is 1.05 to 1.8 times the thickness. 10 . The high electron mobility transistor as claimed in claim 1 , further comprising a protection layer covering the second III-V compound layer.

11. The high electron mobility transistor of claim 1, wherein the first dielectric layer comprises SiN, SiO2, SiON, SiOCN, AlN, Al2O3, AlON, or GaON, and the second dielectric layer comprises SiN, SiO2, SiON, SiOCN, AlN, Al2O3, AlON, or GaON. 12 . The high electron mobility transistor of claim 1 , further comprising a two-dimensional electron gas disposed in the first III-V compound layer.

13. A method for manufacturing a high electron mobility transistor, comprising: providing a first III-V compound layer; forming a groove in the first III-V compound layer; forming a dielectric layer to fill the groove; forming a second III-V compound layer on the first III-V compound layer and contacting the dielectric layer, wherein the second III-V compound layer has a different composition than the first III-V compound layer; forming a trench in the first III-V compound layer and the second III-V compound layer, wherein the trench intercepts the dielectric layer so that the dielectric layer is divided into a first dielectric layer and a second dielectric layer respectively located at bottom corners on both sides of the trench, wherein the first dielectric layer and the second dielectric layer are both buried in the first III-V compound layer; forming a gate in the trench; A source electrode, a drain electrode and a gate electrode are formed, wherein the gate electrode is located directly above the gate, and the source electrode and the drain electrode are respectively located on both sides of the gate. 14 . The method for fabricating a high electron mobility transistor according to claim 13 , further comprising: before forming the trench, forming a protection layer to cover the second III-V compound layer. 15 . The method for fabricating a high electron mobility transistor according to claim 14 , wherein the trench is located in the protection layer, the second III-V compound layer, and the first III-V compound layer. 16 . The method for fabricating a high electron mobility transistor according to claim 13 , further comprising forming a third III-V compound layer contacting the trench before forming the gate, wherein the third III-V compound layer and the second III-V compound layer are composed of the same Group III and Group V elements. 17 . The method for fabricating a high electron mobility transistor according to claim 13 , wherein the first III-V compound layer comprises gallium nitride, and the second III-V compound layer comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride, or aluminum nitride.

18. The method for fabricating a high electron mobility transistor as described in claim 13, wherein the trench has a first corner and a second corner both located in the first III-V compound layer, the first corner consists of a first sidewall and a bottom surface, the second corner consists of a second sidewall and the bottom surface, the first dielectric layer contacts the first sidewall, the second dielectric layer contacts the second sidewall, and the first dielectric layer and the second dielectric layer are both located outside the trench.

19. The method for fabricating a high electron mobility transistor according to claim 13, wherein the gate is a group III-V compound layer with P-type dopant, and the group III-V compound layer with P-type dopant and the first group III-V compound layer are composed of the same group III and group V elements.

20. The method for fabricating a high electron mobility transistor according to claim 13, wherein the first dielectric layer comprises SiN, SiO2, SiON, SiOCN, AlN, Al2O3, AlON or GaON, and the second dielectric layer comprises SiN, SiO2, SiON, SiOCN, AlN, Al2O3, AlON or GaON.

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