A boost circuit with adaptive slope compensation

Abstract

The present application relates to a kind of adaptive slope compensation BOOST circuit, including basic BOOST circuit and adaptive slope compensation circuit, the basic BOOST circuit is set to receive input voltage V in And provide output voltage V out , the adaptive slope compensation circuit includes differential circuit and slope generation circuit, the differential circuit is set to generate the difference current of current size with the difference of output voltage V out And input voltage V in The slope generation circuit is set to generate sawtooth wave voltage with the difference of output voltage V out And input voltage V in The adaptive slope compensation BOOST circuit of the present application, using differential circuit and slope generation circuit generates a compensation slope voltage signal related to input and output voltage while varying with duty cycle, simple structure, easy to realize, and good compensation performance in a wide range of output voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and more particularly to a BOOST circuit with adaptive slope compensation. BACKGROUND

[0002] With the explosive development of electronic industry, power management chip as an extremely important voltage stabilizing module is widely used in portable devices, which requires the chip to ensure stable and efficient working state under wide input and output voltage variation range. Compared with other types of power management chips, DC-DC converter has great advantages in conversion efficiency, especially the peak current control mode BOOST circuit, which is widely used due to its fast transient response, large gain bandwidth, excellent EMI characteristics and other advantages.

[0003] However, the peak current control mode will appear sub-harmonic oscillation when the duty cycle is greater than 50%, as shown in Figure 1A and 1B , ΔI0 is the initial disturbance of inductor current, and ΔI1 is the disturbance after one period, which can be expressed as:

[0004]

[0005] Where S n and S f are the slopes of the inductor current rising and falling in the BOOST circuit, which can be expressed as:

[0006] and

[0007] Therefore, the expression of ΔI1 can be changed to:

[0008]

[0009] Then the disturbance ΔI n of ΔI0 after n periods can be expressed as:

[0010]

[0011] From the above formula, when D>50%, the formula does not converge, and sub-harmonic oscillation phenomenon occurs. In order to suppress this phenomenon, a compensation slope with a slope of S e is introduced by using a slope compensation circuit, and the expression of ΔI n can be changed to:

[0012]

[0013] As long as the value of S e is ensured to make So that the above formula converges, and thus the sub-harmonic oscillation phenomenon can be avoided when the duty cycle D>50%.

[0014] Traditional slope compensation can be divided into one-time slope compensation and segmented slope compensation, as shown in the following table. Figure 2 As shown in the table, a fixed slope ramp signal is constructed in one clock cycle, which can effectively suppress the sub-harmonic oscillation phenomenon, but the required slope slope is often not a fixed value under different duty cycles. When determining the slope slope, the slope required at the maximum duty cycle is generally used. Relatively, over-compensation occurs when the duty cycle is small, which reduces the gain bandwidth and greatly reduces the transient response capability. The segmented slope compensation is to construct several fixed slope ramp signals at the same time, which are applied in different duty cycles. This method is not the optimal solution for compensation in the full duty cycle range. At the same time, the introduction of multiple charging and discharging capacitors will greatly reduce the silicon utilization rate. SUMMARY

[0015] The purpose of the present application is to provide an adaptive slope compensation BOOST circuit, which dynamically modulates the slope of the compensation slope according to the change of the input and output voltages, thereby avoiding over-compensation or under-compensation, effectively suppressing sub-harmonic oscillation, and improving the transient response capability.

[0016] The present application provides an adaptive slope compensation BOOST circuit, comprising: a basic BOOST circuit and an adaptive slope compensation circuit, the basic BOOST circuit is arranged to receive an input voltage V in and provide an output voltage V out , the adaptive slope compensation circuit comprises a differential circuit and a slope generation circuit, the differential circuit is arranged to generate a differential current whose size is proportional to the difference between the output voltage V out and the input voltage V in , and the slope generation circuit is arranged to generate a sawtooth voltage whose slope is proportional to the difference between the output voltage V out and the input voltage V in .

[0017] Further, the basic BOOST circuit comprises a power switch tube M1, a synchronous rectifier tube M2, an energy storage inductor L sw , a first feedback resistor R fb1 , a second feedback resistor R fb2 , an inductor current sampling circuit V sense , an error amplifier EA, a pulse width modulation comparator PWM, a logic circuit, a first drive buffer, a second drive buffer, a load resistor R L , and an output capacitor C O, the drain of the power switch tube M1 and the drain of the synchronous rectifier M2 are connected and the connection point of the power switch tube M1 and the synchronous rectifier M2 is arranged to receive the induced voltage V sw , one end of the energy storage inductor L sw is connected to the first voltage source to receive the input voltage V in , the other end of the energy storage inductor L sw provides the induced voltage V sw ; the source of the power switch tube M1 is connected to the reference ground voltage GND, the source of the synchronous rectifier M2 is connected to one end of the output capacitor C O , one end of the load resistor R L and the voltage output end, the other end of the output capacitor C O is connected to the reference ground voltage GND, the other end of the load resistor R L is connected to the reference ground voltage GND; the first feedback resistor R fb1 and the second feedback resistor R fb2 are connected and the connection point is arranged to provide the feedback voltage V fb , the other end of the first feedback resistor R fb1 is connected to the voltage output end to receive the output voltage V out provided by the voltage output end, the other end of the second feedback resistor R fb2 is connected to the reference ground voltage GND; the positive input end of the error amplifier EA is connected to the second voltage source to receive the reference voltage V ref , the negative input end receives the feedback voltage V fb ; the negative input end of the pulse width modulation comparator PWM is connected to the output end of the error amplifier EA, the output end is connected to the input end of the logic circuit; the two output ends of the logic circuit are respectively connected to the input ends of the first drive buffer and the second drive buffer, the output ends of the first drive buffer and the second drive buffer are respectively connected to the control ends of the synchronous rectifier M2 and the power switch tube M1; the input end of the inductor current sampling circuit V sense is connected to the end of the energy storage inductor L sw providing the induced voltage V sw to receive the inducted inductor current sampling signal I sense , the output signal provided by the output end is superimposed with the output voltage of the adaptive slope compensation circuit and then received by the positive input end of the pulse width modulation comparator PWM; the output voltage of the adaptive slope compensation circuit is the sawtooth wave voltage V slope .

[0018] Further, the differential circuit comprises first, second, third and fourth differential PMOS tubes MP1, MP2, MP3, MP4, first, second, third and fourth differential NMOS tubes MN1, MN2, MN3, MN4, a first current source, a second current source, a third current source, a fourth current source and a first resistor R1; one end of the first current source receives an input voltage V in , and the other end is connected to the gate of the first differential PMOS tube MP1 and the second differential PMOS tube MP2 and the drain of the first differential NMOS tube MN1; one end of the second current source I2 is connected to the input voltage V in , and the other end is connected to the gate of the third differential PMOS tube MP3 and the fourth differential PMOS tube MP4 and the drain of the second differential NMOS tube MN2, the gate of the first differential NMOS tube MN1 is connected to a voltage proportional to the output voltage V out , the source of the first differential NMOS tube MN1 is connected to one end of the third current source, and the other end of the third current source is connected to a reference ground voltage GND; the gate of the second differential NMOS tube MN2 is connected to a voltage proportional to the input voltage V in , the source of the second differential NMOS tube MN2 is connected to one end of the fourth current source, and the other end of the fourth current source is connected to the reference ground voltage GND; one end of the first resistor R1 is connected to one end of the third current source, the drain of the second differential PMOS tube MP2 and the source of the first differential NMOS tube MN1, and the other end of the first resistor R1 is connected to one end of the fourth current source, the drain of the third differential PMOS tube MP3 and the source of the second differential NMOS tube MN2; the sources of the first differential PMOS tube MP1, the second differential PMOS tube MP2, the third differential PMOS tube MP3 and the fourth differential PMOS tube MP4 receive the input voltage V in , the drain of the first differential PMOS tube MP1 is connected to the drain and the gate of the third differential NMOS tube MN3, the source of the third differential NMOS tube MN3 is connected to the reference ground voltage GND; the drain of the fourth differential PMOS tube MP4 is connected to the drain of the fourth differential NMOS tube MN4, and the source of the fourth differential NMOS tube MN4 is connected to the reference ground voltage GND.

[0019] Further, the voltage connected to the gate of the first differential NMOS tube MN1 is V out / 4.

[0020] Further, the voltage connected to the gate of the second differential NMOS tube MN2 is V in / 4.

[0021] Further, the first fixed current I1 provided by the first current source is equal to the second fixed current I2 provided by the second current source, and the third fixed current I3 provided by the third current source is equal to the fourth fixed current I4 provided by the fourth current source.

[0022] Further, the slope generating circuit comprises a first slope PMOS MP5, a second slope PMOS MP6, a slope NMOS MN5 and a first capacitor C1, the source of the first slope PMOS MP5 and the source of the second slope PMOS MP6 receive an input voltage V in in, the drain of the first slope PMOS MP5 is connected with the gate of the first slope PMOS MP5 and the gate of the second slope PMOS MP6, the drain of the second slope PMOS MP6 is connected with one end of the first capacitor C1 and the drain of the slope NMOS MN5, and is set to output an output voltage of the adaptive slope compensation circuit, the gate of the slope NMOS MN5 is connected with a clock signal CLK of the basic BOOST circuit, and the other end of the first capacitor C1 and the source of the slope NMOS MN5 are connected with a reference ground voltage GND.

[0023] Further, the third differential PMOS MP3 and the fourth differential PMOS MP4, the second differential PMOS MP2 and the first differential PMOS MP1, and the third differential NMOS MN3 and the fourth differential NMOS MN4 respectively constitute a current mirror with a ratio of 1:1.

[0024] Further, the first slope PMOS MP5 and the second slope PMOS MP6 constitute a current mirror with a ratio of 1:1.

[0025] Further, the first capacitor C1, the first resistor R1 and the energy storage inductor L sw satisfy the relationship: 2R1C1=L sw .

[0026] The adaptive slope compensation BOOST circuit of the present application generates a compensation slope voltage signal related to input and output voltages and changing with duty cycle by using a differential circuit and a slope generating circuit, has a simple structure, is easy to realize, and has good compensation performance in a wide output voltage range. Due to the special structure of the differential circuit, the differential current can be very small, the capacitor area can be reduced accordingly while reducing power consumption, and the silicon utilization rate is greatly improved. The adaptive slope compensation function can provide the optimal solution for the slope compensation of the BOOST circuit under different duty cycles, avoid overcompensation or undercompensation, effectively suppress subharmonic oscillation, and improve the transient response capability. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1A and 1B are respectively the system disturbance affected by inductance current when the existing peak current mode BOOST circuit has a duty cycle less than 50% and greater than 50%;

[0028] Figure 2 Fig. 2 is a diagram showing the system affected by inductance current disturbance after introducing the first slope compensation in the existing peak current mode BOOST circuit;

[0029] Figure 3 Fig. 3 is a block diagram of the adaptive slope compensation BOOST circuit according to the embodiment of the present application;

[0030] Figure 4 Fig. 4 is a block diagram of the adaptive slope compensation circuit according to the embodiment of the present application;

[0031] Figure 5A Fig. 5 is a slope voltage waveform diagram when the input voltage is fixed and the output voltage varies according to the embodiment of the present application;

[0032] Figure 5B Fig. 6 is a slope voltage waveform diagram when the output voltage is fixed and the input voltage varies according to the embodiment of the present application. DETAILED DESCRIPTION

[0033] The preferred embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0034] As shown in Figure 3 , the embodiment of the present application provides an adaptive slope compensation BOOST circuit, which comprises a basic BOOST circuit and an adaptive slope compensation circuit 102 electrically connected to each other. The basic BOOST circuit comprises a power switch tube M1, a synchronous rectifier tube M2, an energy storage inductor L sw , a first feedback resistor R fb1 , a second feedback resistor R fb2 , an inductance current sampling circuit V sense , an error amplifier EA, a pulse width modulation comparator PWM, a logic circuit 101, a first drive buffer 103, a second drive buffer 104, a load resistor R L , an output capacitor C O , a first voltage source and a second voltage source, wherein the first voltage source is used to provide an input voltage V in , and the second voltage source is used to provide a reference voltage V ref .

[0035] The drain of the power switch tube M1 is connected to the drain of the synchronous rectifier tube M2, and the connection point of the power switch tube M1 and the synchronous rectifier tube M2 is arranged to receive an induced voltage V sw . One end of the energy storage inductor L sw is connected to the first voltage source to receive the input voltage V in , and the other end of the energy storage inductor L sw provides the induced voltage V sw ; the source of the power switch tube M1 is connected to a reference ground voltage GND, and the source of the synchronous rectifier tube M2 is also connected to the output capacitor CO One end, load resistor R L One end and the voltage output terminal, to provide the output voltage V to the voltage output terminal. out Output capacitor C O The other end is connected to the reference ground voltage GND, and the load resistance R L The other end is connected to the reference ground voltage GND. In this embodiment, the power switch M1 is an NMOS transistor, and the synchronous rectifier M2 is a PMOS transistor.

[0036] First feedback resistor R fb1 Second feedback resistor R fb2 Connected, first feedback resistor R fb1 Second feedback resistor R fb2 The connection point is configured to provide a feedback voltage V. fb First feedback resistor R fb1 The other end is connected to the voltage output terminal to receive the output voltage V provided by the voltage output terminal. out The second feedback resistor R fb2 The other end is connected to the reference ground voltage GND.

[0037] The positive input of the error amplifier EA is connected to a second voltage source to receive the reference voltage V. ref The negative input terminal receives the feedback voltage V. fb .

[0038] The negative input of the pulse width modulation comparator (PWM) is connected to the output of the error amplifier (EA), and the output is connected to the input of the logic circuit 101.

[0039] The two output terminals of logic circuit 101 are connected to the input terminals of the first drive buffer 103 and the second drive buffer 104, respectively. The output terminals of the first drive buffer 103 and the second drive buffer 104 are connected to the control terminals of the synchronous rectifier tube M2 and the power switch tube M1, respectively.

[0040] Inductor current sampling circuit V sense The input terminal and the energy storage inductor L sw The induced voltage V is provided sw One end is connected to receive the inductor current sampling signal I. sense The output signal provided by its output terminal is superimposed with the output voltage of the adaptive slope compensation circuit 102 and then received by the positive input terminal of the pulse width modulation comparator PWM.

[0041] like Figure 4 As shown, the adaptive slope compensation circuit 102 includes a differential circuit and a slope generation circuit, wherein the differential circuit is used to generate a current magnitude that is related to the output voltage V. out and input voltage V ina differential current proportional to the difference between the input voltage V out and the output voltage V in , the ramp generation circuit is used to generate a sawtooth voltage proportional to the difference between the input voltage V

[0042] The differential circuit comprises first, second, third and fourth differential PMOS transistors MP1, MP2, MP3 and MP4, first, second, third and fourth differential NMOS transistors MN1, MN2, MN3 and MN4, a first current source, a second current source, a third current source, a fourth current source and a first resistor R1, and the ramp generation circuit comprises first and second ramp PMOS transistors MP5 and MP6, a ramp NMOS transistor MN5 and a first capacitor C1.

[0043] The first current source and the second current source are respectively used to provide a first fixed current I1 and a second fixed current I2, and I1 = I2, and the third current source and the fourth current source are respectively used to provide a third fixed current I3 and a fourth fixed current I4, and I3 = I4. The first capacitor C1 is used to generate a sawtooth voltage signal V slope .

[0044] One end of the first current source receives the input voltage V in , and the other end is connected to the gate of the first differential PMOS transistor MP1 and the second differential PMOS transistor MP2 and the drain of the first differential NMOS transistor MN1; one end of the second current source is connected to the input voltage V in , and the other end is connected to the gate of MP3 and MP4 and the drain of MN2.

[0045] The gate of MN1 is connected to a voltage proportional to the output voltage V out , which is V out / 4 in this embodiment, and the source of MN1 is connected to one end of the third current source, and the other end of the third current source is connected to a reference ground voltage GND; the gate of MN2 is connected to a voltage proportional to the input voltage V in , which is V in / 4 in this embodiment, and the source of MN2 is connected to one end of the fourth current source, and the other end of the fourth current source is connected to the reference ground voltage GND.

[0046] One end of the first resistor R1 is connected to one end of the third current source, the drain of MP2 and the source of MN1, and the other end of the first resistor R1 is connected to one end of the fourth current source, the drain of MP3 and the source of MN2.

[0047] The sources of MP1, MP2, MP3 and MP4 receive the input voltage V in , the drain of MP1 is connected to the drain and gate of MN3, and the source of MN3 is connected to the reference ground voltage GND; the drain of MP4 is connected to the drain of MN4, and the source of MN4 is connected to the reference ground voltage GND.

[0048] The source of PMOS transistors MP5 and MP6 receives an input voltage V in The drain of MP5 is connected to the gate of MP5 and MP6, and the drain of MP4 and MN4.

[0049] The drain of MP6 is connected to one end of a first capacitor C1 and the drain of MN5, and is configured to output an output voltage (i.e., a sawtooth voltage V slope ) of the adaptive slope compensation circuit 102, the gate of MN5 is connected to a clock signal CLK of the BOOST circuit, the other end of C1 and the source of MN5 are connected to a reference ground voltage GND.

[0050] The control-to-output transfer function of the BOOST converter can be expressed as (Pulse Width Modulation DC-DC Power Conversion—Circuit, Dynamic Characteristics and Control Design[M].Cui Bingzhou, Mechanical Industry Press, 2018: 472-477):

[0051]

[0052] where s is a complex frequency domain independent variable, Kvc is a low frequency gain, ω esr is an output capacitor ESR zero point, ω rhp is a right half plane zero point, ω p1 is an output main pole, ω n is one-half of the switching frequency.

[0053] In the control-to-output transfer function of the current control mode BOOST circuit, the quality factor Q of the second order term can be expressed as (A new, continuous-time model for current-mode control[J].Ridley R B.IEEE Transactions on Power Electronics, 1991, 6(2): 271-280):

[0054]

[0055] where, S n is the slope of the inductor current rise in peak current mode, S e is the slope of the compensation slope, D is the duty ratio, and D' = 1-D. To make the system stable and have good transient performance, it is necessary to ensure that the quality factor

[0056] For the peak current mode basic BOOST circuit, the inductor current rise slope S n and the drop slope S f are:

[0057]

[0058] S n Substitute the expression of Q, we can find that when , That is, to make the system stable and good transient performance, need to ensure And at this time the circuit implementation is relatively easy.

[0059] Thus we can see that, in different input and output voltage, that is, different duty cycle conditions, the optimal solution of slope compensation is not fixed, can be considered that it and V out and V in Difference exists linear relationship, for the use of fixed inductance L sw BOOST circuit, can be considered that the relationship coefficient is a fixed value.

[0060] In the differential circuit, because I1=I2, so the current through MN1 and MN2 are equal, and MN1 and MN2 gate are connected to V out / 4 and V in / 4, therefore:

[0061]

[0062] Where V R is the voltage difference between the first resistor R1.

[0063] By analyzing the current network between the first resistor R1, we can get:

[0064] I X =I3+I R -I1

[0065] I Y =I4+I R -I2

[0066] Where, I X , I Y , I R are the current flowing into or out of the current network between the first resistor R1, I1-I4 is the DC current set in advance (i.e. the first, second, third, fourth fixed current), wherein the differential pair MN1 and MN2 control voltage changes will affect the current value of I X , I Y , so the difference between I X and I Y can directly reflect the difference between the differential pair MN1 and MN2 control end.

[0067] In this embodiment, MP3 and MP4, MP2 and MP1 constitute current mirrors with a ratio of 1:A respectively, while MN3 and MN4 constitute a current mirror with a ratio of 1:1, in which case:

[0068] I out1 = AI X

[0069] I out2 = AI Y

[0070] According to Kirchhoff's current law, we have:

[0071] I out = I out1 -I out2

[0072] where Iout is the output current of the differential circuit.

[0073] Since I1=I2, I3=I4, we can get:

[0074]

[0075] To generate different charging currents and match different capacitor values, the differential current is multiplied by the current mirror coefficient A and then multiplied by the current mirror coefficient B. Therefore, in the slope generation circuit, MP5 and MP6 constitute a current mirror with a ratio of 1:B, so the slope generation current I slope is:

[0076]

[0077] To simplify the formula, in this embodiment, the current mirror ratios A and B are both set to 1. Of course, A and B can also take other appropriate values as needed.

[0078] Using I slope to charge the first capacitor C1, the clock signal CLK of the BOOST circuit controls the charging and discharging period of the first capacitor C1, thereby forming a sawtooth wave, and the sawtooth wave voltage V slope output by the adaptive slope compensation circuit 102 is:

[0079]

[0080] Through the foregoing analysis, it can be known that the optimal solution of the slope compensation of the basic BOOST circuit is:

[0081]

[0082] Therefore, only need to set the value of R1 and C1, so that 2R1C1=L, can provide the optimal compensation ramp for the BOOST circuit under different duty cycles, in this embodiment, L=L sw .

[0083] As shown in Figure 5A , when the input voltage is fixed, the output voltage gradually increases, that is, the duty cycle becomes larger, the slope voltage slope gradually increases; as shown in Figure 5B , when the output voltage is fixed, the input voltage gradually increases, that is, the duty cycle becomes smaller, the slope voltage slope gradually decreases; thereby realizing the adaptive slope compensation function.

[0084] The adaptive slope compensation BOOST circuit provided by the embodiment of the application generates a compensation slope voltage signal related to input and output voltages and changing with the duty cycle by using a differential circuit and a slope generation circuit, has a simple structure, is easy to implement, and has good compensation performance in a wide output voltage range. Due to the special structure of the differential circuit, the differential current can be small, the capacitor area can be reduced accordingly while reducing power consumption, and the silicon utilization rate is greatly improved. The adaptive slope compensation function can provide the optimal solution for the BOOST circuit under different duty cycles, avoid overcompensation or undercompensation, effectively suppress the sub-harmonic oscillation, and improve the transient response capability.

[0085] The above is only a preferred embodiment of the application, and is not intended to limit the scope of the application. The above embodiment of the application can be variously changed. Any simple, equivalent changes and modifications made according to the content of the claims and the description of the application fall within the scope of protection of the patent. The application is not described in detail.

Claims

1. A self-adapting slope-compensated BOOST circuit, characterized in that, It includes a basic BOOST circuit and an adaptive slope compensation circuit, wherein the basic BOOST circuit is configured to receive the input voltage V. in And provide output voltage V out The adaptive slope compensation circuit includes a differential circuit and a slope generation circuit. The differential circuit is configured to generate a current magnitude that is related to the output voltage V. out and input voltage V in The differential current is proportional to the difference, and the ramp generation circuit is configured to generate a slope that is proportional to the output voltage V. out and input voltage V in The difference is proportional to the sawtooth wave voltage; The basic BOOST circuit comprises a power switch tube M1, a synchronous rectifier M2, an energy storage inductor L sw , a first feedback resistor R fb1 , a second feedback resistor R fb2 , an inductor current sampling circuit V sense , an error amplifier EA, a pulse width modulation comparator PWM, a logic circuit, a first driving buffer, a second driving buffer, a load resistor R L , an output capacitor C O , a first voltage source and a second voltage source, the drain of the power switch tube M1 is connected with the drain of the synchronous rectifier M2, and the connection point of the power switch tube M1 and the synchronous rectifier M2 is arranged to receive an induced voltage V sw , one end of the energy storage inductor L sw is connected with the first voltage source to receive an input voltage V in , the other end of the energy storage inductor L sw provides the induced voltage V sw ; the source of the power switch tube M1 is connected with a reference ground voltage GND, the source of the synchronous rectifier M2 is connected with one end of the output capacitor C O , one end of the load resistor R L and a voltage output end, the other end of the output capacitor C O is connected with the reference ground voltage GND, and the other end of the load resistor R L is connected with the reference ground voltage GND; the first feedback resistor R fb1 is connected with the second feedback resistor R fb2 , and the connection point is arranged to provide a feedback voltage V fb , the other end of the first feedback resistor R fb1 is connected with the voltage output end to receive an output voltage V out provided by the voltage output end, the other end of the second feedback resistor R fb2 is connected with the reference ground voltage GND; the positive input end of the error amplifier EA is connected with the second voltage source to receive a reference voltage V ref , and the negative input end receives the feedback voltage V fb ; the negative input end of the pulse width modulation comparator PWM is connected with the output end of the error amplifier EA, and the output end is connected with the input end of the logic circuit; the two output ends of the logic circuit are respectively connected with the input ends of the first driving buffer and the second driving buffer, and the output ends of the first driving buffer and the second driving buffer are respectively connected with the control ends of the synchronous rectifier M2 and the power switch tube M1; the input end of the inductor current sampling circuit V sense is connected with one end of the energy storage inductor L sw providing the induced voltage V sw , to receive an inductor current sampling signal I sense The output signal provided by the output end is superimposed with the output voltage of the adaptive slope compensation circuit and then received by the positive input end of the pulse width modulation comparator PWM; the output voltage of the adaptive slope compensation circuit is the sawtooth voltage V slope ; The differential circuit comprises first, second, third and fourth differential PMOS tubes MP1, MP2, MP3, MP4, first, second, third and fourth differential NMOS tubes MN1, MN2, MN3, MN4, a first current source, a second current source, a third current source, a fourth current source and a first resistor R1; one end of the first current source receives an input voltage V in , the other end is connected to the gates of the first and second differential PMOS tubes MP1, MP2 and the drain of the first differential NMOS tube MN1; one end of the second current source I2 is connected to the input voltage V in , the other end is connected to the gates of the third and fourth differential PMOS tubes MP3, MP4 and the drain of the second differential NMOS tube MN2, the gate of the first differential NMOS tube MN1 is connected to a voltage proportional to the output voltage V out , the source of the first differential NMOS tube MN1 is connected to one end of the third current source, the other end of the third current source is connected to a reference ground voltage GND; the gate of the second differential NMOS tube MN2 is connected to a voltage proportional to the input voltage V in , the source of the second differential NMOS tube MN2 is connected to one end of the fourth current source, the other end of the fourth current source is connected to the reference ground voltage GND; one end of the first resistor R1 is connected to one end of the third current source, the drain of the second differential PMOS tube MP2 and the source of the first differential NMOS tube MN1, the other end of the first resistor R1 is connected to one end of the fourth current source, the drain of the third differential PMOS tube MP3 and the source of the second differential NMOS tube MN2; the sources of the first, second, third and fourth differential PMOS tubes MP1, MP2, MP3 and MP4 receive the input voltage V in , the drain of the first differential PMOS tube MP1 is connected to the drain and gate of the third differential NMOS tube MN3, the source of the third differential NMOS tube MN3 is connected to the reference ground voltage GND; the drain of the fourth differential PMOS tube MP4 is connected to the drain of the fourth differential NMOS tube MN4, the source of the fourth differential NMOS tube MN4 is connected to the reference ground voltage GND; The voltage connected to the gate of the first differential NMOS transistor MN1 is V out / 4; The voltage connected to the gate of the second differential NMOS transistor MN2 is V in / 4; The first fixed current I1 provided by the first current source is equal to the second fixed current I2 provided by the second current source, and the third fixed current I3 provided by the third current source is equal to the fourth fixed current I4 provided by the fourth current source; The slope generation circuit comprises a first slope PMOS tube MP5, a second slope PMOS tube MP6, a slope NMOS tube MN5 and a first capacitor C1, the sources of the first slope PMOS tube MP5 and the second slope PMOS tube MP6 receive an input voltage V in , the drain and the gate of the first slope PMOS tube MP5 are connected, the gate of the second slope PMOS tube MP6, the drains of the fourth differential PMOS tube MP4 and the fourth differential NMOS tube MN4 are connected, the drain of the second slope PMOS tube MP6 is connected to one end of the first capacitor C1 and the drain of the slope NMOS tube MN5, and is set to output an output voltage of the adaptive slope compensation circuit, the gate of the slope NMOS tube MN5 is connected to a clock signal CLK of a basic BOOST circuit, the other end of the first capacitor C1 and the source of the slope NMOS tube MN5 are connected to a reference ground voltage GND; The third differential PMOS tube MP3 and the fourth differential PMOS tube MP4, the second differential PMOS tube MP2 and the first differential PMOS tube MP1, and the third differential NMOS tube MN3 and the fourth differential NMOS tube MN4 respectively constitute current mirrors with a ratio of 1:1; The first slope PMOS tube MP5 and the second slope PMOS tube MP6 constitute a current mirror with a ratio of 1:

1. The first capacitor C1, the first resistor R1 and the energy storage inductor L sw satisfy the relationship: 2R1C1=L sw .

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