Low power level shifting circuit

Abstract

The invention discloses a low-power level conversion circuit, which includes a first PMOS tube, etc. The source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube, and the source of the fourth PMOS tube are connected to each other, the drain of the first PMOS tube, the grid of the third PMOS tube, and the grid of the sixth NMOS tube are all connected to the source of the sixth PMOS tube, the drain of the third PMOS tube and the drain of the third NMOS tube are all connected to the first output signal terminal, the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are all connected to the second output signal terminal, the source of the fifth PMOS tube, the grid of the fourth PMOS tube, and the grid of the fifth NMOS tube are all connected to the drain of the second PMOS tube, and the drain of the fifth PMOS tube and the drain of the fifth NMOS tube are all connected to the grid of the first PMOS tube. The current of the level conversion circuit of the invention is small, and no large short-circuit current loss will be generated.

Description

Technical Field

[0001] The invention relates to a conversion circuit, in particular to a low power consumption level conversion circuit. Background Art

[0002] Traditional level conversion circuits have a higher short-circuit current during the level conversion process, resulting in greater short-circuit current loss. Summary of the invention

[0003] In view of the above situation, in order to overcome the defects of the prior art, the present invention provides a low power consumption level conversion circuit.

[0004] The present invention solves the above technical problems through the following technical solutions: a low-power level conversion circuit, characterized in that it comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, an input signal terminal IN, a first output signal terminal, and a second output signal terminal, the source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube, and the source of the fourth PMOS tube are connected to each other, the drain of the first PMOS tube, the gate of the third PMOS tube, and the gate of the sixth NMOS tube are all connected to the source of the sixth PMOS tube, the drain of the third PMOS tube and the drain of the third NMOS tube are all connected to the first output signal terminal, the drain of the fourth PMOS tube and the drain of the fourth NMOS tube are all connected to the second output signal terminal The source of the fifth PMOS tube, the gate of the fourth PMOS tube, and the gate of the fifth NMOS tube are all connected to the drain of the second PMOS tube, the drain of the fifth PMOS tube and the drain of the fifth NMOS tube are all connected to the gate of the first PMOS tube, the source of the fifth NMOS tube, the drain of the second NMOS tube, and the gate of the fourth NMOS tube are all connected to the gate of the fifth PMOS tube, the drain of the sixth PMOS tube and the drain of the sixth NMOS tube are all connected to the gate of the second PMOS tube, the gate of the third NMOS tube, the source of the sixth NMOS tube, and the drain of the first NMOS tube are all connected to the gate of the sixth PMOS tube, the source of the first NMOS tube, the source of the second NMOS tube, the source of the third NMOS tube, and the source of the fourth NMOS tube are all grounded, an inverter is connected between the gate of the first NMOS tube and the gate of the second NMOS tube, and the gate of the first NMOS tube and the input end of the inverter are all connected to the input signal end.

[0005] Preferably, the gate of the second NMOS tube is connected to the output end of the inverter, and the input signal of the gate of the second NMOS tube is the same as the output end signal of the inverter.

[0006] Preferably, the inverter comprises a first CMOS inverter, a gate of the first NMOS tube is connected to an input terminal of the first CMOS inverter, and a gate of the second NMOS tube is connected to an output terminal of the first CMOS inverter.

[0007] Preferably, the first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, and the sixth PMOS tube are PMOS tubes of the same model, and the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, and the sixth NMOS tube are NMOS tubes of the same model.

[0008] The positive improvement effect of the present invention is that the current of the level conversion circuit of the present invention is small, and no large short-circuit current loss will be generated. The high-voltage power supply current consumed in converting 0-1.2v to 0-2.5v within 1us is reduced from 4.5uA to 0.8uA, and the short-circuit current is no longer the main load. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of a low power level conversion circuit of the present invention. DETAILED DESCRIPTION

[0010] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0011] like Figure 1As shown, the low-power level conversion circuit of the present invention includes a first PMOS tube PH1, a second PMOS tube PH2, a third PMOS tube PH3, a fourth PMOS tube PH4, a fifth PMOS tube PH5, a sixth PMOS tube PH6, a first NMOS tube NH1, a second NMOS tube NH2, a third NMOS tube NH3, a fourth NMOS tube NH4, a fifth NMOS tube NH5, a sixth NMOS tube NH6, an input signal terminal IN, a first output signal terminal OUT, a second output signal terminal OUTN, a source of the first PMOS tube PH1, a second The source of the PMOS tube PH2, the source of the third PMOS tube PH3, and the source of the fourth PMOS tube PH4 are connected to each other, the drain of the first PMOS tube PH1, the gate of the third PMOS tube PH3, and the gate of the sixth NMOS tube NH6 are all connected to the source of the sixth PMOS tube PH6, the drain of the third PMOS tube PH3 and the drain of the third NMOS tube NH3 are all connected to the first output signal terminal OUT, the drain of the fourth PMOS tube PH4 and the drain of the fourth NMOS tube NH4 are all connected to the second output signal terminal OUTN, and the fifth PMOS tube P The source of the fourth PMOS tube PH4, the gate of the fifth NMOS tube NH5 are all connected to the drain of the second PMOS tube PH2, the drain of the fifth PMOS tube PH5 and the drain of the fifth NMOS tube NH5 are all connected to the gate of the first PMOS tube PH1, the source of the fifth NMOS tube NH5, the drain of the second NMOS tube NH2, and the gate of the fourth NMOS tube NH4 are all connected to the gate of the fifth PMOS tube PH5, the drain of the sixth PMOS tube PH6 and the drain of the sixth NMOS tube NH6 are all connected to the gate of the second PMOS tube PH2. The gate of the third NMOS tube NH3, the source of the sixth NMOS tube NH6, and the drain of the first NMOS tube NH1 are all connected to the gate of the sixth PMOS tube PH6, the source of the first NMOS tube NH1, the source of the second NMOS tube NH2, the source of the third NMOS tube NH3, and the source of the fourth NMOS tube NH4 are all grounded, an inverter X1 is connected between the gate of the first NMOS tube NH1 and the gate of the second NMOS tube NH2, and the gate of the first NMOS tube NH1 and the input end of the inverter X1 are all connected to the input signal terminal IN.

[0012] The gate of the second NMOS transistor NH2 is connected to the output end of the inverter X1 , and the input signal of the gate of the second NMOS transistor NH2 is the same as the output end signal of the inverter X1 , which facilitates the connection and transmission of signals.

[0013] The inverter X1 includes a first CMOS inverter, a gate of the first NMOS transistor NH1 is connected to the input end of the first CMOS inverter, and a gate of the second NMOS transistor NH2 is connected to the output end of the first CMOS inverter, so as to facilitate connection and signal transmission.

[0014] The first PMOS tube PH1, the second PMOS tube PH2, the third PMOS tube PH3, the fourth PMOS tube PH4, the fifth PMOS tube PH5, and the sixth PMOS tube PH6 are PMOS tubes of the same model, and the first NMOS tube NH1, the second NMOS tube NH2, the third NMOS tube NH3, the fourth NMOS tube NH4, the fifth NMOS tube NH5, and the sixth NMOS tube NH6 are NMOS tubes of the same model, which is convenient to use.

[0015] When the input signal of the input signal terminal IN is at a low level, the first NMOS tube NH1 is turned off and the second NMOS tube NH2 is turned on, the fourth point D is pulled down to zero level, and the sixth point F and the fourth point D are connected to the NMOS tube and the PMOS tube through the diode, so the sixth point F is pulled down to the MOS tube threshold voltage Vth. Since the fifth PMOS tube PH5 has an obvious substrate bias effect at this time, and the fifth NMOS tube NH5 has almost no substrate bias effect, the threshold voltage of the fifth PMOS tube PH5 is higher, the fifth PMOS tube PH5 is turned off and the fifth NMOS tube NH5 is weakly turned on, and the voltage of the second point B drops to zero potential. Similarly, it can be deduced that the potential of the third point C is HV-Vth, and the potentials of the first point A and the fifth point E are both HV. Therefore, the third PMOS tube PH3 is turned on, the third NMOS tube NH3 is turned off, and the output signal of the first output signal terminal OUT is high level.

[0016] When the input signal of the input signal terminal IN changes from low to high level, the first NMOS tube NH1 is turned on and the second NMOS tube NH2 is turned off. The third point C starts to pull down from HV-Vth. Due to the blocking effect of the sixth NMOS tube NH6 and the sixth PMOS tube PH6 (the sixth PMOS tube PH6 is weakly turned on and the sixth NMOS tube NH6 is weakly turned off), the voltage drop time of the fifth point E lags behind the third point C. Therefore, for the third PMOS tube PH3 and the third NMOS tube NH3 branch, the third NMOS tube NH3 can be quickly turned off, and the third PMOS tube PH3 is turned on later, and the short-circuit current of this branch is very small. Similarly, due to the existence of the sixth PMOS tube PH6 and the sixth NMOS tube NH6, it is equivalent to inserting a large resistor between the first PMOS tube PH1 and the first NMOS tube NH1, so that the short-circuit current of this path is also very small. After the first point A is pulled down, the second PMOS tube PH2 is turned on, the sixth point F is pulled high first, and then the second point B and the fourth point D are pulled high. Similarly, for the fourth PMOS tube PH4 and the fourth NMOS tube NH4 branch, the fourth PMOS tube PH4 is first turned off, and then the fourth NMOS tube NH4 is turned on, and the short-circuit current flowing through the branch is also very small. After the input signal of the input signal terminal IN becomes high, the output signal of the first output signal terminal OUT also becomes a high level. Compared with the conventional design, the current of the level conversion circuit of the present invention is smaller, but the voltage conversion time will increase, but the appropriate sacrifice of delay in exchange for the optimization of power consumption is often more practical in low-power applications.

[0017] When the input signal at the input signal terminal IN changes from a high level to a low level, similar to the above process, the output of the level conversion circuit changes to a low level, and the short-circuit current in this process is also very small.

[0018] The above specific implementation modes are preferred embodiments of the present invention and cannot be used to limit the present invention. Any other changes or other equivalent replacement methods that do not deviate from the technical solution of the present invention are included in the protection scope of the present invention.

Claims

1. A low power level conversion circuit, characterized in that: The invention comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, an input signal terminal IN, a first output signal terminal, and a second output signal terminal. The source of the first PMOS tube, the source of the second PMOS tube, the source of the third PMOS tube, and the source of the fourth PMOS tube are connected to each other. The drain of the first PMOS tube, the gate of the third PMOS tube, and the gate of the sixth NMOS tube are all connected to the source of the sixth PMOS tube. The drain of the third PMOS tube and the drain of the third NMOS tube are all connected to the first output signal terminal. The drain of the fourth PMOS tube and the drain of the fourth NMOS tube are all connected to the second output signal terminal. The source of the fifth PMOS tube, the source of the fourth PMOS tube, and the gate of the sixth NMOS tube are all connected to the source of the sixth PMOS tube. The gate of the fifth NMOS tube and the gate of the fifth NMOS tube are all connected to the drain of the second PMOS tube, the drain of the fifth PMOS tube and the drain of the fifth NMOS tube are all connected to the gate of the first PMOS tube, the source of the fifth NMOS tube, the drain of the second NMOS tube, and the gate of the fourth NMOS tube are all connected to the gate of the fifth PMOS tube, the drain of the sixth PMOS tube and the drain of the sixth NMOS tube are all connected to the gate of the second PMOS tube, the gate of the third NMOS tube, the source of the sixth NMOS tube, and the drain of the first NMOS tube are all connected to the gate of the sixth PMOS tube, the source of the first NMOS tube, the source of the second NMOS tube, the source of the third NMOS tube, and the source of the fourth NMOS tube are all grounded, an inverter is connected between the gate of the first NMOS tube and the gate of the second NMOS tube, and the gate of the first NMOS tube and the input end of the inverter are all connected to the input signal end.

2. The low power level conversion circuit according to claim 1, characterized in that: The gate of the second NMOS tube is connected to the output end of the inverter, and the input signal of the gate of the second NMOS tube is the same as the output end signal of the inverter.

3. The low power consumption level conversion circuit according to claim 1, characterized in that: The inverter comprises a first CMOS inverter, a gate of a first NMOS tube is connected to an input end of the first CMOS inverter, and a gate of a second NMOS tube is connected to an output end of the first CMOS inverter.

4. The low power level conversion circuit according to claim 1, characterized in that: The first PMOS tube, the second PMOS tube, the third PMOS tube, the fourth PMOS tube, the fifth PMOS tube, and the sixth PMOS tube are PMOS tubes of the same model, and the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube, and the sixth NMOS tube are NMOS tubes of the same model.

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