Pipeline analog-to-digital converter and analog-to-digital conversion method

Abstract

The pipeline analog-to-digital converter includes a plurality of converter circuit systems. The plurality of converter circuit systems are used to convert an input signal into a plurality of digital codes in sequence. The plurality of converter circuit systems include a first converter circuit system and a second converter circuit system. The first converter circuit system is used to convert a first signal into a first digital code among the plurality of digital codes, and to generate a first residual signal according to the first signal and the first digital code. The second converter circuit system is used to receive the first signal and the first digital code, to quantize the first signal according to the first digital code to generate a second digital code among the plurality of digital codes, and to generate a second residual signal according to the first residual signal and the second digital code.

Description

Technical Field

[0001] The present invention relates to a pipelined analog-to-digital converter, and more particularly to a pipelined analog-to-digital converter with an extended amplification period and an analog-to-digital conversion method. Background Art

[0002] The pipeline analog-to-digital converter can convert the input signal into the corresponding digital code in sequence through multi-stage conversion. In the prior art, the operation period of each stage of conversion is fixed. As the clock pulse frequency becomes higher and higher, the time of a cycle becomes shorter and shorter. In order for the pipeline analog-to-digital converter to correctly process the conversion result in a very short cycle, some circuits in the pipeline analog-to-digital converter (such as the residual amplifier) ​​need to have a higher current. As a result, the overall power consumption will be higher and the overall circuit area will be larger. Summary of the invention

[0003] In some embodiments, the pipeline analog-to-digital converter includes a plurality of converter circuit systems. The plurality of converter circuit systems are used to convert an input signal into a plurality of digital codes in sequence. The plurality of converter circuit systems include a first converter circuit system and a second converter circuit system. The first converter circuit system is used to convert a first signal into a first digital code among the plurality of digital codes, and to generate a first residual signal according to the first signal and the first digital code. The second converter circuit system is used to receive the first signal and the first digital code to quantize the first signal according to the first digital code to generate a second digital code among the plurality of digital codes, and to generate a second residual signal according to the first residual signal and the second digital code.

[0004] In some embodiments, the analog-to-digital conversion method includes the following operations: converting a first signal into a first digital code, and generating a first residual signal based on the first signal and the first digital code; and quantizing the first signal according to the first digital code to generate a second digital code, and generating a second residual signal based on the first residual signal and the second digital code.

[0005] The features, implementation and effects of the present invention are described in detail below with reference to the drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the present invention;

[0007] Figure 1B According to some embodiments of the present invention, Figure 1A Operation timing diagram of multiple converter circuit systems;

[0008] Figure 2 According to some embodiments of the present invention, Figure 1A A circuit diagram of a plurality of converter circuit systems;

[0009] Figure 3 According to some embodiments of the present invention, Figure 2 Schematic diagram of the Neutron analog-to-digital converter circuit;

[0010] Figure 4 A schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the present invention; and

[0011] Figure 5 The present invention is a flowchart of an analog-to-digital conversion method according to some embodiments of the present invention. DETAILED DESCRIPTION

[0012] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the context of this application, are merely illustrative and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0013] As used herein, "coupled" or "connected" may refer to two or more components making physical or electrical contact directly with each other, or making physical or electrical contact indirectly with each other, or may refer to two or more components operating or acting with each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit, and the term "circuit" may be a device composed of at least one transistor and / or at least one active / passive component connected in a certain manner to process signals.

[0014] As used herein, the term "and / or" includes any combination of one or more of the listed associated items. In this document, the terms first, second, third, etc. are used to describe and distinguish each component. Therefore, the first component in this document can also be referred to as the second component without departing from the original intention of the case. For ease of understanding, similar components in each figure will be designated with the same reference numerals.

[0015] Figure 1A is a schematic diagram of a pipeline analog-to-digital converter 100 according to some embodiments of the present invention, and Figure 1B According to some embodiments of the present invention, Figure 1A Operation timing diagram of converter circuit system 120[1] and converter circuit system 120[2].

[0016] The pipeline analog-to-digital converter 100 includes a sample-and-hold circuit 110, a plurality of converter circuit systems 120[1] to 120[3], a clock pulse generator circuit 130, and a digital correction circuit 140. The sample-and-hold circuit 110 samples an input signal VIN and outputs the sampled input signal VIN as a signal S1. In some embodiments, the sample-and-hold circuit 110 may be implemented by a switched capacitor circuit or a switched capacitor circuit.

[0017] Multiple converter circuit systems 120[1]~120[3] convert the sampled input signal VIN (i.e., signal S1) into multiple digital codes D1[1]~D1[3] in sequence. In detail, converter circuit system 120[1] converts signal S1 to generate digital code D1[1], and generates residual signal S2[1] based on digital code D1[1] and signal S1. Converter circuit system 120[2] receives signal S1, residual signal S2[1] and digital code D1[1]. Converter circuit system 120[2] quantizes signal S1 based on digital code D1[1] to generate digital code D1[2]. Converter circuit system 120[2] also generates residual signal S2[2] based on digital code D1[2] and residual signal S2[1]. The related operations of converter circuit system 120[1] and converter circuit system 120[2] will be referred to later. Figure 2 and Figure 3 In some embodiments, the converter circuit system 120 [ 3 ] may be (but not limited to) a flash analog-to-digital converter circuit, which is used to generate a digital code D1 [ 3 ] according to the residual signal S2 [ 2 ].

[0018] The clock generator circuit 130 is used to generate a plurality of clock signals (not shown) to the sample and hold circuit 110 and the plurality of converter circuit systems 120[1] to 120[3]. In this way, the sample and hold circuit 110 and the plurality of converter circuit systems 120[1] to 120[3] can sequentially perform the above-mentioned plurality of operations according to the plurality of clock signals. The digital correction circuit 140 is used to combine the plurality of digital codes D1[1] to D1[3] to generate a digital code DOUT. In some implementations, the digital correction circuit 140 can be used to correct the offset error and / or gain error of each of the plurality of converter circuit systems 120[1] to 120[3]. In some embodiments, the digital correction circuit 140 can be implemented by a plurality of digital logic circuits.

[0019] In some related technologies, a first-stage converter in a pipeline analog-to-digital converter is configured to convert a previous-stage residual signal to generate a corresponding digital code, and this digital code is only used to generate a corresponding residual signal in the converter of this stage. In these technologies, the converter needs to wait for the previous-stage converter to generate a residual signal before it can perform analog-to-digital conversion. In this way, the operational period of analog-to-digital conversion of each stage of the converter will be limited. Compared with the above-mentioned technology, in some embodiments of the present case, the converter circuit system 120[2] is configured to convert the sampled input signal VIN (i.e., the conversion signal S1 instead of the residual signal S2[1]), and the converter circuit system 120[2] is also configured to directly receive the digital code D1[1]. With this configuration, the converter circuit system 120[2] can enter the amplification period in advance to start generating the residual signal S2[2].

[0020] For example, Figure 1B As shown, when the converter circuit system 120[1] generates the residual signal S2[1] during the amplification period T1, the converter circuit system 120[2] can simultaneously perform analog-to-digital conversion (i.e., generate the digital code D1[2]) and sample the residual signal S2[1] during the sampling and decoding period T2. The converter circuit system 120[1] performs analog-to-digital conversion during the non-overlapping period t1. Compared with the converter circuit system 120[1], the analog-to-digital conversion of the converter circuit system 120[2] is performed during the sampling and decoding period T2 (rather than the non-overlapping time between the sampling and decoding period T2 and the amplification period T3). In this way, the period during which the converter circuit system 120[2] performs analog-to-digital conversion (i.e., generates the digital code D1[2]) can be relaxed, and the converter circuit system 120[2] can enter the amplification period T3 in advance to generate the residual signal S2[2]. With this configuration, the amplification period T3 can be longer than the amplification period T1. In this way, the current of the converter circuit system 120 [2] can be reduced, thereby reducing the overall power and circuit area.

[0021] Figure 2 According to some embodiments of the present invention, Figure 1A Schematic diagram of a converter circuit system 120[1] and a converter circuit system 120[2]. The converter circuit system 120[1] includes a sub-analog-to-digital converter circuit 210 and a multiplying digital to analog converter circuit 220. The sub-analog-to-digital converter circuit 210 is used to convert a signal S1 to generate a digital code D1[1]. In some embodiments, the sub-analog-to-digital converter circuit 210 may be (but not limited to) a flash analog-to-digital converter circuit. The multiplying digital to analog converter circuit 220 is used to process the digital code D1[1] and the signal S1 to generate a residual signal S2[1].

[0022] In detail, the multiplication digital-to-analog converter circuit 220 includes a sub-digital-to-analog converter circuit 220-1, a subtractor circuit 220-2, and a residual amplifier circuit 220-3. The sub-digital-to-analog converter circuit 220-1 can convert the digital code D1[1] into a signal S21. The subtractor circuit 220-2 is used to subtract the signal S21 from the signal S1 to generate a signal S31. The residual amplifier circuit 220-3 can amplify the signal S31 to output a residual signal S2[1]. In some embodiments, the sub-digital-to-analog converter circuit 220-1, the subtractor circuit 220-2, and the residual amplifier circuit 220-3 can be implemented by a switched capacitor circuit or a switched capacitor circuit (not shown). Some switches of the switched capacitor circuit or the switched capacitor circuit are turned on during the sampling period to sample the input signal VIN to obtain the signal S1. Other switches of the switched capacitor circuit or the switched capacitor circuit are turned on during the amplification period T1 to generate the residual signal S2[1].

[0023] The converter circuit system 120[2] includes a sub-ADC circuit 230 and a multiplication DAC circuit 240. The sub-ADC circuit 230 receives a digital code D1[1] and a signal S1, and quantizes the signal S1 according to the digital code D1[1] to generate a digital code D1[2]. In some embodiments, the sub-ADC circuit 230 may be (but not limited to) a successive approximation register (SAR) ADC circuit. The multiplication DAC circuit 240 is used to process the digital code D1[2] and the residual signal S2[1] to generate a residual signal S2[2].

[0024] The multiplication digital-to-analog converter circuit 240 includes a sub-digital-to-analog converter circuit 240-1, a subtractor circuit 240-2, and a residual amplifier circuit 240-3. The sub-digital-to-analog converter circuit 240-1 can convert the digital code D1[2] into a signal S22. The subtractor circuit 240-2 is used to subtract the signal S22 from the residual signal S2[1] to generate a signal S32. The residual amplifier circuit 240-3 can amplify the signal S32 to output a residual signal S2[2]. In some embodiments, the sub-digital-to-analog converter circuit 240-1, the subtractor circuit 240-2, and the residual amplifier circuit 240-3 can be implemented by a switched capacitor circuit or a switched capacitor circuit (not shown). Some switches of the switched capacitor circuit or the switched capacitor circuit are turned on during the sampling and decoding period T2 to sample the residual signal S2[1]. Other switches of the switched capacitor circuit or the switched capacitor circuit are turned on during the amplification period T3 to generate a residual signal S2[2].

[0025] Figure 3 According to some embodiments of the present invention, Figure 2 Schematic diagram of the sub-ADC circuit 230 . In this example, the sub-ADC circuit 230 is a SAR ADC circuit, which includes a comparator circuit 310 , a control logic circuit 320 , and a capacitor array circuit 330 .

[0026] One end of the capacitor array circuit 330 receives a predetermined voltage VCM (or common mode voltage) via the switch SW during the sampling and decoding period T2, and the other end of the capacitor array circuit 330 samples the signal S1 to generate a signal ST. The comparator circuit 310 is used to compare the predetermined voltage VCM with the signal ST to generate a decision signal SD. The control logic circuit 320 performs a binary search algorithm according to the decision signal SD to control the capacitor array circuit 330 to switch in sequence to generate a plurality of bits of the digital code D1[2]. Before the control logic circuit 320 starts switching the capacitor array circuit 330 (i.e., before starting to output the digital code D1[2]), the capacitor array circuit 330 is also used to switch some capacitors (e.g., capacitors C3 to C6) according to the digital code D1[1] to adjust the signal ST.

[0027] In detail, the capacitor array circuit 330 includes a switching circuit 331, a switching circuit 332, and a plurality of capacitors C1-C6. The capacitance values ​​of the plurality of capacitors C1-C6 are C, 2C, 4C, 8C, 16C, and 32C, respectively. In other words, the weight value of capacitor C1 is 1, the weight value of capacitor C2 is 2, ..., and the weight value of capacitor C6 is 32. In some embodiments, the plurality of capacitors C3-C6 with higher weight values ​​correspond to the most significant bit (MSB), and the plurality of capacitors C1-C2 with lower weight values ​​correspond to the least significant bit (LSB).

[0028] The switching circuit 331 includes a plurality of switches for selectively transmitting the signal S1, the reference voltage VREF1 or the reference voltage VREF2 (e.g., the ground voltage or the negative reference voltage) to the plurality of capacitors C3-C6 according to the plurality of bits of the digital code D1[1]. The switching circuit 332 includes a plurality of switches for selectively transmitting the signal S1, the reference voltage VREF1 or the reference voltage VREF2 to the plurality of capacitors C1-C2 according to the control of the control logic circuit 320 (i.e., according to the plurality of bits of the digital code D1[2]). In other words, the plurality of capacitors C3-C6 are controlled by the digital code D1[1] (which is from the previous stage converter circuit system), the plurality of capacitors C1-C2 are controlled by the digital code D1[2] (which is from the current stage converter circuit system), and the weight value corresponding to each of the plurality of capacitors C3-C6 is higher than the weight value corresponding to each of the plurality of capacitors C1-C2. As a result, before the control logic circuit 320 starts switching the capacitor array circuit 330 , the level of the signal ST can be pre-adjusted according to a plurality of bits (in this example, 4 bits) of the digital code D1 [ 1 ].

[0029] Above Figures 1A to 3 In the figure, three converter circuit systems 120[1]-120[3] are used as examples, but the present invention is not limited thereto. In other embodiments, the pipelined analog-to-digital converter 100 may include more converter circuit systems, and the configuration of these converter circuit systems is similar to that of the converter circuit system 120[2]. Figure 3 The SAR analog-to-digital converter circuit is used as an example, but the present invention is not limited thereto. Various sub-analog-to-digital converter circuits 230 that can pre-adjust the signal level according to the digital code D1[1] are all within the scope of the present invention.

[0030] Figure 4Schematic diagram of a pipeline analog-to-digital converter 400 according to some embodiments of the present invention. For example, the pipeline analog-to-digital converter 400 also includes a converter circuit system 120[4], which is coupled between the converter circuit system 120[2] and the converter circuit system 120[3]. The converter circuit system 120[4] generates a digital code D1[4] based on the residual signal S2[1], and generates a residual signal S2[3] based on the digital code D1[4] and the residual signal S2[2]. It should be understood that the configuration of the converter circuit system 120[4] is similar to that of the converter circuit system 120[2]. For example, in the converter circuit system 120[4], the sub-analog-to-digital converter circuit (e.g., the sub-analog-to-digital converter circuit 230) quantizes the previous residual signal S2[1] from the first two converter circuit systems 120[1] according to the digital code D1[2] to generate the digital code D1[4]. Similarly, in converter circuit system 120 [ 4 ], a multiplication digital-to-analog converter circuit (eg, multiplication digital-to-analog converter circuit 240 ) processes digital code D1 [ 2 ] and residual signal S2 [ 2 ] to generate a residual signal S2 [ 3 ].

[0031] For ease of understanding, the operations of the above embodiments are described using a single-ended circuit as an example, but the present invention is not limited thereto. It should be understood that the above embodiments can also be implemented by a differential circuit. In other words, the pipelined analog-to-digital converter 100 (or pipelined analog-to-digital converter 400) implemented by a single-ended circuit or a differential circuit is within the scope of the present invention.

[0032] Figure 5 FIG. 5 is a flow chart of an analog-to-digital conversion method 500 according to some embodiments of the present invention. In some embodiments, the analog-to-digital conversion method 500 may be (but not limited to) Figure 1A The pipeline analog-to-digital converter 100 or Figure 4 The pipelined analog-to-digital converter 400 is executed.

[0033] In operation S510, the first signal is converted into a first digital code, and a first residual signal is generated according to the first signal and the first digital code. Figure 1A and Figure 4 The sampled input signal VIN (i.e., signal S1) in Figure 4 The residual signal S2[1].

[0034] In operation S520 , the first signal is quantized according to the first digital code to generate a second digital code, and a second residual signal is generated according to the first residual signal and the second digital code.

[0035] The description of the above-mentioned operation S510 and operation S520 can refer to the above-mentioned various embodiments, so it is not repeated. The multiple operations of the above-mentioned analog-to-digital conversion method 500 are only examples, and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present case, the various operations under the analog-to-digital conversion method 500 can be appropriately increased, replaced, omitted or performed in a different order. Alternatively, one or more operations under the analog-to-digital conversion method 500 can be performed simultaneously or partially simultaneously.

[0036] In summary, the pipelined analog-to-digital converter and analog-to-digital conversion method in some embodiments of the present invention can relax the operating period limit of analog-to-digital conversion and extend the amplification period of generating the residual signal, thereby saving a certain amount of power and circuit area.

[0037] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. A person with ordinary knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be subject to the scope of the patent application defined in this specification.

[0038] Description of reference numerals:

[0039] 100, 400: Pipeline analog-to-digital converter

[0040] 110: Sample and hold circuit

[0041] 120[1], 120[2], 120[3], 120[4]: Converter circuit system

[0042] 130: Clock pulse generator circuit

[0043] 140: Digital correction circuit

[0044] 210, 230: Sub-analog-to-digital converter circuit

[0045] 220, 240: Multiplication digital-to-analog converter circuit

[0046] 220-1, 240-1: Sub-digital analog converter circuit

[0047] 220-2, 240-2: Subtractor circuit

[0048] 220-3, 240-3: Residual value amplifier circuit

[0049] 310: Comparator Circuit

[0050] 320: Control Logic Circuit

[0051] 330: Capacitor Array Circuit

[0052] 331, 332: Switching circuit

[0053] 500: Analog-to-digital conversion method

[0054] C1~C6:Capacitor

[0055] C, 2C, 4C, 8C, 16C, 32C: capacitance value

[0056] D1[1]~D1[4], DOUT: digital code

[0057] S1, S2, S3, S21, S22, S31, S32, ST: Signal

[0058] S2[1], S2[2], S1[3]: residual signal

[0059] S510, S520: Operation

[0060] SD: Decision Signal

[0061] ST: Signal

[0062] SW: Switch

[0063] T1, T3: Amplification period

[0064] T2: Sampling and decoding period

[0065] t1: non-overlapping period

[0066] VCM: Predetermined voltage

[0067] VIN: Input signal

[0068] VREF1, VREF2: reference voltage

Claims

1. A pipeline analog-to-digital converter, comprising: A plurality of converter circuit systems are used to convert input signals into a plurality of digital codes in sequence, wherein the plurality of converter circuit systems include: a first converter circuit system for converting a first signal into a first digital code among the plurality of digital codes, and generating a first residual signal according to the first signal and the first digital code; and The second converter circuit system is used for receiving the first signal and the first digital code, quantizing the first signal according to the first digital code to generate a second digital code among the plurality of digital codes, and generating a second residual signal according to the first residual signal and the second digital code.

2. The pipelined analog-to-digital converter according to claim 1, wherein the first signal is a corresponding signal of the input signal or a previous residual signal, and the previous residual signal is a residual signal generated by the first two converter circuit systems of the second converter circuit system among the multiple converter circuit systems.

3. The pipelined analog-to-digital converter of claim 1 , wherein the second converter circuit system comprises a SAR analog-to-digital converter circuit, and the SAR analog-to-digital converter circuit is used to quantize the first signal according to the first digital code to generate the second digital code.

4. The pipelined analog-to-digital converter of claim 1 , wherein the second converter circuit system comprises: a sub-analog-to-digital converter circuit, configured to quantize the first signal according to the first digital code to generate the second digital code; as well as The multiplication digital-to-analog converter circuit is used to generate the second residual signal according to the second digital code and the first residual signal.

5. The pipelined analog-to-digital converter according to claim 4, wherein the sub-analog-to-digital converter circuit comprises: a comparator circuit for comparing the second signal with a predetermined voltage to generate a decision signal; A control logic circuit, used for generating the second digital code according to the decision signal; as well as The capacitor array circuit is used to generate the second signal according to the first digital code and the second digital code.

6. The pipelined analog-to-digital converter according to claim 5, wherein the capacitor array circuit comprises a plurality of first capacitors and a plurality of second capacitors, the plurality of first capacitors are controlled by the first digital code, the plurality of second capacitors are controlled by the second digital code, and a weight value corresponding to each of the plurality of first capacitors is higher than a weight value corresponding to each of the plurality of second capacitors. 7 . The pipelined analog-to-digital converter of claim 5 , wherein before the control logic circuit generates the second digital code, the capacitor array circuit is used to adjust the level of the second signal according to the first digital code.

8. The pipelined ADC of claim 1, wherein the first converter circuit system generates the first residue signal in a first amplification period, the second converter circuit system generates the second residue signal in a second amplification period, and the second amplification period is longer than the first amplification period. 9 . The pipelined ADC of claim 1 , wherein the second converter circuit system generates the second digital code and samples the first residue signal in a same period of time.

10. An analog-to-digital conversion method, comprising: Converting a first signal into a first digital code, and generating a first residual signal according to the first signal and the first digital code; as well as The first signal is quantized according to the first digital code to generate a second digital code, and a second residual signal is generated according to the first residual signal and the second digital code.

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