High mobility spin field effect transistor and method of making the same

Abstract

This invention discloses a high-mobility spin field-effect transistor (SFET), comprising a source electrode, a drain electrode, a gate electrode, a semiconductor channel, and a substrate. Compared to existing SFETs based on a single semiconductor channel, this semiconductor channel structure offers advantages such as tunable band structure, high mobility, tunable carrier concentration and type, and long spin diffusion length. Compared to traditional substrate-based SFETs, this invention introduces a substrate with piezoelectric properties, allowing for the modulation of carrier spin transport within the semiconductor channel through the surface polarization electric field of the substrate. This effectively reduces the turn-on or turn-off voltage and improves gate control. Compared to existing SFET fabrication processes, this invention optimizes the crystal quality of the spin tunneling layer, increases carrier spin polarization, thereby improving the device's on / off ratio and reducing operating current.

Description

Technical Field

[0001] This invention relates to the technical field of spin field-effect transistors, and more specifically, to a high-mobility spin field-effect transistor and its fabrication method. Background Technology

[0002] The rapid development of modern information technology is inseparable from the continuous advancements in logic operations, information transmission, and data storage technologies. Over the past fifty years, the miniaturization of semiconductor manufacturing processes has driven the continuous growth of transistor and memory cell densities, following Moore's Law. Spintronics, by manipulating, transmitting, and probing the spin properties of charge carriers, has opened up a new dimension for the utilization of charge carriers, making it a promising new approach to surpass the physical limits of Moore's Law. Compared to controlling charge flow, changing only the electron spin state consumes less energy. Furthermore, electron spin can couple with the helical nature of photons, thereby enabling instantaneous data transmission. Therefore, spintronic devices hold promise as a low-energy, high-speed system solution for future information technology.

[0003] Among numerous spintronic devices, spin field-effect transistors (SFETs) based on semiconductor channel materials such as InGaAs and InAs were the first to come into focus. The SFET was first proposed by S. Datta and B. Das. Unlike conventional field-effect transistors (FETs), SFETs use magnetic materials as source and drain stages. By manipulating the spin precession of electrons through a gate electric field, the spin polarization direction of the electrons diffusing from the source to the drain is either the same as or opposite to the magnetization direction of the drain, thus achieving channel switching. However, only a few publications have reported experimentally fabricated SFETs, and these devices exhibit weak signals and poor switching ratios. The main reasons for this include low spin injection and detection polarization, poor semiconductor spin transport efficiency, and the dependence of spin state modulation on a large gate voltage. To address these issues, efforts should be made in the following areas: First, to achieve effective control of electron spin, electrons in semiconductors must possess large spin diffusion lengths and spin relaxation times. Conventional semiconductor materials exhibit relatively short carrier spin relaxation times (τs(GaN) ~22.5 ps, τs(GaAs) ~86 ps, τs(InAs) ~10 ps) and spin diffusion lengths (λs(GaN) ~137 nm, λs(GaAs) ~1 μm, λs(InAs) ~1.3 μm) at room temperature. Therefore, finding semiconductor materials with longer spin relaxation times, larger spin diffusion lengths, and higher carrier mobility is a crucial prerequisite for improving the performance of spintronic devices.

[0004] Secondly, high-performance spin field-effect transistors rely on the high polarization of spin electrons for injection and detection. Due to the impedance discontinuity effect at the semiconductor / ferromagnetic metal interface, the highest spin polarization can only be achieved when the contact resistance is close to the spin channel resistance. Typically, a very thin (1-2 nm) dielectric layer is inserted at the interface to form a magnetic tunnel junction as the spin detection electrode. Magnetic tunneling electrodes using MgO (001) tunneling layers have extremely high spin polarization (92.6% at room temperature, corresponding to a tunneling magnetoresistance of 604%), and are commonly used spin injection and detection structures in semiconductor spin devices. MgO films grown by conventional methods are usually amorphous. To transform them into polycrystalline or single-crystal structures with a (001) lattice orientation, high-temperature annealing in a vacuum is required. However, ferromagnetic metals generally cannot withstand high temperatures, and the annealing temperature needs to be limited to below 350 degrees Celsius, affecting the crystal quality of the dielectric film and resulting in typically low polarization for spin injection and detection. Therefore, it is necessary to design the annealing process in a reasonable way to improve the crystal quality of the tunneling layer as much as possible without affecting the magnetic properties of the ferromagnetic metal.

[0005] Finally, traditional Datta-Das spin field-effect transistors (SFETs) primarily rely on controlling the precession of spin electrons under an electric field through a gate electric field, thereby manipulating their spin polarization direction as they drift from the source to the drain. Due to the relatively short spin diffusion length of semiconductors, a large gate electric field is typically required to enable electrons to achieve spin polarization reversal within a limited drift distance. This necessitates a large turn-off voltage for the SFET, limiting its performance. Therefore, it is necessary to explore how to obtain the largest possible gate electric field under reasonable gate voltage conditions. Summary of the Invention

[0006] To address the aforementioned technical problems in related technologies, this invention provides a high-mobility spin field-effect transistor and its fabrication method, which can solve the above problems.

[0007] This invention addresses the problems faced by existing spin field-effect transistor structures and fabrication technologies: Question 1: The realization of spin field-effect transistors relies on the efficient transport of spin electrons in semiconductor channels. However, the carrier spin relaxation time at room temperature in conventional semiconductor materials is relatively short, often on the order of picoseconds. Thus, carriers lose their spin polarization after a short period of transport within the semiconductor channel, making them undetectable. Therefore, it is necessary to select a suitable semiconductor material or structure as the carrier transport channel to ensure that spin polarization is not lost during the carrier drift from the source to the drain.

[0008] Solution: To address the poor electron spin transport efficiency in spin field-effect transistor devices, a proposed solution is to utilize semiconductor heterojunctions, quantum wells, or two-dimensional electron gas structures in two-dimensional materials as semiconductor channels (e.g., Figure 3-8In this structure, carrier transport is confined to a thin two-dimensional space, exhibiting characteristics of a two-dimensional electron gas or a two-dimensional hole gas. This semiconductor channel may comprise at least one semiconductor A thin film layer, a heterojunction comprising at least one combination of semiconductor B and semiconductor C thin film layers (where the band gaps of semiconductor B and semiconductor C thin film layers are generally different and form a type I heterojunction), or a quantum well comprising at least one combination of semiconductor D, semiconductor E, and semiconductor F thin film layers (where the band gaps of semiconductor D and semiconductor F thin film layers should be greater than that of semiconductor E thin film layer).

[0009] Question 2: High-performance spin field-effect transistors require the injection of carriers with high spin polarization into the semiconductor channel and the ability to sensitively detect the spin polarization direction of these carriers. Currently, spin tunneling electrodes with ferromagnetic metal / dielectric material structures are typically used as the injection and detection electrodes for spin current. In current fabrication processes, to improve the crystal quality of the dielectric material, vacuum annealing is usually performed after depositing the dielectric material and ferromagnetic metal. However, the magnetic metal layer cannot withstand high temperatures, limiting the annealing temperature to below 350 degrees Celsius. This results in the dielectric film not being able to fully crystallize, and the spin injection and detection efficiency remains poor.

[0010] Solution: Spintronic devices rely on spin tunneling layers with ferromagnetic metal / dielectric material structures to inject spin current into semiconductor channels. However, due to limitations in the crystal quality of the dielectric material, spin injection efficiency is typically poor. To improve the crystal quality of the dielectric material, vacuum annealing is commonly used; however, the magnetic metal layer cannot withstand high temperatures, limiting the annealing temperature to below 350 degrees Celsius, which affects the crystal quality of the dielectric film. This invention proposes an in-situ layered annealing process for growing source and drain electrodes. First, a tunneling layer is grown or transferred on the semiconductor channel surface, and then fully crystallized through in-situ high-temperature annealing. Subsequently, a magnetic layer and capping layer are grown after cooling, and finally, low-temperature magnetic field annealing is used to control the magnetic anisotropy of the magnetic layer.

[0011] Question 3: Traditional Datta-Das spin field-effect transistors primarily rely on controlling the precession of spin electrons under an electric field through a gate electric field, thereby manipulating their spin polarization direction as they drift from the source to the drain. Due to the relatively short spin diffusion length of semiconductors, a relatively large gate voltage is typically required to enable electrons to achieve spin polarization reversal within a limited drift distance. This higher gate voltage impacts device performance and increases the risk of gate leakage.

[0012] Solution: Traditional Datta-Das spin field-effect transistors (SFETs) primarily rely on controlling the precession of spin electrons under an electric field through the gate electrode, thereby manipulating their spin polarization direction as they drift from the source electrode to the drain electrode. Due to the relatively short spin diffusion length of semiconductors, a large gate voltage is typically required to achieve spin polarization reversal within a limited drift distance. In this invention, the semiconductor channel is grown on a piezoelectric substrate, which may be a thin sheet of material with piezoelectric properties or a piezoelectric thin film grown on other substrates. When a gate voltage is applied, a surface polarization field several times larger than the gate electric field is generated on the piezoelectric material surface, thus enabling effective control of electron spin precession under relatively low gate voltage conditions.

[0013] The beneficial effects of the present invention are as follows: (1) Compared with the existing spin field-effect transistors based on a single semiconductor channel, the present semiconductor channel structure has the advantages of adjustable band structure, high mobility, adjustable carrier concentration and type, and long spin diffusion length; (2) Compared with the spin field-effect transistor based on a traditional substrate, the present invention introduces a substrate with piezoelectric properties, which can regulate the spin transport of carriers in the semiconductor channel through the surface polarization electric field of the substrate, effectively reducing the turn-on or turn-off voltage and improving the gate control effect; (3) Compared with the existing spin field-effect transistor fabrication process, the present invention can optimize the crystal quality of the spin tunneling layer, improve the spin polarization of carriers, thereby improving the on / off ratio of the device and reducing the operating current. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] The present invention will now be described in further detail with reference to the accompanying drawings.

[0016] Figure 1 This is a high-mobility spin field-effect transistor (the gate electrode is located on the semiconductor channel) as described in the embodiments of the present invention. Figure 2 This is a high-mobility spin field-effect transistor (gate electrode located on substrate) as described in an embodiment of the present invention. Figure 3 This is a simplified diagram of the semiconductor thin film layer structure described in an embodiment of the present invention; Figure 4 This is a simplified diagram of the combined structure of semiconductor B thin film layer and semiconductor C thin film layer according to an embodiment of the present invention; Figure 5This is a simplified diagram of the combined layer structure of semiconductor D thin film layer, semiconductor E thin film layer and semiconductor J thin film layer as described in the embodiments of the present invention; Figure 6 This is as described in the embodiments of the present invention. Figure 3 A schematic diagram of the band structure corresponding to the structure; Figure 7 This is as described in the embodiments of the present invention. Figure 4 A schematic diagram of the band structure corresponding to the structure; Figure 8 This is as described in the embodiments of the present invention. Figure 5 A schematic diagram of the band structure corresponding to the structure; Figure 9 This is a simplified structural diagram of the source electrode or drain electrode according to an embodiment of the present invention; Figure 10 This is a simplified diagram of the magnetic material A thin film layer structure described in an embodiment of the present invention; Figure 11 This is a simplified structural diagram of the combined layer of magnetic material B thin film and non-magnetic material thin film as described in the embodiments of the present invention; Figure 12 This is a simplified structural diagram of the composite layer of magnetic material C thin film and magnetic material D thin film as described in the embodiments of the present invention; Figure 13 This is a flowchart of a high-mobility spin field-effect transistor fabrication method according to an embodiment of the present invention.

[0017] In the figure: 10, source electrode; 11, capping layer; 12, magnetic layer; 13, tunneling layer; 20, drain electrode; 21, magnetic material A thin film layer; 22, magnetic material B thin film layer; 23, non-magnetic material thin film layer; 24, magnetic material C thin film layer; 25, magnetic material D thin film layer; 30, gate electrode; 40, semiconductor channel; 41, semiconductor A thin film layer; 42, semiconductor B thin film layer; 43, semiconductor C thin film layer; 44, semiconductor D thin film layer; 45, semiconductor E thin film layer; 46, semiconductor F thin film layer; 50, substrate; E C , Conductor belt bottom; E V Price band top; E F Fermi level. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0019] like Figure 1-13As shown, a high-mobility spin field-effect transistor according to an embodiment of the present invention includes a source electrode 10, a drain electrode 20, a gate electrode 30, a semiconductor channel 40, and a substrate 50. The substrate 50 includes a thin film or sheet made of a piezoelectric material. The semiconductor channel 40 is located on the substrate 50 and is made of a semiconductor material with a two-dimensional electron gas structure or a heterojunction semiconductor material. The source electrode 10 and the drain electrode 20 are located on the semiconductor channel 40. Both the source electrode 10 and the drain electrode 20 include a capping layer 11, a magnetic layer 12, and a tunneling layer 13. The gate electrode 30 is located on the semiconductor channel 40 or on the substrate 50 and includes an electrode layer and an insulating layer.

[0020] In one embodiment of the present invention, the substrate 50 may be a thin sheet of material with piezoelectric properties, or a piezoelectric thin film grown on other substrates. The piezoelectric material includes SiO2, GaN, ZnO, BaTiO3, and PbZr. x Ti 1-x O3, LiGaO2, GeLi2O3, Pb(Mg) 1 / 3 Nb 2 / 3 O3, polyvinylidene fluoride (PVDF), and their related compounds or polymers. When a gate voltage is applied, the surface of the piezoelectric material generates a surface polarization field several times larger than the gate electric field, thereby enabling effective control of electron spin precession under relatively low gate voltage conditions.

[0021] In one embodiment of the present invention, the semiconductor channel 40 is selected from semiconductor materials or heterojunctions with a two-dimensional electron gas structure. This semiconductor channel 40 may include at least one semiconductor A thin film layer 41, a heterojunction comprising at least one combination of semiconductor B thin film layers 42 and semiconductor C thin film layers 43 (wherein the band gaps of semiconductor B thin film layers 42 and semiconductor C thin film layers 43 are generally different and form a type I heterojunction), or a quantum well comprising at least one combination of semiconductor D thin film layers 44, semiconductor E thin film layers 45, and semiconductor He thin film layers 46 (wherein the band gaps of semiconductor D thin film layers 44 and semiconductor He thin film layers 46 should be greater than that of semiconductor E thin film layer 45), with each thin film layer having a thickness of 0.1-100 nm. The semiconductor A thin film layer 41, semiconductor B thin film layer 42, semiconductor C thin film layer 43, semiconductor D thin film layer 44, semiconductor E thin film layer 45, and semiconductor He thin film layer 46 may be: elemental semiconductors (such as Si, Ge, B, Sn, Te, Se, Sb and their compounds), or III-V group compound semiconductors (such as GaN, AlN, Al...). x Ga (1-x)Semiconductors include N, GaAs, InAs, GaP, InP and their compounds, IIB-VIA group compound semiconductors (such as ZnO and its related compounds), III-VI group compound semiconductors (Ga2O3 and its related compounds), IV-IV group compound semiconductors (such as SiC and its related compounds), and two-dimensional semiconductors (such as layered Sn, Te, Se, Sb, and black phosphorus). The semiconductor channel 40 may be a planar or curved thin film, or a three-dimensional fin-type thin layer, nanosheet, or nanowire.

[0022] In one embodiment of the present invention, both the source electrode 10 and the drain electrode 20 are multilayer thin film structures composed of a capping layer 11, a magnetic layer 12, and a tunneling layer 13. The tunneling layer 13 contacts the semiconductor channel 40. Depending on the shape of the semiconductor channel 40, the source electrode 10 and the drain electrode 20 may be stacked on top of the semiconductor channel 40, or they may be in side contact or partially or completely encapsulated. The spacing between the source electrode 10 and the drain electrode 20 is 1-2000 nm, and their material composition may be the same, partially the same, or different. The capping layer 11 is typically one or more layers of highly stable metals and their alloys or non-metallic materials, such as Au, Ru, Al, Rh, Ir, Os, Re, Cd, Mo, Zr, Ta, Pt, Ag, Cu, Hf, W, Pd, Cr, V, Ta2O5, Al2O3, TiO2, and MgO, with a thickness of approximately 1-100 nm. The magnetic layer 12 is typically one or more layers of ferromagnetic or ferrimagnetic material. The magnetic layer 12 includes at least one layer of magnetic material A thin film 21, at least one combination layer of magnetic material B thin film 22 and non-magnetic material thin film 23, or at least one combination layer of magnetic material C thin film 24 and magnetic material D thin film 25 (magnetic material C thin film 24 and magnetic material D thin film 25 are two different materials. Through this structure, composite magnetic films can be constructed using two or more materials with different magnetic anisotropy and saturation magnetization, so as to freely control the direction of the easy magnetization axis and the magnitude of the saturation magnetization of the composite film. Among them, the magnetic material A thin film layer 21, magnetic material B thin film layer 22, magnetic material C thin film layer 24, and magnetic material D thin film layer 25 may be Fe, Co, Ni, Mn, FeCo, NiFe, CoFeB, NiFeCuMo, Ni2MnGa, Co2FeAl, Co2CrSi, NiMnSb, Co2(Fe,Mn)Si, Co2Fe(AlSi), Co2Fe(GeGa) or alloys containing the above materials, with each thin film layer having a thickness of approximately 0.1–50 nm; the non-magnetic material 23 may be Au, Ru, Rh, Al, Ir, Os, Re, Cd, Mo, Zr, Ta, Pt, Ag, Cu, Hf, W, Pd, Cr, V, Ta2O5, Al2O3, TiO2, or MgO, with each thin film layer having a thickness of approximately 0.1–50 nm. The tunneling layer 13 is typically a thin insulating or semiconductor material, such as MgO, AlOx, SiO2, MgAl2O4, AlN, TiO2, or a two-dimensional material, with a thickness of 0.1–5 nm.

[0023] In one embodiment of the present invention, the gate electrode 30 is typically located between the source electrode 10 and the drain electrode 20, and is composed of an electrode layer and an insulating layer. It may be located above the semiconductor channel 40 or below the substrate 50, wherein the insulating layer contacts the semiconductor channel 40 or the substrate 50. Depending on the shape of the semiconductor channel 40, the gate electrode 30 may be stacked above the semiconductor channel 40, or it may be in lateral contact or partially or completely enclosed by the channel. The electrode layer is composed of a conductive metal or semiconductor, with a thickness of 1-100 nm, and the insulating layer may be a semiconductor or insulator with poor conductivity, with a thickness of 1-100 nm.

[0024] A high-mobility spin field-effect transistor and its fabrication method are disclosed, comprising the following fabrication steps: preparing a substrate; growing a semiconductor channel; surface treatment of the semiconductor channel; growing a tunneling layer for the source and drain electrodes; high-temperature annealing; growing a magnetic layer and a capping layer for the source and drain electrodes; photolithography, etching, and defining the source and drain electrode patterns; growing and stripping the gate electrode; and low-temperature magnetic field annealing.

[0025] Substrate preparation refers to the cleaning and surface treatment of substrate 50, specifically including processing silicon wafers, sapphire or glass substrates through RCA cleaning process and growing the aforementioned piezoelectric thin films on their surface (generating a substrate with piezoelectric properties), or cleaning piezoelectric material sheets that have been cut into thin sheets (directly using the piezoelectric material sheets as a substrate with piezoelectric properties), and performing pretreatments such as plasma treatment and ultraviolet irradiation on their surfaces to remove surface organic contamination and oxidation.

[0026] Semiconductor channel 40 growth refers to the growth of semiconductor channel 40 on substrate 50 using thin film growth processes such as pulsed laser deposition, chemical vapor deposition, magnetron sputtering, atomic layer deposition, molecular beam epitaxy, metal-organic chemical vapor deposition, thermal evaporation, and electron beam evaporation. Semiconductor channel 40 may be one or more materials and includes the aforementioned materials and structural layers of semiconductor channel 40.

[0027] Semiconductor channel 40 surface treatment refers to the use of plasma treatment, particle beam bombardment, high-energy ray irradiation and other methods to remove contaminants and oxide layers from the surface of semiconductor channel 40, which helps with subsequent contact with source and drain electrodes.

[0028] The growth of the tunneling layer 13 of the source and drain electrodes refers to the growth of the tunneling layer 13 in the aforementioned source electrode 10 and drain electrode 20 on the surface of the semiconductor channel using thin film growth processes such as magnetron sputtering, atomic layer deposition, thermal evaporation, and electron beam evaporation; or the transfer of the grown tunneling layer 13 to the surface of the semiconductor channel 40 through physicochemical transfer. Physical transfer can use dry transfer printing, an experimental method used to prepare van der Waals heterojunctions. Specifically, it is an experimental method that uses an adhesive polymer to transfer an arbitrary two-dimensional material to the surface of another material. The materials are bonded together by weak van der Waals forces, without any lattice matching. Chemical transfer can use etching, electrochemical bubbling, etc.

[0029] High-temperature annealing refers to annealing in a vacuum or under a specific atmosphere. The annealing temperature is ideal for achieving the best crystal quality in the tunneling layer 13, typically between 200-500 ºC, and the annealing time is 10-240 minutes. Before reaching the specified annealing temperature, the temperature needs to be gradually increased from room temperature to the specified temperature at a rate of 0.1–20 ºC / min. After annealing, the temperature also needs to be gradually decreased to room temperature at a rate of 0.1–20 ºC / min to improve crystal quality and reduce internal stress in the film.

[0030] The growth of the magnetic layer and capping layer of the source and drain electrodes refers to the use of thin film growth processes such as pulsed laser deposition, chemical vapor deposition, magnetron sputtering, atomic layer deposition, molecular beam epitaxy, metal-organic chemical vapor deposition, thermal evaporation, and electron beam evaporation to grow the magnetic layer 12 and capping layer 11 sequentially on the tunneling layer 13; or to transfer the grown magnetic layer 12 or capping layer 11 to the surface of the tunneling layer 13 sequentially through physicochemical transfer.

[0031] Photolithography, etching, and defining source and drain electrode patterns refer to defining the shape of the source electrode 10 and drain electrode 20 through optical exposure, electron beam exposure, ion beam exposure, hard mask, etc., and using etching processes such as plasma etching, chemical etching, ion milling, and laser lift-off to remove the capping layer, magnetic layer, and tunneling layer film outside the source and drain electrode area, leaving only the source and drain electrode parts defined by photolithography.

[0032] Gate electrode growth and lift-off refers to the process of first defining the shape and position of the gate electrode 30 on the back side of the substrate 50 or the surface of the semiconductor channel 40 using methods such as optical exposure, electron beam exposure, ion beam exposure, and hard masking. Then, using thin film growth processes such as pulsed laser deposition, chemical vapor deposition, magnetron sputtering, atomic layer deposition, molecular beam epitaxy, metal-organic chemical vapor deposition, thermal evaporation, and electron beam evaporation, the insulating layer and electrode layer of the gate electrode 30 are sequentially grown on the back side of the substrate 50 or the upper surface of the semiconductor channel 40. Subsequently, based on a chemical lift-off process, an organic solution is used to remove the previously defined photoresist or hard mask, as well as the insulating layer and electrode film attached to its surface, finally fabricating the gate electrode 30 in the device.

[0033] Low-temperature magnetic field annealing refers to annealing in a vacuum or under a specific atmosphere. During annealing, a magnetic field of 0.01–20 T can be applied to achieve relatively uniform magnetization of the magnetic layer 12 in the source electrode 10 and drain electrode 20. The annealing temperature should not significantly degrade the properties of the metallic material, generally between 100–350 ºC, and the annealing time should be 30–120 minutes. Before reaching the specified annealing temperature, the temperature needs to be gradually increased from room temperature to the specified temperature at a rate of 0.1–20 ºC / min. After annealing, the temperature also needs to be gradually decreased to room temperature at a rate of 0.1–20 ºC / min to improve crystal quality and reduce film internal stress.

[0034] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-mobility spin field-effect transistor, comprising a source electrode (10), a drain electrode (20), a gate electrode (30), a semiconductor channel (40), and a substrate (50), characterized in that: The substrate (50) is a thin sheet made of a piezoelectric material, or the substrate is formed by growing a thin film with piezoelectric properties on other substrates. The semiconductor channel (40) is located on the substrate (50). The semiconductor channel (40) is made of a semiconductor material with a two-dimensional electron gas structure. The source electrode (10) and the drain electrode (20) are located on the semiconductor channel (40). The source electrode (10) and the drain electrode (20) each include a capping layer (11), a magnetic layer (12) and a tunneling layer (13). The gate electrode (30) is located on the semiconductor channel (40) or on the substrate (50). The gate electrode (30) includes an electrode layer and an insulating layer.

2. The high-mobility spin field-effect transistor according to claim 1, characterized in that: The semiconductor channel (40) is a planar or curved thin film; the semiconductor channel (40) is a multilayer thin film structure, comprising at least one semiconductor A thin film layer (41), at least one set of semiconductor B thin film layers (42) and semiconductor C thin film layers (43) combined layer or at least one set of semiconductor D thin film layers (44), semiconductor E thin film layers (45) and semiconductor F thin film layers (46) combined layer; the thickness of semiconductor A thin film layer (41), semiconductor B thin film layer (42), semiconductor C thin film layer (43), semiconductor D thin film layer (44) and semiconductor E thin film layer (45) is 0.1-100 nm.

3. A high-mobility spin field-effect transistor according to claim 1, characterized in that: The semiconductor channel (40) is in the shape of a three-dimensional fin-shaped thin layer, nanosheet, or nanowire.

4. A high-mobility spin field-effect transistor according to claim 2, characterized in that: The semiconductor A thin film layer (41), the semiconductor B thin film layer (42), the semiconductor C thin film layer (43), the semiconductor D thin film layer (44), the semiconductor E thin film layer (45), and the semiconductor F thin film layer (46) are elemental semiconductors, III-V compound semiconductors, IIB-VIA compound semiconductors, III-VI compound semiconductors, or IV-IV compound semiconductors; the combined layer of the semiconductor B thin film layer (42) and the semiconductor C thin film layer (43) forms a type I heterojunction, and the band gap of the semiconductor D thin film layer (44) and the semiconductor F thin film layer (46) is greater than that of the semiconductor E thin film layer (45).

5. A high-mobility spin field-effect transistor according to claim 1, characterized in that: The capping layer (11) has a thickness of 1-100 nm; the magnetic layer (12) is a multilayer thin film structure, comprising at least one layer of magnetic material A thin film (21), at least one group of magnetic material B thin film (22) and a combination layer of non-magnetic material thin film (23), or at least one group of magnetic material C thin film (24) and magnetic material D thin film (25); the thickness of the magnetic material A thin film (21), the magnetic material B thin film (22), the non-magnetic material thin film (23), the magnetic material C thin film (24) and the magnetic material D thin film (25) is 0.1-50 nm; the tunneling layer (13) is made of an insulator or semiconductor material and has a thickness of 0.1-5 nm.

6. A high-mobility spin field-effect transistor according to claim 1, characterized in that: The electrode layer is made of a conductive metal or semiconductor and has a thickness of 1-100 nm; the insulating layer is made of a semiconductor or insulator with poor conductivity and has a thickness of 1-100 nm.

7. A method for fabricating a high-mobility spin field-effect transistor, characterized in that: The process includes the following steps: S1. Processing a silicon wafer, sapphire, or glass substrate using an RCA cleaning process, and growing a thin film with piezoelectric properties on the surface of the processed silicon wafer, sapphire, or glass substrate to generate a piezoelectric substrate (50), or directly fabricating the piezoelectric substrate by cutting it into thin sheets of piezoelectric material, and performing plasma treatment and ultraviolet irradiation pretreatment on the entire surface of the piezoelectric substrate to remove surface organic contamination and oxidation; S2. Growing a semiconductor channel (40) on the substrate (50) using a thin film growth process; S3. S4. Using plasma treatment, particle beam bombardment, or high-energy ray irradiation, remove contaminants and oxide layers from the surface of the semiconductor channel (40); S5. Using thin film growth process, grow tunneling layers (13) for the source electrode (10) and drain electrode (20) on the surface of the semiconductor channel (40), or transfer the grown tunneling layer (13) to the surface of the semiconductor channel (40) by physicochemical transfer; S6. Anneal the tunneling layer (13) in vacuum or atmosphere at an annealing temperature of 200-500 ºC for 10-240 minutes. Before reaching the specified annealing temperature, the temperature needs to be gradually increased from room temperature to the specified annealing temperature at a rate of 0.1-20 ºC / min. After annealing, the annealing temperature also needs to be gradually decreased to room temperature at a rate of 0.1-20 ºC / min. ºC / min; S6. Using a thin film growth process, the magnetic layer (12) and the capping layer (11) are sequentially grown on the tunneling layer (13), or the grown magnetic layer (12) or capping layer (11) is sequentially transferred to the surface of the tunneling layer (13) by a physicochemical transfer method; S7. The shape of the source electrode (10) and the drain electrode (20) is defined by a photolithography process, and the thin film of the capping layer (11), the magnetic layer (12) and the tunneling layer (13) located outside the area defined by the photolithography process in this step is removed by an etching process, leaving only the source electrode (10) defined by the photolithography process in this step. S8. Define the shape and position of the gate electrode (30) on the back side of the substrate (50) or the surface of the semiconductor channel (40) by photolithography. Then, using a thin film growth process, grow the insulating layer and the electrode layer in the gate electrode (30) sequentially on the back side of the substrate (50) or the surface of the semiconductor channel (40). Then, based on a chemical lift-off process, use an organic solution to remove the thin film outside the area defined by the photolithography process in this step, and finally fabricate the gate electrode (30) in the device. S9. Anneal in a vacuum or atmosphere, applying 0 during the annealing process.An annealing process is conducted under a magnetic field of 0.1–20 T, with an annealing temperature of 100–350 ºC and an annealing time of 30–120 minutes. Before reaching the specified annealing temperature, the temperature needs to be gradually increased from room temperature at a rate of 0.1–20 ºC / min. After annealing, the temperature also needs to be gradually decreased to room temperature at a rate of 0.1–20 ºC / min.

8. The method for fabricating a high-mobility spin field-effect transistor according to claim 7, characterized in that: The thin film growth processes in S2, S4, S6 and S8 include pulsed laser deposition, chemical vapor deposition, magnetron sputtering, atomic layer deposition, molecular beam epitaxy, metal-organic chemical vapor deposition, thermal evaporation or electron beam evaporation.

9. The method for fabricating a high-mobility spin field-effect transistor according to claim 7, characterized in that: The photolithography processes in steps S7 and S8 include optical exposure, electron beam exposure, ion beam exposure, or hard masking; the etching processes in step S7 include plasma etching, chemical etching, ion milling, or laser lift-off.

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