A half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit and comparison method

Abstract

A half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit and comparison method, relates to the field of semiconductor technology chip design, the circuit includes a comparator and a capacitor array at the input end of the comparator, a configuration voltage and a logic switch, the circuit is a two-terminal input structure; the capacitor array is two groups, each group includes an upper capacitor array and a lower capacitor array, and the upper and lower capacitor arrays are consistent, from the third to the last capacitor, the capacitance value is the sum of all the capacitance values ​​before the current capacitor; the configuration voltage is Vin, Vip, Vref, gnd, and the logic switch is installed between the capacitor and the configuration voltage to realize the switching of the configuration voltage during the comparison process. The present invention makes the input voltage of the comparator, that is, the voltage from the capacitor array, halved during operation, thereby reducing the excessive input voltage, helping the comparator to select transistors with low-voltage technology, and select a lower power supply voltage, which helps to save the power consumption of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology chip design, and more specifically, to a successive approximation analog-to-digital conversion circuit. Background Art

[0002] Successive approximation ADC includes n-bit successive approximation A / D conversion. The traditional successive approximation mode differential analog-to-digital conversion circuit is as follows Figure 1 As shown, there are two symmetrical capacitor arrays. One end of the capacitors is connected together and connected to a section of the comparator, where the upper capacitor array connection point is Vp.

[0003] like Figure 1-3 As shown in the figure, it is a schematic diagram of the traditional successive comparison circuit and the comparison process. In sampling, Vp=Vn=Vref. In comparison 1, Vp=3 / 2Vref-Vin, Vn=3 / 2Vref-Vip, Vp-Vn=Vip-Vin. It can be seen that the maximum value of the Vp voltage can be close to 1.5 times of Vref. Vref is the reference voltage selected by the comparator. Vref directly determines the input operating range of the analog-to-digital conversion circuit. Generally, the maximum value is selected as the power supply voltage. Assuming the power supply voltage is 2v, Vp may exceed 2v.

[0004] The specific comparison process is explained using a 2-bit successive approximation analog-to-digital conversion process.

[0005] From left to right: acquisition - input differential voltage value; comparison 1 - highest bit comparison; comparison 2: second highest bit comparison;

[0006] The switches of the capacitor array in each stage are connected to the corresponding bias voltages, thereby obtaining the voltage values ​​of Vp and Vn, which are marked next to them.

[0007] Comparison 1: The comparator input positive and negative comparison is actually the comparison of Vip and Vin. For differential input, it compares the positive and negative input voltages Vp-Vn=Vip-Vin.

[0008] Comparison 2: If Vip is greater than Vin, the upper comparison is performed to obtain the high value. From the equation, it can be seen that the actual result is whether the differential input is greater than 0.5Vref. If Vip is less than Vin, the lower comparison is performed to obtain whether the differential input is less than -0.5Vref:

[0009] That is, in the upper capacitor array of comparison 2:

[0010] Vp=5 / 4Vref-Vin, Vn=7 / 4Vref-Vip, Vp-Vn=(Vip-Vin)-1 / 2Vref;

[0011] Compare the lower capacitor array of 2:

[0012] Vp=7 / 4Vref-Vin, Vn=5 / 4Vref-Vip, Vp-Vn=(Vip-Vin)-(-1 / 2Vref);

[0013] The process of comparing voltages can be found in Figure 3 Finally, it is confirmed that the differential input is in one of the four segments (Vref, -Vref); from the above process, it can be seen that the value of Vp or Vn may be greater than Vref, that is, greater than the power supply voltage, which is not good for the circuit components.

[0014] Although to a certain extent, loading this voltage on the input of the comparator circuit will not cause damage quickly, it can easily cause accelerated aging of the device and increase leakage, affecting the performance of the analog-to-digital conversion circuit. Summary of the invention

[0015] The purpose of the present invention is to propose a half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit to address the problems that components in a traditional successive approximation mode AD conversion circuit are prone to aging and leakage, which will affect the analog-to-digital conversion performance.

[0016] The technical solution of the present invention is:

[0017] The present invention provides a half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit, the circuit comprising a comparator and a capacitor array at the input end of the comparator, a configuration voltage and a logic switch, the circuit being a double-end input structure;

[0018] The capacitor array consists of two groups, each group includes an upper capacitor array and a lower capacitor array, and the upper and lower capacitor arrays are consistent, both C, C to 2 n C, from the third capacitor to the last capacitor, the capacitance value is the sum of all the capacitance values ​​before the current capacitor; the configuration voltage is Vin, Vip, Vref, gnd, and the logic switch is installed between the capacitor and the configuration voltage to realize the switching of the configuration voltage during the comparison process;

[0019] Wherein: the upper half of the logic switch of one group of capacitor arrays is configured as spa, and the lower half is configured as sna, the upper half of the logic switch of another group of capacitor arrays is configured as spb, and the lower half is configured as snb, the number of comparisons is the number of bits, and during the comparison process, the logic switch performs the following operations:

[0020] During sampling, in the upper capacitor array, the logic switch spa is closed to Vin, and the logic switch spb is closed to Vref; in the lower capacitor array, the logic switch sna is closed to Vip, and the logic switch snb is closed to Vref. At this time, Vp = Vn = Vref;

[0021] Compare the highest bit, that is, the capacitance at this position is 2 n C. The second highest position comparison means the capacitance at this position is 2 n-1 C... to the lowest bit comparison, that is, when the capacitance at this position is C; in the upper half of the capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive comparison array, and the logic switch spb is closed to gnd; in the lower half of the capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive comparison array, and the logic switch snb is closed to gnd.

[0022] Furthermore, the comparison logic of the traditional successive comparison array is:

[0023] When comparing the highest bit, the highest bit capacitor of the capacitor array connected to the positive input of the comparator is connected to Vref, and the remaining capacitors are grounded. The capacitor array connected to the negative input of the comparator is connected in the opposite way, that is, the highest bit capacitor is grounded, and the remaining capacitors are connected to Vref.

[0024] If Vip>Vin, the logic switch spna of the highest capacitor at the positive input end is connected to ground, the logic switch snna of the highest capacitor at the negative input end is connected to Vref, the logic switch spn-1a of the second highest capacitor at the positive input end is connected to Vref, and the logic switch snn-1a ​​of the second highest capacitor at the negative input end is connected to ground;

[0025] Otherwise, the logic switch spna of the highest capacitor at the positive input terminal remains unchanged (connected to Vref), the logic switch snna of the highest capacitor at the negative input terminal remains unchanged (connected to gnd), the logic switch spn-1a of the second highest capacitor at the positive input terminal is connected to Vref, and the logic switch snn-1a ​​of the second highest capacitor at the negative input terminal is grounded;

[0026] According to the above logic, the second highest bit comparison is performed until the lowest bit comparison.

[0027] Furthermore, when the circuit is a single-ended input structure; each group of capacitor arrays includes an upper capacitor array, and the logic switch performs the following operations:

[0028] During sampling, in the upper capacitor array, the logic switch spa is closed to Vin, and the logic switch spb is closed to Vref; the negative terminal of the comparator is connected to a fixed reference voltage level, at this time, Vp = Vref;

[0029] Compare the highest bit, that is, the capacitance at this position is 2 n C. The second highest position comparison means the capacitance at this position is 2 n-1 C... to the lowest bit comparison, that is, when the capacitance at this position is C; in the upper half of the capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive comparison array, and the logic switch spb is closed to gnd.

[0030] A half-amplitude step-down capacitor sampling successive comparison method adopts a half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit. During the comparison process, the logic switch performs the following operations:

[0031] During sampling, in the upper capacitor array, the logic switch spa is closed to Vin, and the logic switch spb is closed to Vref; in the lower capacitor array, the logic switch spa is closed to Vip, and the logic switch spb is closed to Vref. At this time, Vp = Vn = Vref;

[0032] Compare the highest bit, that is, the capacitance at this position is 2 n C. The second highest position comparison means the capacitance at this position is 2 n-1 C... to the lowest bit comparison, that is, when the capacitance at this position is C; in the upper capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive comparison array, and the logic switch spb is closed to gnd; in the lower capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive comparison array, and the logic switch snb is closed to gnd.

[0033] Beneficial effects of the present invention:

[0034] The present invention reduces the input voltage of the comparator, i.e., the voltage from the capacitor array, by half during operation, thereby reducing excessive input voltage, helping the comparator to select transistors with low-voltage processes and select a lower power supply voltage, thus helping to save circuit power consumption.

[0035] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0037] Figure 1 A conventional successive comparison circuit diagram is shown.

[0038] Figure 2 A schematic diagram of the traditional successive comparison process is shown.

[0039] Figure 3 The figure shows the differential input voltage schematic of the traditional successive approximation process.

[0040] Figure 4 The invention shows a circuit diagram of a capacitor sampling successive approximation analog-to-digital conversion with half-amplitude voltage reduction.

[0041] Figure 5 A schematic diagram of the capacitor sampling successive comparison process of the half-amplitude voltage reduction of the present invention is shown. DETAILED DESCRIPTION

[0042] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0043] A half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit, the circuit includes a capacitor array, a configuration voltage and a logic switch, wherein the capacitor array is divided into two groups, each group includes an upper capacitor array and a lower capacitor array, and the upper and lower capacitor arrays are consistent, both C, C to 2 n C, from the third capacitor to the last capacitor, the capacitance value is the sum of all the capacitance values ​​of the current capacitor; the configuration voltage is Vin, Vip, Vref, gnd, and the logic switch is installed between the capacitor and the configuration voltage to realize the switching of the configuration voltage during the comparison process;

[0044] Wherein: the logic switch configuration of one group of capacitor arrays is spa, and the logic switch configuration of another group of capacitor arrays is spb. During the comparison process, the logic switches perform the following operations:

[0045] During sampling, in the upper capacitor array, the logic switch spa is closed to Vin, and the logic switch spb is closed to Vref; in the lower capacitor array, the logic switch spa is closed to Vip, and the logic switch spb is closed to Vref. At this time, Vp = Vn = Vref;

[0046] In comparison 1, comparison 2, ... to the last comparison, in the upper capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive comparison array, and the logic switch spb is closed to gnd; in the lower capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive comparison array, and the logic switch spb is closed to gnd.

[0047] References for traditional successive approximation arrays: Science Press, "Low Power CMOS Successive Approximation Analog-to-Digital Converter", first edition, Chapter 2, page 13, section 2.1.1, the comparison logic is as follows:

[0048] When comparing the highest bit, the highest bit capacitor of the capacitor array connected to the positive input of the comparator is connected to Vref, and the remaining capacitors are grounded. The capacitor array connected to the negative input of the comparator is connected in the opposite way, that is, the highest bit capacitor is grounded, and the remaining capacitors are connected to Vref.

[0049] If Vip>Vin, the logic switch spna of the highest capacitor at the positive input end is connected to ground, the logic switch snna of the highest capacitor at the negative input end is connected to Vref, the logic switch spn-1a of the second highest capacitor at the positive input end is connected to Vref, and the logic switch snn-1a ​​of the second highest capacitor at the negative input end is connected to ground;

[0050] Otherwise, the logic switch spna of the highest capacitor at the positive input terminal remains unchanged, that is, connected to Vref, the logic switch snna of the highest capacitor at the negative input terminal remains unchanged, that is, connected to gnd, the logic switch spn-1a of the second highest capacitor at the positive input terminal is connected to Vref, and the logic switch snn-1a ​​of the second highest capacitor at the negative input terminal is grounded;

[0051] According to the above logic, the second highest bit comparison is performed until the lowest bit comparison.

[0052] When the circuit is a single-ended input structure, each group of capacitor arrays includes an upper half of the capacitor array, and the switching refers to the upper half of the capacitor array.

[0053] like Figure 5 As shown, taking 2-bit successive approximation as an example, the working process of the circuit of the present invention is explained:

[0054] During data acquisition, in the upper capacitor array, the switch of the capacitor pair labeled a is closed to Vin, and the switch of the capacitor pair labeled b is closed to Vref; in the lower capacitor array, the switch of the capacitor pair labeled a is closed to Vip, and the switch of the capacitor pair labeled b is closed to Vref;

[0055] Entering the comparison process, when comparing 1 and 2, that is, the highest bit and the second highest bit, in the upper capacitor array, the switch marked a in the capacitor pair has the same connection voltage as the traditional structure, and the switch marked b is closed to gnd. In the lower capacitor array, the switch marked a in the capacitor pair has the same connection voltage as the corresponding capacitor in the lower capacitor array of the traditional structure, and the switch marked b is closed to gnd. The obtained Vp and Vn voltage values ​​are as follows:

[0056] Sampling: input differential voltage value, Vp = Vn = Vref;

[0057] Comparison 1: The highest bit comparison corresponds to the first bit capacitor (2c)

[0058] Vp=3 / 4Vref-1 / 2Vin, Vn=3 / 4Vref-1 / 2Vip, Vp-Vn=1 / 2(Vip-Vin);

[0059] Comparison 2: Second highest comparison;

[0060] The result of comparison 1 is positive, and the connection relationship becomes upper right:

[0061] For the upper part, the voltage of the first capacitor (2c) becomes gnd, and the voltage of the second capacitor (c) becomes Vref;

[0062] For the lower half, the voltage of the first capacitor (2c) becomes Vref, and the voltage of the second capacitor (c) becomes gnd;

[0063] Then do the second comparison:

[0064] Vp=5 / 8Vref-1 / 2Vin, Vn=7 / 8Vref-1 / 2Vip, Vp-Vn=1 / 2(Vip-Vin)-1 / 4Vref;

[0065] The result of comparison 1 is negative, and the connection relationship changes to the lower right:

[0066] For the upper part, the voltage of the first capacitor (2c) remains unchanged, and the voltage of the second capacitor (c) becomes Vref;

[0067] For the lower half, the voltage of the first capacitor (2c) remains unchanged, and the voltage of the second capacitor (c) changes to gnd;

[0068] Then do the second comparison:

[0069] Vp=7 / 8Vref-1 / 2Vin, Vn=5 / 8Vref-1 / 2Vip, Vp-Vn=1 / 2(Vip-Vin)-(-1 / 4Vref);

[0070] . . .

[0071] For more references to the comparison process of the positions, please refer to the first edition of "Low-Power CMOS Successive Approximation Analog-to-Digital Converter" published by Science Press, Chapter 2, page 13, section 2.1.1.

[0072] It can be seen from the above voltage values ​​that in each comparison stage, the differential voltage point actually compared by the comparator is the same as that of the traditional structure, satisfying the successive approximation conversion process. However, the voltage values ​​of Vp and Vn will not exceed Vref, effectively preventing the comparator input voltage from exceeding the comparator power supply range, helping the comparator select a lower voltage and reducing circuit power consumption.

[0073] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit, characterized in that: The circuit includes a comparator and a capacitor array, a configuration voltage and a logic switch at the input end of the comparator, and the circuit is a double-terminal input structure; The capacitor array consists of two groups, each group includes an upper capacitor array and a lower capacitor array, and the upper and lower capacitor arrays are consistent, both C, C to 2 n C, from the third capacitor to the last capacitor, the capacitance value is the sum of all the capacitance values ​​before the current capacitor; the configuration voltage is Vin, Vip, Vref, gnd, and the logic switch is installed between the capacitor and the configuration voltage to realize the switching of the configuration voltage during the comparison process; Wherein: the upper half of the logic switch of one group of capacitor arrays is configured as spa, and the lower half is configured as sna, the upper half of the logic switch of another group of capacitor arrays is configured as spb, and the lower half is configured as snb, the number of comparisons is the number of bits, and during the comparison process, the logic switch performs the following operations: During sampling, in the upper capacitor array, the logic switch spa is closed to Vin, and the logic switch spb is closed to Vref; in the lower capacitor array, the logic switch sna is closed to Vip, and the logic switch snb is closed to Vref. At this time, Vp = Vn = Vref; Compare the highest bit, that is, the capacitance at this position is 2 n C. The second highest position comparison means that the capacitance at this position is 2 n-1 C... to the lowest bit comparison, that is, when the capacitance at this position is C; in the upper part of the capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive approximation array, and the logic switch spb is closed to gnd; in the lower part of the capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive approximation array, and the logic switch snb is closed to gnd.

2. The half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit according to claim 1, characterized in that: The comparison logic of the traditional successive comparison array is: When comparing the highest bit, the highest bit capacitor of the capacitor array connected to the positive input of the comparator is connected to Vref, and the remaining capacitors are grounded. The capacitor array connected to the negative input of the comparator is connected in the opposite way, that is, the highest bit capacitor is grounded, and the remaining capacitors are connected to Vref. If Vip>Vin, the logic switch spna of the highest capacitor at the positive input end is connected to ground, the logic switch snna of the highest capacitor at the negative input end is connected to Vref, the logic switch spn-1a of the second highest capacitor at the positive input end is connected to Vref, and the logic switch snn-1a ​​of the second highest capacitor at the negative input end is connected to ground; Otherwise, the logic switch spna of the highest capacitor at the positive input end remains unchanged, that is, connected to Vref, the logic switch snna of the highest capacitor at the negative input end remains unchanged, that is, connected to gnd, the logic switch spn-1a of the second highest capacitor at the positive input end is connected to Vref, and the logic switch snn-1a ​​of the second highest capacitor at the negative input end is grounded; the second highest bit comparison is performed according to the above logic until the lowest bit comparison is performed.

3. The half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit according to claim 1, characterized in that: When the circuit is a single-ended input structure; each group of capacitor arrays includes an upper capacitor array, and the logic switch performs the following operations: During sampling, in the upper capacitor array, the logic switch spa is closed to Vin, and the logic switch spb is closed to Vref; the negative terminal of the comparator is connected to a fixed reference voltage level, at this time, Vp = Vref; Compare the highest bit, that is, the capacitance at this position is 2 n C. The second highest position comparison means that the capacitance at this position is 2 n-1 C... to the lowest bit comparison, that is, when the capacitance at this position is C; in the upper part of the capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive comparison array, and the logic switch spb is closed to gnd.

4. A half-amplitude step-down capacitor sampling successive comparison method, using the half-amplitude step-down capacitor sampling successive approximation analog-to-digital conversion circuit used in any one of claims 1-2, characterized in that: During the comparison process, the logic switch performs the following operations: During sampling, in the upper capacitor array, the logic switch spa is closed to Vin, and the logic switch spb is closed to Vref; in the lower capacitor array, the logic switch spa is closed to Vip, and the logic switch spb is closed to Vref. At this time, Vp = Vn = Vref; Compare the highest bit, that is, the capacitance at this position is 2 n C. The second highest position comparison means that the capacitance at this position is 2 n-1 C... to the lowest bit comparison, that is, when the capacitance at this position is C, in the upper capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive approximation array, and the logic switch spb is closed to gnd; in the lower capacitor array, the connection voltage of the logic switch spa is the same as that of the traditional successive approximation array, and the logic switch snb is closed to gnd.

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