Compiler code generation method for cryptographic processor and related equipment

Abstract

The present application discloses a compiler code generation method for a cryptographic processor and related equipment. In the scheme, first, a data flow graph is obtained, and the data flow graph corresponds to multiple instructions; then, schedulable instructions are screened out from the instructions corresponding to the data flow graph, and a candidate cluster of each schedulable instruction is determined; then, a preset number of target instructions are determined from the schedulable instructions, and the cluster where the target instruction is located is determined based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction; finally, based on the candidate register type of the operand in the target instruction and the cluster where the target instruction is located, register allocation is performed on the operand in the target instruction. The scheme is suitable for compiler code generation of a VLIW architecture cryptographic processor, and can reduce compilation time and improve the performance of the generated program.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a compiler code generation method for a cryptographic processor and related equipment. Background Art

[0002] A VLIW (Very Long Instruction Word) architecture cryptographic processor refers to a cryptographic instruction set processor that uses a VLIW architecture. The VLIW architecture encodes multiple instructions based on program parallelism and resource availability to form a very long instruction that is executed in one cycle. Its core idea is to transfer instruction scheduling from hardware to the compiler.

[0003] The VLIW architecture cryptographic processor adopts a special very long instruction word architecture. Compared with the traditional very long instruction word architecture processor, it adopts the register access method of arbitrary read and fixed write, and adopts a reconfigurable operation unit. The cluster includes three types of register files: general registers, key registers and configuration registers. It adopts instructions of different word lengths and the cascade method of operation units between clusters to adapt to the flexible cryptographic operation bit width. The compiler code generation method of the cryptographic processor of the traditional very long instruction word architecture processor is not suitable for the VLIW architecture cryptographic processor.

[0004] Therefore, how to provide a compiler code generation method for a cryptographic processor suitable for a VLIW architecture cryptographic processor has become a technical problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0005] In view of the above problems, this application proposes a compiler code generation method and related equipment for a cryptographic processor. The specific scheme is as follows:

[0006] A method for generating compiler code for a cryptographic processor, the method comprising:

[0007] Obtaining a data flow graph, wherein the data flow graph corresponds to a plurality of instructions;

[0008] Filter out schedulable instructions from the instructions corresponding to the data flow graph, and determine a candidate cluster for each schedulable instruction;

[0009] Determine a preset number of target instructions from the schedulable instructions, and determine the cluster where the target instruction is located based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction;

[0010] Based on the candidate register types of the operands in the target instruction and the cluster where the target instruction is located, register allocation is performed on the operands in the target instruction.

[0011] Optionally, screening out schedulable instructions from the instructions corresponding to the data flow graph and determining a candidate cluster of each schedulable instruction includes:

[0012] Based on the data flow graph, determining an instruction list without a predecessor node;

[0013] The schedulable instructions are screened out from the instruction list without predecessor nodes, and a candidate cluster of each schedulable instruction is determined.

[0014] Optionally, determining a preset number of target instructions from the schedulable instructions, and determining the cluster where the target instruction is located based on the candidate cluster of each target instruction, includes:

[0015] Determine the priority of each schedulable instruction;

[0016] Determining a preset number of target instructions from the schedulable instructions based on the priorities of the schedulable instructions;

[0017] For each target instruction, determine the maximum pressure difference between register files corresponding to the candidate cluster of the target instruction; and determine the cluster where the target instruction is located based on the maximum pressure difference between register files corresponding to the candidate cluster of the target instruction.

[0018] Optionally, determining the priority of each schedulable instruction includes:

[0019] For each schedulable instruction, determining the mobility, number of successor nodes and word length of the schedulable instruction;

[0020] The priority of the schedulable instruction is determined based on the mobility, the number of successor nodes and the word length of the schedulable instruction.

[0021] Optionally, the determining the mobility of the schedulable instruction comprises:

[0022] Based on the data flow graph, determining the earliest execution time and the latest execution time of the schedulable instruction;

[0023] The mobility of the schedulable instruction is determined based on the earliest execution time and the latest execution time of the schedulable instruction.

[0024] Optionally, the method for determining the candidate register type of the operand in the instruction includes:

[0025] Determine a value-reference chain of operands in the instruction, and register type constraint information of the instruction on the operands;

[0026] Based on the value-reference chain of the operand in the instruction and the register type constraint information of the operand in the instruction, the candidate register type of the operand in the instruction is determined.

[0027] Optionally, performing register allocation on the operand in the target instruction based on the candidate register type of the operand in the target instruction and the cluster to which the target instruction belongs includes:

[0028] Determine a target register file, the target register file being a register file corresponding to the candidate register type in the cluster where the target instruction is located;

[0029] Obtaining an active variable list corresponding to the target register file, wherein the active variable list is used to represent variables currently stored in the target register file;

[0030] Determining whether there are available registers in the target register file based on an active variable list corresponding to the target register file;

[0031] If so, an operand within the target instruction is allocated an available register in the target register file.

[0032] A compiler code generation device for a cryptographic processor, the device comprising:

[0033] An acquisition unit, used for acquiring a data flow graph, wherein the data flow graph corresponds to a plurality of instructions;

[0034] An instruction screening unit, used to screen out schedulable instructions from the instructions corresponding to the data flow graph, and determine a candidate cluster of each schedulable instruction;

[0035] A cluster assignment unit, configured to determine a preset number of target instructions from the schedulable instructions, and determine a cluster where the target instruction is located based on a candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction;

[0036] The register allocation unit is used to allocate registers for the operands in the target instruction based on the candidate register types of the operands in the target instruction and the cluster where the target instruction is located.

[0037] A compiler code generation device for a cryptographic processor, comprising a memory and a processor;

[0038] The memory is used to store programs;

[0039] The processor is used to execute the program to implement the various steps of the compiler code generation method for the cryptographic processor as described above.

[0040] A readable storage medium stores a computer program thereon. When the computer program is executed by a processor, the computer program implements the various steps of the compiler code generation method for the cryptographic processor as described above.

[0041] By means of the above technical scheme, the present application discloses a compiler code generation method and related equipment for a cryptographic processor. In the scheme, first, a data flow graph is obtained, and the data flow graph corresponds to multiple instructions; then, schedulable instructions are screened out from the instructions corresponding to the data flow graph, and a candidate cluster of each schedulable instruction is determined; then, a preset number of target instructions are determined from the schedulable instructions, and the cluster where the target instruction is located is determined based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction; finally, based on the candidate register type of the operand in the target instruction and the cluster where the target instruction is located, register allocation is performed on the operand in the target instruction. The scheme is suitable for compiler code generation of a VLIW architecture cryptographic processor, and can reduce compilation time and improve the performance of the generated program. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0043] Figure 1 A schematic diagram of the structure of a VLIW architecture cryptographic processor disclosed in an embodiment of the present application;

[0044] Figure 2 An instruction diagram of a VLIW architecture cryptographic processor disclosed in an embodiment of the present application;

[0045] Figure 3 A flowchart of a compiler code generation method for a cryptographic processor disclosed in an embodiment of the present application;

[0046] Figure 4 A schematic diagram of a DFG with register type conflicts disclosed in an embodiment of the present application;

[0047] Figure 5 A schematic diagram of a DFG for resolving register type conflicts disclosed in an embodiment of the present application;

[0048] Figure 6 A schematic diagram of the structure of a compiler code generation device for a cryptographic processor disclosed in an embodiment of the present application;

[0049] Figure 7This is a hardware structure block diagram of a compiler code generation device for a cryptographic processor disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0051] As the number of computing units increases, VLIW architecture processors should be able to provide corresponding register files to meet the data reading and writing requirements. All computing units accessing the same register file will reduce the scalability of the architecture, and a large number of read and write ports will also increase the data access latency. Therefore, VLIW architecture processors usually adopt a clustered structure. The computing units within a cluster can access the registers within the cluster, and data interaction between clusters requires additional hardware resources, transmission instructions, and clock cycles. The clustered structure restricts instruction-level parallelism to a certain extent and complicates the original static scheduling strategy. Instruction scheduling with high performance as the goal must not only make full use of computing units in different clusters to improve parallelism, but also reduce the time overhead of data interaction between clusters. It must also consider the constraints of register ports on parallelism and unnecessary register overflows caused by uneven pressure on registers between clusters.

[0052] The compiler code generation of VLIW architecture processors is mainly divided into three stages: cluster assignment, instruction scheduling and register allocation. Among them, cluster assignment is to determine the cluster where the instruction is executed. Instruction scheduling is a compiler optimization that rearranges the execution order of instructions without changing the program function. It is used to improve instruction-level parallelism and thus improve processor performance. Register allocation is the process of assigning variables to a limited number of registers.

[0053] In the traditional compiler code generation method for cryptographic processors of very long instruction word architecture processors, the heuristic algorithm compilation time is too long and the quality of the solution cannot be guaranteed. The non-heuristic algorithm is not suitable for compiler code generation of VLIW architecture cryptographic processors. In view of this, the inventor of this case conducted in-depth research and finally proposed a compiler code generation method for cryptographic processors suitable for VLIW architecture cryptographic processors.

[0054] The structure of the VLIW architecture cryptographic processor is first described in detail below.

[0055] Reference Figure 1 , Figure 1 Schematic diagram of the structure of a VLIW architecture cryptographic processor disclosed in the embodiment of the present application. Figure 1As shown in the figure, there are four clusters Cluster A, Cluster B, Cluster C and Cluster D in the VLIW architecture cryptographic processor. The clusters are designed in a homogeneous manner. The clusters contain 12 RCEs (reconfigurable computing elements), DataRFs (data register files), and KeyRFs (key register files). The size of DataRF is 32×32 bits, and the size of KeyRF is 64×32 bits. DataRF has two read ports and one write port, while KeyRF has one read port and one write port.

[0056] It should be noted that the VLIW architecture cryptographic processor has the following special constraints to comply with:

[0057] Considering the chaotic and diffuse characteristics of cryptographic operations, frequent cross-cluster communications will occur. Therefore, registers are organized in a random read and fixed write manner, that is, RCE within a cluster can read register files of other clusters, but can only write data back to register files of its own cluster.

[0058] The operations that can be performed by the 12 RCEs in the cluster are different, including permutation, substitution, and modulo operations. By writing the corresponding configuration information, the operation unit can be reconfigured, such as different bit widths for permutation operations, different permutation tables, etc. The configuration information in the cluster and the RCE are tightly coupled, that is, the configuration information in the cluster is only valid for the operation units of the cluster. Therefore, in order to use the corresponding configuration information, the instructions must be assigned to the corresponding cluster.

[0059] The data register file and the key register file are used not according to the data type, but according to the instruction format. The operands in some instructions can be stored in either the data register or the key register.

[0060] The instructions of the VLIW architecture cryptographic processor are all single-cycle, and the data dependency between adjacent very long instructions is resolved by means of data forwarding. Figure 2 , Figure 2 This is a schematic diagram of instructions for a VLIW architecture cryptographic processor disclosed in an embodiment of the present application. Figure 2As shown in the figure, in the VLIW architecture cryptographic processor, instructions of different word lengths are designed to adapt to different operation bit widths in cryptographic operations, including single-word instructions, double-word instructions, and quad-word instructions, which process 32, 64, and 128 bits of data, respectively, and occupy 1, 2, and 4 instruction slots. Instructions occupying multiple instruction slots can write the results back to the corresponding multiple clusters. For example, double-word instructions occupying Slot1 and Slot2 can write data back to the registers of ClusterA or ClusterB.

[0061] Based on the above VLIW architecture cryptographic processor, the inventor of this case proposes a compiler code generation method for a cryptographic processor. Next, the compiler code generation method for a cryptographic processor provided by this application is introduced through the following embodiments.

[0062] Reference Figure 3 , Figure 3 This is a flow chart of a compiler code generation method for a cryptographic processor disclosed in an embodiment of the present application. The method may include:

[0063] Step S101: Obtain a data flow graph, where the data flow graph corresponds to multiple instructions.

[0064] In the present application, the data flow graph DFG (DataFlow Gragh) includes multiple nodes, and each node corresponds to an instruction.

[0065] It should be noted that the data flow graph can be an initial data flow graph, or it can be a data flow graph that is updated after the initial data flow graph has gone through a compiler code generation process. The data flow graph can be updated by reducing the in-degree of the successor node of the target execution determined by a compiler code generation process by 1.

[0066] Step S102: Filter out schedulable instructions from the instructions corresponding to the data flow graph, and determine a candidate cluster for each schedulable instruction.

[0067] Step S103: determining a preset number of target instructions from the schedulable instructions, and determining the cluster where the target instruction is located based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction.

[0068] Step S104: performing register allocation for the operands in the target instruction based on the candidate register types of the operands in the target instruction and the cluster to which the target instruction belongs.

[0069] In this application, after the above steps are completed, the compiler code generation process is completed once, and a super long instruction is generated, which includes a preset number of target instructions. The target instruction will obtain the corresponding triple {C i ,T i ,R i}, where C i Indicates the cluster where the target instruction is located, T i represents the execution time of the target instruction, R i Represents the ordered set of registers where the operands in the target instruction are located. i The elements in can also be represented by triples {c i ,t i ,s i} means that c i Indicates the cluster where the operand is located, t i Indicates the register type of the operand, s i Indicates the specific register of the operand. For example, {Cluster AB,4,{<Cluster A,DRFs,6> ,<Cluster B,KRFs,8>}} indicates that the double-word instruction is scheduled on ClusterAB at the 4th clock cycle, and its two destination operands are stored in the 6th register of DRFs in Cluster A and the 8th register of KRFs in Cluster B respectively.

[0070] It should be noted that the above four steps need to be executed at least once in this application to complete the processing of all instructions in the data flow graph. Each time the above four steps are executed, the data flow graph is updated once, and then the above four steps are executed with the updated data flow graph as the processing object.

[0071] The present embodiment discloses a compiler code generation method for a cryptographic processor, in which, first, a data flow graph is obtained, the data flow graph corresponding to a plurality of instructions; then, schedulable instructions are screened out from the instructions corresponding to the data flow graph, and a candidate cluster of each schedulable instruction is determined; then, a preset number of target instructions are determined from the schedulable instructions, and the cluster where the target instruction is located is determined based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction; finally, register allocation is performed on the operands in the target instruction based on the candidate register types of the operands in the target instruction and the cluster where the target instruction is located. The method is suitable for compiler code generation of a VLIW architecture cryptographic processor, and can reduce compilation time and improve the performance of the generated program.

[0072] In another embodiment of the present application, a specific implementation method of screening out schedulable instructions from the instructions corresponding to the data flow graph and determining a candidate cluster of each schedulable instruction is described, and the method may include the following steps:

[0073] Step S201: Based on the data flow graph, determine an instruction list without a predecessor node.

[0074] In the present application, an instruction list L without a predecessor node can be constructed, and any instruction OP∈L satisfies pred(OP)=null.

[0075] Step S202: Filter out schedulable instructions from the instruction list without predecessor nodes, and determine a candidate cluster for each schedulable instruction.

[0076] Specifically, for each instruction in the instruction list L without a predecessor node, the candidate cluster is determined based on its instruction type (reconfigurable instruction or non-reconfigurable instruction), the cluster occupancy of the instruction configuration information, the port constraints, the instruction word length and the initial candidate cluster occupancy. Instructions whose candidate cluster set is empty are unschedulable instructions.

[0077] For reconfigurable instructions, such as permutation instructions and S-box replacement instructions, first check whether the cluster where the configuration information is located is occupied. The RCE in the cluster adopts a reconfigurable design, and the configuration information is written into the cluster in advance, so that the same instruction can be used to implement operations with different parameters. However, due to the tight coupling between RCE and configuration information, once the cluster is occupied by other instructions, the instructions using the configuration information in the cluster cannot be executed in the current cycle.

[0078] For non-reconfigurable instructions, the initial candidate clusters for instructions of different word lengths are different. The initial candidate clusters for four-word instructions are {Cluster ABCD}, the initial candidate clusters for double-word instructions are {Cluster AB, Cluster CD}, and the initial candidate clusters for single-word instructions are {Cluster A, Cluster B, Cluster C, Cluster D}. In addition, it is necessary to remove unavailable clusters in the initial candidate clusters based on the occupancy of the clusters. When Cluster A is occupied, the candidate cluster for four-word instructions is Φ, the candidate cluster for double-word instructions is {Cluster CD}, and the initial candidate clusters for single-word instructions are {Cluster B, Cluster C, Cluster D}.

[0079] Finally, the instructions must satisfy the read port constraint. DRFs and KRFs have a fixed number of read ports, DRFs have 2 read ports, and KRFs have 1 read port. The already scheduled instructions in the super-long instruction will occupy some read ports, so the newly added instructions cannot cause conflicts. When the 2 read ports of the DRF in Cluster A are already occupied, the instructions whose source operands also come from the register file will not be selected.

[0080] For easier understanding, please refer to the following code:

[0081] 1:foreach OP in L

[0082] 2:if (OP is a reconfigurable instruction)

[0083] 3:if (the cluster where the OP configuration information is located is occupied)

[0084] 4: OP cannot be scheduled;

[0085] 5:else if (OP satisfies the read port constraint)

[0086] 6: OP is schedulable, the candidate cluster is the cluster where the configuration information is located;

[0087] 7:else

[0088] 8: OP cannot be scheduled;

[0089] 9:else

[0090] 10: Generate candidate clusters based on instruction word length and cluster occupancy;

[0091] 11:if (the candidate cluster set is empty)

[0092] 12: OP cannot be scheduled;

[0093] 13:else if (OP satisfies the read port constraint)

[0094] 14: OP can be scheduled;

[0095] 15:else

[0096] OP is not schedulable, set the candidate cluster set to empty;

[0097] In another embodiment of the present application, a specific implementation method of determining a preset number of target instructions from the schedulable instructions and determining the cluster where the target instruction is located based on the candidate cluster of each target instruction is described. The method may include the following steps:

[0098] Step S301: Determine the priority of each schedulable instruction;

[0099] As an implementable method, determining the priority of each schedulable instruction includes: for each schedulable instruction, determining the mobility, number of successor nodes and word length of the schedulable instruction; based on the mobility, number of successor nodes and word length of the schedulable instruction, determining the priority of the schedulable instruction.

[0100] In this application, in order to ensure that instructions with greater impact on performance are executed first, a priority-based instruction selection method is adopted, which considers the impact of instruction mobility, the number of successor nodes and instruction word length on the scheduling result in turn.

[0101] As an implementable method, the determining the mobility of the schedulable instruction includes: determining the earliest execution time and the latest execution time of the schedulable instruction based on the data flow graph; determining the mobility of the schedulable instruction based on the earliest execution time and the latest execution time of the schedulable instruction. Specifically, ASAP scheduling is performed on DFG, and the earliest execution time of instruction OP is obtained as Te(OP); ALAP scheduling is performed on DFG, and the latest execution time of instruction OP is obtained as Tl(OP); and the mobility of instruction OP is calculated, Mobility(OP)=Tl(OP)-Te(OP).

[0102] Step S302: determining a preset number of target instructions from the schedulable instructions based on the priorities of the schedulable instructions;

[0103] Instructions with low mobility have higher priority than instructions with high mobility. The smaller the mobility, the more critical it is to the scheduling of instructions. Once instructions with low mobility are delayed, the overall execution time of the program will be worsened. Therefore, instructions with low mobility should be processed first. Under the premise of the same mobility, instructions with more successor nodes have higher priority than instructions with fewer successor nodes. The more successor nodes an instruction has, the more instructions it can release after being executed, which is beneficial to the subsequent scheduling; the fewer successor nodes an instruction has, the fewer instructions it can release after being executed, which is not conducive to the subsequent scheduling. Therefore, instructions with more successor nodes should be processed first. Under the premise of the same mobility and the number of successor nodes, long-word instructions have higher priority than short-word instructions. On the one hand, for a four-word instruction, whether it is executed first or later does not affect the execution time of the final program; on the other hand, from the perspective of flexibility, short-word instructions are more flexible than long-word instructions. Single-word instructions can be filled in any position of the instruction slot, double-word instructions must have two consecutive instruction slots Slot 12 or Slot 34, and four-word instructions require all instruction slots to be empty. Therefore, compared with short-word instructions, long-word instructions should be processed first.

[0104] Step S303: for each target instruction, determine the maximum pressure difference between register files corresponding to the candidate clusters of the target instruction; and determine the cluster where the target instruction is located based on the maximum pressure difference between register files corresponding to the candidate clusters of the target instruction.

[0105] Under the constraints of the hardware structure, the cluster where the instruction is located directly determines the storage location of the operand. Therefore, when assigning clusters, full consideration should be given to balancing the pressure between register files. On the one hand, variable overflow requires additional memory access instructions, which in turn affects the performance of the program. Relatively balanced register pressure can reduce the probability of variable overflow; on the other hand, relatively balanced register pressure makes the source operands of the instructions relatively balanced, thereby reducing the probability of register file read port conflicts, which is beneficial to the subsequent scheduling.

[0106] In the present application, for each target instruction, the maximum pressure difference between the register files corresponding to the candidate clusters of the target instruction can be calculated. The maximum pressure difference between register files refers to the difference between the maximum pressure and the minimum pressure of the register file in the current cycle. DRFs and KRFs need to be considered separately when calculating the maximum pressure difference. For example, the pressures of the four DRFs are 2, 3, 1, and 2, respectively. The register type of the destination operand Rd in the single-word instruction XOR32 Rd, Rs1, Rs2 is DRFs. The three candidate clusters of the instruction are Cluster B, Cluster C, and Cluster D, respectively. It can be calculated that the maximum pressure differences between register files under the three cluster selection schemes are 3, 1, and 2, respectively. Obviously, we choose the scheme with a smaller maximum pressure difference, that is, to assign the instruction to Cluster C.

[0107] In another embodiment of the present application, a method for determining the candidate register type of the operand in the instruction is described in detail, and the method may include the following steps:

[0108] Step S401: Determine the value-reference chain of the operands in the instruction, and the register type constraint information of the operands of the instruction.

[0109] The instruction manual specifies in detail the register type constraints for the operands in each instruction. Such constraints appear not only in the source operand position, but also in the destination operand position. For example, the source operand Rs3 of the PERM_XOR Rd, Rs1, Rs2, Rs3 instruction can only come from KRF, while the destination operand Rd of the XOR32 Rd, Rs1, Rs2 instruction can only be written back to DRF. This means that each operand has two or more register type constraints. Register type assignment is performed during instruction scheduling, and the constraints on the operand register type of subsequent references cannot be evaluated, resulting in an increased possibility of conflicts. Register type assignment is performed after instruction scheduling is completed, and new instructions need to be inserted to resolve conflicts, resulting in unnecessary rescheduling. Therefore, assign register types to operands first.

[0110] Step S402: Determine candidate register types for the operands in the instruction based on the value-reference chain of the operands in the instruction and the register type constraint information of the operands in the instruction.

[0111] In the register type assignment phase, the register type is assigned to the operand according to the "value-reference" chain of the operand and the register type constraint on the operand in the instruction. The specific process is as follows:

[0112] First, construct the "fixed value-reference" chain of each operand according to DFG, which can be represented by a triple {x, d, U}, where x is the symbolic name of the operand, d is the location of the fixed value, and U is the reference set of the fixed value. Figure 4 (DFG with register type conflict) as shown, {tmp,<OP1,1> ,{<OP4,3> ,<OP6,2>}} indicates that operand tmp is set at the first position of OP1 and referenced at the third position of OP4 and the second position of OP6.

[0113] Secondly, determine the candidate register type set of the operand. Use type(OP,k) to represent the register type constraint of the kth operand of instruction OP. There are three possible values ​​for type(OP,k): {DRFs}, {KRFs}, and {DRFs,KRFs}. The candidate register type set of the operand is the intersection of the register type constraint at the evaluation point and the register type constraint at all reference points. Figure 4 As shown in (DFG with register type conflict), the candidate register type set of operand tmp is type(OP1,1)∩type(OP4,3)∩type(OP6,2), and its candidate register type set has four possible values: {DRFs}, {KRFs}, {DRFs,KRFs}, Φ:

[0114] When the value is {DRFs} or {KRFs}, that is, when there is only one element in the set, the corresponding register type is directly assigned to the operand;

[0115] When the value is {DRFs, KRFs}, the pressure between different types of register files should be balanced. However, the instructions are not scheduled at this time, and the pressure of each register file cannot be accurately evaluated. According to experience, DRFs can be directly assigned to operands. This is because most data in cryptographic operations are referenced immediately after being valuated and only referenced once, so DRFs have less register pressure overall;

[0116] When the value is Φ, there is a register type conflict. The conflict can be resolved by renaming all conflicting references, inserting mov instructions, and updating DFG and the "constant-reference" chain. Assume type(OP1,1)={DRFs}, type(OP4,3)={DRFs,KRFs}, type(OP6,2)={KRFs}, calculate type(OP1,1)∩type(OP4,3)={DRFs}, and type(OP1,1)∩type(OP4,3)∩type(OP6,2)=Φ, it can be considered that all conflicting references have<OP6,2> Therefore, a mov tmp1, tmp instruction OP7 is inserted between OP6 and OP1, and the operand tmp is assigned the DRFs type and the operand tmp1 is assigned the KRFs type. Based on this, the DFG and the "value-reference" chain need to be updated. The updated DFG is as follows Figure 5 (DFG to resolve register type conflicts) is shown below. The original one "constant value-reference" chain is also converted into two, {tmp,<OP1,1> ,{<OP4,3>}} and {tmp1,<OP7,1> ,{<OP6,2>}}.

[0117] In another embodiment of the present application, a specific implementation method of register allocation for the operand in the target instruction based on the candidate register type of the operand in the target instruction and the cluster to which the target instruction belongs is described, and the method may include the following steps:

[0118] Step S501: determining a target register file, wherein the target register file is a register file corresponding to the candidate register type in the cluster where the target instruction is located;

[0119] Register allocation can be divided into three stages: register type assignment, register cluster assignment and specific register assignment. Determining the cluster where the target instruction is located completes the register cluster assignment, and determining the candidate register type completes the register type assignment.

[0120] Step S502: obtaining an active variable list corresponding to the target register file, wherein the active variable list is used to represent variables currently stored in the target register file;

[0121] The algorithm uses a method of allocating registers while scheduling, that is, after scheduling a very long instruction, a specific register is allocated for the destination operand in the current instruction. This method does not complete instruction scheduling before register allocation, so it is impossible to construct a complete register conflict graph, and the graph coloring algorithm cannot be used directly to deal with the register allocation problem. The linear scan algorithm allocates registers in the order of instruction execution, which meets the characteristics of allocating registers while scheduling in this section. Therefore, this paper proposes an improved linear scan algorithm and extends it to the VLIW architecture that can execute multiple instructions in parallel.

[0122] The multiple register files in the processor maintain their own "active variable" lists, that is, the variables currently stored in the register files. In addition, all register files need to jointly maintain a variable "active cycle" list to indicate the fixed value position and the last reference position of each variable. When a variable is set, it is stored in a register; when the variable is no longer referenced, the register it is in is released. Since instruction scheduling is not completed when registers are allocated, it is impossible to determine the actual "active cycle" of the variable, so the "number of times to be referenced" list L is used. active Replaces the "Active Cycles" list.

[0123] Each time a variable is referenced, L active The corresponding number of pending references in the L is reduced by 1. When the number of pending references is 0, it means that the variable is no longer referenced, that is, the "active cycle" ends, and the variable is removed from L active , and releases the register where it is located, freeing up more resources for the next allocation. Once a variable is set, it is added to L active And according to the variable's "fixed value-reference" chain, the number of times to be referenced is added at the same time.

[0124] Step S503: Based on the active variable list corresponding to the target register file, determine whether the target register file has available registers; if so, execute step S504; if not, overflow the variables of the target register file. When the variables overflow, you can choose the "first in, first out" strategy, that is, the variables that are set first overflow first, or choose other strategies, such as "last in, first out", "least used, first out", etc.

[0125] Step S504: Allocate available registers in the target register file for the operands in the target instruction.

[0126] The compiler code generation device of the cryptographic processor disclosed in the embodiment of the present application is described below. The compiler code generation device of the cryptographic processor described below and the compiler code generation method of the cryptographic processor described above can be referenced to each other.

[0127] Reference Figure 6 , Figure 6 This is a schematic diagram of the structure of a compiler code generation device for a cryptographic processor disclosed in an embodiment of the present application. Figure 6 As shown, the compiler code generation device of the cryptographic processor may include:

[0128] An acquisition unit 11 is used to acquire a data flow graph, where the data flow graph corresponds to a plurality of instructions;

[0129] An instruction screening unit 12, used to screen out schedulable instructions from the instructions corresponding to the data flow graph, and determine a candidate cluster of each schedulable instruction;

[0130] A cluster assignment unit 13 is used to determine a preset number of target instructions from the schedulable instructions, and determine the cluster where the target instruction is located based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction;

[0131] The register allocation unit 14 is used to allocate registers for the operands in the target instruction based on the candidate register types of the operands in the target instruction and the cluster to which the target instruction belongs.

[0132] Reference Figure 7 , Figure 7 The hardware structure block diagram of the compiler code generation device of the cryptographic processor provided in the embodiment of the present application is shown in FIG. Figure 7 , the hardware structure of the compiler code generation device of the cryptographic processor may include: at least one processor 1, at least one communication interface 2, at least one memory 3 and at least one communication bus 4;

[0133] In the embodiment of the present application, the number of the processor 1, the communication interface 2, the memory 3, and the communication bus 4 is at least one, and the processor 1, the communication interface 2, and the memory 3 communicate with each other through the communication bus 4;

[0134] The processor 1 may be a central processing unit CPU, or an application-specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention, etc.;

[0135] The memory 3 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory;

[0136] The memory stores a program, and the processor can call the program stored in the memory, wherein the program is used to:

[0137] Obtaining a data flow graph, wherein the data flow graph corresponds to a plurality of instructions;

[0138] Filter out schedulable instructions from the instructions corresponding to the data flow graph, and determine a candidate cluster for each schedulable instruction;

[0139] Determine a preset number of target instructions from the schedulable instructions, and determine the cluster where the target instruction is located based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction;

[0140] Based on the candidate register types of the operands in the target instruction and the cluster where the target instruction is located, register allocation is performed on the operands in the target instruction.

[0141] Optionally, the detailed functions and extended functions of the program may refer to the above description.

[0142] The embodiment of the present application further provides a readable storage medium, which may store a program suitable for execution by a processor, wherein the program is used to:

[0143] Obtaining a data flow graph, wherein the data flow graph corresponds to a plurality of instructions;

[0144] Filter out schedulable instructions from the instructions corresponding to the data flow graph, and determine a candidate cluster for each schedulable instruction;

[0145] Determine a preset number of target instructions from the schedulable instructions, and determine the cluster where the target instruction is located based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction;

[0146] Based on the candidate register types of the operands in the target instruction and the cluster where the target instruction is located, register allocation is performed on the operands in the target instruction.

[0147] Optionally, the detailed functions and extended functions of the program may refer to the above description.

[0148] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0149] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0150] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A compiler code generation method for a cryptographic processor, characterized in that: The method comprises: Obtaining a data flow graph, wherein the data flow graph corresponds to a plurality of instructions; Filter out schedulable instructions from the instructions corresponding to the data flow graph, and determine a candidate cluster for each schedulable instruction; Determine a preset number of target instructions from the schedulable instructions, and determine the cluster where the target instruction is located based on the candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction; Based on the candidate register types of the operands in the target instruction and the cluster where the target instruction is located, register allocation is performed on the operands in the target instruction; The step of determining a preset number of target instructions from the schedulable instructions, and determining a cluster where the target instruction is located based on a candidate cluster of each target instruction, includes: Determine the priority of each schedulable instruction; Determining a preset number of target instructions from the schedulable instructions based on the priorities of the schedulable instructions; For each target instruction, determining a maximum pressure difference between register files corresponding to a candidate cluster of the target instruction; determining a cluster where the target instruction is located based on the maximum pressure difference between register files corresponding to the candidate cluster of the target instruction; The step of allocating registers for the operands in the target instruction based on the candidate register types of the operands in the target instruction and the cluster to which the target instruction belongs includes: Determine a target register file, the target register file being a register file corresponding to the candidate register type in the cluster where the target instruction is located; Obtaining an active variable list corresponding to the target register file, wherein the active variable list is used to represent variables currently stored in the target register file; Determining whether there are available registers in the target register file based on an active variable list corresponding to the target register file; If so, an operand within the target instruction is allocated an available register in the target register file.

2. The method according to claim 1, characterized in that The step of screening out schedulable instructions from the instructions corresponding to the data flow graph and determining a candidate cluster of each schedulable instruction includes: Based on the data flow graph, determining an instruction list without a predecessor node; The schedulable instructions are screened out from the instruction list without predecessor nodes, and a candidate cluster of each schedulable instruction is determined.

3. The method according to claim 1, characterized in that Determining the priority of each schedulable instruction includes: For each schedulable instruction, determining the mobility, number of successor nodes and word length of the schedulable instruction; The priority of the schedulable instruction is determined based on the mobility, the number of successor nodes and the word length of the schedulable instruction.

4. The method according to claim 3, characterized in that The determining the mobility of the schedulable instruction comprises: Based on the data flow graph, determining the earliest execution time and the latest execution time of the schedulable instruction; The mobility of the schedulable instruction is determined based on the earliest execution time and the latest execution time of the schedulable instruction.

5. The method according to claim 1, characterized in that The method for determining the candidate register type of the operand in the instruction includes: Determine a value-reference chain of operands in the instruction, and register type constraint information of the instruction on the operands; Based on the value-reference chain of the operand in the instruction and the register type constraint information of the operand in the instruction, the candidate register type of the operand in the instruction is determined.

6. A compiler code generation device for a cryptographic processor, characterized in that: The device comprises: An acquisition unit, used for acquiring a data flow graph, wherein the data flow graph corresponds to a plurality of instructions; An instruction screening unit, used to screen out schedulable instructions from the instructions corresponding to the data flow graph, and determine a candidate cluster of each schedulable instruction; A cluster assignment unit, configured to determine a preset number of target instructions from the schedulable instructions, and determine a cluster where the target instruction is located based on a candidate cluster of each target instruction; the preset number is consistent with the number of instruction slots in a very long instruction; A register allocation unit, configured to perform register allocation on the operands in the target instruction based on candidate register types of the operands in the target instruction and the cluster to which the target instruction belongs; The cluster assignment unit is specifically used to determine the priority of each schedulable instruction; based on the priority of each schedulable instruction, determine a preset number of target instructions from the schedulable instructions; for each target instruction, determine the maximum pressure difference between register files corresponding to the candidate clusters of the target instruction; determine the cluster where the target instruction is located based on the maximum pressure difference between register files corresponding to the candidate clusters of the target instruction; The register allocation unit is specifically used to determine a target register file, where the target register file is a register file corresponding to the candidate register type in the cluster where the target instruction is located; obtain an active variable list corresponding to the target register file, where the active variable list is used to represent variables currently stored in the target register file; determine whether there are available registers in the target register file based on the active variable list corresponding to the target register file; if so, allocate available registers in the target register file to operands in the target instruction.

7. A compiler code generation device for a cryptographic processor, characterized in that: including memory and processor; The memory is used to store programs; The processor is used to execute the program to implement the various steps of the compiler code generation method for the cryptographic processor according to any one of claims 1 to 5.

8. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, each step of the compiler code generation method for a cryptographic processor according to any one of claims 1 to 5 is implemented.

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