Controller and its operation method

Abstract

The present technology includes a controller and an operating method thereof. The controller includes: a buffer that stores N-bit data; and a cyclic redundancy check controller configured to divide the N-bit data stored in the buffer into m data groups, each including K-bit data, generate compressed data including K bits by processing the data included in the m data groups, and generate a cyclic redundancy check code using the compressed data.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2020-0164597 filed on November 30, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a controller and an operating method thereof, and more particularly, to a controller capable of generating a cyclic redundancy check code and an operating method thereof. Background Art

[0004] A memory system can be configured to store data transmitted from a host or output stored data to the host under the control of the host. A memory system may include a storage device capable of storing data and a controller capable of controlling the storage device. The storage device may include multiple memory devices. Memory devices can generally be categorized as volatile memory devices and non-volatile memory devices. The controller may be configured to communicate between the host and the storage device.

[0005] The controller may generate a cyclic redundancy check code for checking data received from a host before transmitting the data to the storage device. For example, the controller may generate the cyclic redundancy check code by processing raw data, add the cyclic redundancy check code to the raw data to generate a data set, and transmit the data set to the storage device.

[0006] Recently, as the amount of data transmitted between a host and a controller increases, the complexity of an operation for generating a cyclic redundancy check code also increases. Summary of the Invention

[0007] Embodiments of the present disclosure provide a controller and an operating method thereof that can reduce the complexity of an operation for generating a cyclic redundancy check code.

[0008] According to an embodiment of the present disclosure, a controller includes: a buffer that stores N-bit data; and a cyclic redundancy check controller that is configured to divide the N-bit data stored in the buffer into m data groups, each including K-bit data, generate compressed data including K bits by processing the data included in the m data groups, and generate a cyclic redundancy check code using the compressed data.

[0009] According to an embodiment of the present disclosure, a method of operating a controller includes: dividing input data into multiple data groups, generating compressed data by logically combining data included in the multiple data groups in units of bits, and generating a cyclic redundancy check code by performing a cyclic redundancy check operation on the compressed data.

[0010] The present technology can reduce the complexity of an operation for generating a cyclic redundancy check code even when the size of data increases. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A memory system according to an embodiment of the present disclosure is shown.

[0012] Figure 2 Showing an embodiment according to the present disclosure Figure 1 controller.

[0013] Figure 3 Showing an embodiment according to the present disclosure Figure 2 host interface.

[0014] Figure 4 A method of dividing data according to an embodiment of the present disclosure is shown.

[0015] Figure 5 is a flowchart illustrating a method of operating a controller according to a first embodiment of the present disclosure.

[0016] Figure 6A and Figure 6B A method of operating a controller according to the first embodiment of the present disclosure is specifically illustrated.

[0017] Figure 7 is a flowchart illustrating a method of operating a controller according to a second embodiment of the present disclosure.

[0018] Figure 8 A method of operating a controller according to the second embodiment of the present disclosure is specifically illustrated.

[0019] Figure 9 is a flowchart illustrating a method of operating a controller according to a third embodiment of the present disclosure.

[0020] Figure 10A and Figure 10B A method of operating a controller according to a third embodiment of the present disclosure is specifically illustrated.

[0021] Figure 11 is a flowchart illustrating a method of operating a controller according to a fourth embodiment of the present disclosure.

[0022] Figure 12A and Figure 12B A method of operating a controller according to a fourth embodiment of the present disclosure is specifically illustrated.

[0023] Figure 13 A memory card system to which the controller of the present disclosure is applied is shown.

[0024] Figure 14A solid-state drive (SSD) system to which the controller of the present disclosure is applied is shown. DETAILED DESCRIPTION

[0025] Figure 1 A memory system 1000 according to an embodiment of the present disclosure is shown.

[0026] Reference Figure 1 , the memory system 1000 may include a memory device 1100 capable of storing data and a controller 1200 capable of controlling the memory device 1100 .

[0027] The memory device 1100 may include a plurality of dies D11 to Dij, where i and j are positive integers. The dies D11 to Dij may be memory devices configured identically to one another. The dies D11 to Dij may perform programming operations, read operations, or erase operations in response to commands provided by the controller 1200. The dies D11 to Dij may be configured as non-volatile memory devices. For example, the non-volatile memory devices may include electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), spin transfer torque magnetic RAM (STT-MRAM), and the like.

[0028] The controller 1200 may communicate between the host 2000 and the memory device 1100. For example, the controller 1200 may generate a program command, a read command, or an erase command according to a request provided by the host 2000, and transmit the generated command to a selected die of the memory device 1100.

[0029] When data is transmitted between the host 2000 and the storage device 1100, the controller 1200 may generate a cyclic redundancy check (CRC) code for verifying the data. For example, the controller 1200 may divide the input data into a plurality of groups and generate a cyclic redundancy check code for each group by processing the data.

[0030] Figure 2 Specifically shows the embodiment according to the present disclosure Figure 1 Controller 1200.

[0031] Reference Figure 2When data is transmitted between the host 2000 and the storage device 1100, the controller 1200 may generate a CRC code based on the data and transmit a data set in which the CRC code is added to the data. For example, the controller 1200 may include a central processing unit 200, a host interface 210, a system interface 220, a system memory 230, and a memory interface 240. The central processing unit 200, the host interface 210, the system interface 220, and the memory interface 240 may communicate with each other via a bus BUS.

[0032] The central processing unit 200 may include software and hardware capable of controlling the overall operation of the controller 1200. For example, the central processing unit 200 may control the host interface 210, the system interface 220, and the memory interface 240 according to a request of the host 2000 received through the host interface 210. In addition, the central processing unit 200 may perform background operations for improving or managing the performance of the memory system 1000 even if the request is not provided by the host 2000.

[0033] When a request is received from the host 2000, the host interface 210 may transmit the received request to the central processing unit 200 and transfer data DATA between the host 2000 and the controller 1200. For example, during a programming operation, when the host interface 210 receives data DATA from the host 2000, the host interface 210 may perform a cyclic redundancy check operation to verify the received data DATA and generate a cyclic redundancy check code CRCC. The cyclic redundancy check operation may be one of various operations for verifying the data DATA. Since the cyclic redundancy check operation generates the cyclic redundancy check code CRCC by processing the data DATA, the complexity of the cyclic redundancy check operation may increase as the size of the data DATA received from the host 2000 increases, and the time required to perform the cyclic redundancy check operation may increase. For example, as the size of the channel 21 between the host 2000 and the controller 1200 increases, the complexity of the cyclic redundancy check operation performed in the host interface 210 also increases.

[0034] Therefore, in this embodiment, a technology for simplifying cyclic redundancy check operations is provided.

[0035] When the cyclic redundancy check code CRCC is generated, the host interface 210 may output a data set DATA+CRCC obtained by adding the cyclic redundancy check code CRCC to the data DATA.

[0036] The data set DATA+CRCC output from the host interface 210 can be transferred to the system memory 230 (22) through the bus BUS and the system interface 220. The system interface 220 can transfer the data set DATA+CRCC loaded on the bus BUS to the system memory 230 (22) under the control of the central processing unit 200.

[0037] System memory 230 can temporarily store various pieces of information used and to be used by controller 1200. For example, system memory 230 can be configured from a volatile memory such as DRAM, SRAM, etc. Therefore, when power to memory system 1000 is cut off, information stored in system memory 230 may be lost. During a programming operation, the data set DATA+CRCC temporarily stored in system memory 230 can be maintained until the programming operation of the data set DATA+CRCC is completed in memory device 1100.

[0038] Under the control of the system interface 220, the data set DATA+CRCC stored in the system memory 230 can be transferred to the memory interface 240 via the bus BUS (23).

[0039] The memory interface 240 can transmit a data set DATA+CRCC between the controller 1200 and the memory device 1100. For example, in a programming operation, the memory interface 240 can receive the data set DATA+CRCC from the system interface 220 (23) and check the data DATA using the cyclic redundancy check code CRCC included in the received data set DATA+CRCC. As a result of the check, when there is no error in the data DATA, the memory interface 240 can transmit the data set DATA+CRCC to the memory device 1100 through the channel 24. In addition to the data set DATA+CRCC, the memory interface 240 can also transmit commands and addresses.

[0040] The host interface 210 and the memory interface 240 may perform a cyclic redundancy check operation. In the embodiment described below, the host interface 210 is described as performing the cyclic redundancy check operation, but this embodiment may also be applied to the memory interface 240.

[0041] Figure 3 Showing an embodiment according to the present disclosure Figure 2 host interface 210 .

[0042] Reference Figure 3 , the host interface 210 may include a buffer 31 and a cyclic redundancy check (CRC) controller 32 .

[0043] The buffer 31 may temporarily store data DATA received from the host 2000. Therefore, as the size of the channel 21 connected to the host 2000 increases, the size of the data DATA stored in the buffer 31 may increase. For example, assuming that N bits of data (N is a positive integer) are input through the channel 21 during one cycle, N bits of first data DATA1 may be input to the buffer 31 during the first cycle, N bits of second data DATA2 may be input to the buffer 31 during the second cycle, N bits of third data DATA3 may be input to the buffer 31 during the third cycle, and N bits of fourth data DATA4 may be input to the buffer 31 during the fourth cycle.

[0044] The CRC controller 32 can generate a first cyclic redundancy check code CRCC1 by performing a cyclic redundancy check operation on the first data DATA1, and output a first data set DATA1+CRCC1 including the first data DATA1 and the first cyclic redundancy check code CRCC1. In this way, the CRC controller 32 can sequentially output the second to fourth data sets DATA2+CRCC2, DATA3+CRCC3, and DATA4+CRCC4 by performing a cyclic redundancy check operation on each of the remaining second to fourth data DATA2 to DATA4.

[0045] However, as the size of data processed by the memory system 1000 increases, N may increase, and the complexity of the cyclic redundancy check operation increases as N increases. Therefore, the time taken for the CRC controller 32 to output the first to fourth data sets DATA1+CRCC1, DATA2+CRCC2, DATA3+CRCC3, and DATA4+CRCC4 may increase.

[0046] Therefore, in this embodiment, the data DATA stored in the buffer 31 can be divided into multiple data groups, each data group includes multiple bits less than N, and a cyclic redundancy check operation can be performed on the data group as a unit, that is, a cyclic redundancy check operation can be performed on each data group.

[0047] Figure 4 The method of dividing data according to the embodiment is shown. Figure 2 and Figure 3 describe Figure 4 The method shown.

[0048] Reference Figure 4, assuming that the size of the data DATA received through the channel 21 in each cycle is N bits. The CRC controller 32 can divide the N-bit data DATA stored in the buffer 31 into m data groups DTG1 to DTGm. Each of the data groups DTG1 to DTGm can be composed of K bits of data. That is, since the N-bit data DATA is divided into m data groups, and each data group is composed of K bits, K is N / m.

[0049] For example, when N-bit first data DATA1 is input to the buffer 31, the first data DATA1 may be divided into (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m, and each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m may include K bits of data. The second data DATA2 input in the next cycle of the first data DATA1 may also be divided into (2-1)th to (2-m)th data groups DTG2-1 to DTG2-m. The third and fourth data DATA3 and DTG4 may also be divided into (3-1)th to (3-m)th data groups DTG3-1 to DTG3-m and (4-1)th to (4-m)th data groups DTG4-1 to DTG4-m, respectively.

[0050] Alternatively, the data DATA may be divided into a plurality of data groups, the number of which corresponds to the number of lanes through which the data DATA is transmitted between the host 2000 and the controller 1200. For example, when the lane 21 includes two lanes, the data DATA may be divided into first and second data groups DTGi-1 and DTGi-2, and when the lane 21 includes four lanes, the data DATA may be divided into first to fourth data groups DTGi-1 to DTGi-4.

[0051] The buffer 31 may include a plurality of cells capable of storing data, and each cell may store 1 bit of data. For example, since the (1-1)th data group DTG1-1 includes K bits of data, the K bits of data of the (1-1)th data group DTG1-1 may be stored in the first to Kth cells R1 to RK, respectively. The first to Kth cells R1 to RK may also be allocated to each of the remaining data groups, and 1 bit of data may be stored in each cell. For another example, the buffer 31 may include a plurality of cell groups corresponding to the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m, respectively, each cell group including K cells, and the K cells respectively store the K bits of data included in the corresponding data groups in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m.

[0052] In this embodiment, a cyclic redundancy check code CRCC may be determined for each data group, and a specific embodiment thereof is described below.

[0053] Figure 5 is a flowchart illustrating a method of operating a controller according to a first embodiment of the present disclosure. Figure 4 To describe Figure 5 The method shown.

[0054] Reference Figure 5 , when data DATA including N bits is input to the buffer 31 , the CRC controller 32 may divide the N-bit data DATA into first to m-th data groups DTG1 to DTGm.

[0055] Subsequently, at S51, the CRC controller 32 may generate compressed data DATA_CP by compressing the data DATA of the first to mth data groups DTG1 to DTGm. For example, the CRC controller 32 may generate compressed data DATA_CP having K bits by logically combining the data selected from the first to mth data groups DTG1 to DTGm and stored in corresponding cells.

[0056] At S52, the CRC controller 32 may generate a cyclic redundancy check code CRCC by performing a cyclic redundancy check operation on the compressed data DATA_CP having K bits. Since the compressed data DATA_CP includes K-bit data, which is less than the N-bit data DATA, the complexity of the cyclic redundancy check operation performed by the CRC controller 32 may be reduced, thereby reducing the time required to perform the cyclic redundancy check operation.

[0057] At S53 , when generating the cyclic redundancy check code CRCC, the CRC controller 32 may output a data set DATA+CRCC in which the cyclic redundancy check code CRCC is added to the data DATA.

[0058] The following describes in more detail the Figure 5 The method of the first embodiment is described.

[0059] Figure 6A and Figure 6B A method of operating a controller according to the first embodiment of the present disclosure is specifically illustrated.

[0060] Figure 6AA method of generating a cyclic redundancy check code CRCC for first data DATA1 is shown. When N-bit first data DATA1 is input to buffer 31, first data DATA1 may be divided into (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. Each of (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m may include K-bit data, which is smaller than N-bit data.

[0061] At S51, compressed data DATA_CP may be generated by performing an XOR operation on the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. For example, the CRC controller 32 may generate compressed data DATA_CP by performing an XOR operation on 1-bit data at the same position in each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. In other words, the value obtained by performing an XOR operation on m data may be 1-bit data of the compressed data DATA_CP, wherein each of the m data is selected from each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. In this way, the CRC controller 32 may generate compressed data DATA_CP including K bits, wherein each of the K bits is obtained by performing an XOR operation on m data at the same position in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. For example, an XOR operation is performed on the first bit among K bits in each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m to generate the first bit of the compressed data DATA_CP.

[0062] At S52, when generating the compressed data DATA_CP, the CRC controller 32 may generate a cyclic redundancy check code CRCC by performing a cyclic redundancy check operation on the compressed data DATA_CP. The cyclic redundancy check code CRCC may be generated to include L bits. L may be a positive integer and may vary according to the cyclic redundancy check operation.

[0063] Since the CRC controller 32 generates the cyclic redundancy check code CRCC using the K-bit compressed data DATA_CP instead of the N-bit first data DATA1 stored in the buffer 31, the cyclic redundancy check code CRCC can be generated more quickly than when the operation is performed using the N-bit first data DATA1. Figure 5 and Figure 6A Described processes S51 and S52.

[0064] Reference Figure 6B, at S51, compressed data DATA_CP can be generated by performing an XOR operation on 1-bit data included in each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. For example, when each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m (including K bits) is stored in the first to K-th units R1 to RK, the value obtained by performing an XOR operation on the m data stored in the first unit R1 in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m can be the first compressed data C1 of the compressed data DATA_CP; the value obtained by performing an XOR operation on the m data stored in the second unit R2 in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m can be the first compressed data C1 of the compressed data DATA_CP. The value obtained by the operation may be the second compressed data C2 of the compressed data DATA_CP; the value obtained by performing an XOR operation on the m data stored in the third unit R3 in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m may be the third compressed data C3 of the compressed data DATA_CP; and the value obtained by performing an XOR operation on the m data stored in the Kth unit RK in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m may be the Kth compressed data CK of the compressed data DATA_CP. Therefore, the number of bits included in the compressed data DATA_CP is the same as the number of bits included in each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. For example, assuming that each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m includes K bits of data as shown above, the compressed data DATA_CP may also include K bits of data.

[0065] At S52, the CRC controller 32 may generate an L-bit cyclic redundancy check code CRCC by performing a cyclic redundancy check operation on the K-bit compressed data DATA_CP. That is, in the prior art, the cyclic redundancy check operation is performed using N-bit data, but in this embodiment, the cyclic redundancy check operation is performed using K-bit compressed data DATA_CP, which is smaller than the N-bit data. Therefore, the cyclic redundancy check operation can be simplified and its operation time can also be shortened.

[0066] Figure 7 is a flowchart illustrating a method of operating a controller according to a second embodiment of the present disclosure. Figure 4 To describe Figure 7 The method shown.

[0067] Reference Figure 7, when data DATA including N bits is input to the buffer 31 , the CRC controller 32 may divide the N-bit data DATA into first to m-th data groups DTG1 to DTGm.

[0068] At S71, the CRC controller 32 may generate first to mth cyclic redundancy check codes CRCC1 to CRCCm corresponding to the respective first to mth data groups DTG1 to DTGm. For example, the CRC controller 32 may generate the first cyclic redundancy check code CRCC1 by processing the data included in the first data group DTG1, and generate the mth cyclic redundancy check code CRCCm by processing the data included in the mth data group DTGm. When each of the first to mth data groups DTG1 to DTGm includes K-bit data, since the first to mth cyclic redundancy check codes CRCC1 to CRCCm are generated using K bits, which is less than N bits, the time required to perform the cyclic redundancy check operation can be reduced compared to a case where N bits of data are used.

[0069] Subsequently, at S72 , the CRC controller 32 may generate a cyclic redundancy check code CRCC by compressing the first to mth cyclic redundancy check codes CRCC1 to CRCCm.

[0070] At S73 , when generating the cyclic redundancy check code CRCC, the CRC controller 32 may output a data set DATA+CRCC in which the cyclic redundancy check code CRCC is added to the data DATA.

[0071] The following describes in more detail the Figure 7 The method of the second embodiment is described.

[0072] Figure 8 A method of operating a controller according to the second embodiment of the present disclosure is specifically illustrated.

[0073] Reference Figure 8 , when N-bit first data DATA1 is input to the buffer 31 , the CRC controller 32 may divide the first data DATA1 into (1-1)th to (1-m)th data groups DTG1 - 1 to DTG1 - m.

[0074] Assuming that each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m includes K bits of data, at S71, first to mth cyclic redundancy check codes CRCC1 to CRCCm corresponding to the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m, respectively, may be generated as L-bit codes, where L bits are less than K bits. For example, the CRC controller 32 may generate a first cyclic redundancy check code CRCC1 for the data included in the (1-1)th data group DTG1-1, and a second cyclic redundancy check code CRCC2 for the data included in the (1-2)th data group DTG1-2. In this way, the CRC controller 32 may generate first to mth cyclic redundancy check codes CRCC1 to CRCCm corresponding to the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m, respectively.

[0075] At S72, a cyclic redundancy check code CRCC may be generated by performing an XOR operation on the data at the same position in the first to mth cyclic redundancy check codes CRCC1 to CRCCm. Figure 6B S72 is performed using a method similar to the method described in S51. That is, assuming that each of the first to mth cyclic redundancy check codes CRCC1 to CRCCm is stored in the first to Lth cells, the value obtained by performing an XOR operation on the m data stored in the first cell of the first to mth cyclic redundancy check codes CRCC1 to CRCCm can become the first bit of the cyclic redundancy check code CRCC, and the value obtained by performing an XOR operation on the m data stored in the second cell of the first to mth cyclic redundancy check codes CRCC1 to CRCCm can become the second bit of the cyclic redundancy check code CRCC. In this way, when an XOR operation is performed on the m data stored in the Lth cell of the first to mth cyclic redundancy check codes CRCC1 to CRCCm, an L-bit cyclic redundancy check code CRCC can be ultimately generated.

[0076] At S73 , a first data set DATA1+CRCC in which a cyclic redundancy check code CRCC is added to the first data DATA1 may be output.

[0077] Figure 9 is a flowchart illustrating a method of operating a controller according to a third embodiment of the present disclosure. Figure 4 To describe Figure 9 The method shown.

[0078] Reference Figure 9, when N-bit data DATA is input to the buffer 31 , the CRC controller 32 may divide the data DATA into first to m-th data groups DTG1 to DTGm, each data group including K bits.

[0079] At S91, the CRC controller 32 can calculate the first to mth count values CTV1 to CTVm by counting the number of selected data included in each of the first to mth data groups DTG1 to DTGm. For example, when the selected data is 1, the number of data 1 included in the first data group DTG1 can be counted and determined as the first count value CTV1. Each of the first to mth count values CTV1 to CTVm can be generated as a binary notation code. The number of bits included in each of the first to mth count values CTV1 to CTVm can be the same. For example, when the first count value CTV1 includes J bits of data (J is a positive integer), each of the remaining second to mth count values CTV2 to CTVm can also include J bits of data.

[0080] Afterwards, at S92, the CRC controller 32 may generate compressed count values CTV_CP for the first to mth count values CTV1 to CTVm. For example, the value obtained by performing an XOR operation on all bits included in the first count value CTV1 may become the first compressed data of the compressed count value CTV_CP, and the value obtained by performing an XOR operation on all bits included in the second count value CTV2 may become the second compressed data of the compressed count value CTV_CP. In this way, the value obtained by performing an XOR operation on each of the remaining third to mth count values CTV3 to CTVm may become the third to mth compressed data of the compressed count value CTV_CP. Therefore, the number of bits of the compressed count value CTV_CP is the same as the number of data groups DTG1 to DTGm.

[0081] At S93, the CRC controller 32 may generate a total count value CV by processing the compressed count value CTV_CP. For example, the total count value CV may be a value obtained by performing an XOR operation on all bits of the compressed count value CTV_CP.

[0082] At S94, the CRC controller 32 may compress the data DATA of the first to mth data groups DTG1 to DTGm to generate compressed data DATA_CP. For example, the CRC controller 32 may logically combine the data selected from the first to mth data groups DTG1 to DTGm and stored in the same position to generate compressed data DATA_CP having K bits.

[0083] At S95, the CRC controller 32 may generate a cyclic redundancy check code CRCC by performing a cyclic redundancy check operation on the compressed data DATA_CP having K bits. Since the compressed data DATA_CP includes K bits which is smaller than N bits, the cyclic redundancy check operation performed by the CRC controller 32 may be simplified, thereby shortening the time required for the cyclic redundancy check operation.

[0084] Among the above-mentioned S91 to S95 , the order between S91 to S93 for generating the total count value CV and S94 to S95 for generating the cyclic redundancy check code CRCC may be changed.

[0085] At S96, the CRC controller 32 may generate a cyclic redundancy check count code CRCCv by logically combining the cyclic redundancy check code CRCC and the total count value CV. For example, the cyclic redundancy check count code CRCCv may be calculated by performing an XOR operation on the cyclic redundancy check code CRCC and the total count value CV.

[0086] At S97 , when the cyclic redundancy check count code CRCCv is generated, the CRC controller 32 may output a data set DATA+CRCCv in which the cyclic redundancy check count code CRCCv is added to the data DATA.

[0087] The following describes in more detail the Figure 9 The operating method of the third embodiment is described.

[0088] Figure 10A and Figure 10B A method of operating a controller according to a third embodiment of the present disclosure is specifically illustrated.

[0089] Reference Figure 10A , specifically showing the reference Figure 9 S91 to S93 described.

[0090] At S91, the number of selected data included in each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m of the first data DATA1 can be calculated as the first to mth count values CTV1 to CTVm. For example, it is assumed that the selected data is 1 and each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m includes K bits of data. In this case, each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m can include K bits of data stored in the first to Kth cells R1 to RK, respectively. When describing the (1-1)th data group DTG1-1 as an example, the data included in the (1-1)th data group DTG1-1 can be stored in the first to Kth cells R1 to RK, each cell including 1 bit of data. The data stored in each cell includes 0 or 1, and 1 is the selected data in this embodiment. Therefore, the CRC controller 32 can calculate the first count value CTV1 by counting the number of data 1 included in the (1-1)th data group DTG1-1. Each of the first to mth count values CTV1 to CTVm can be generated as a binary notation code. The number of bits of each of the first to mth count values CTV1 to CTVm can be the same. For example, when the first count value CTV1 includes a J-bit code (J is a positive integer), each of the remaining second to mth count values CTV2 to CTVm can also include a J-bit code.

[0091] For example, assuming that K is 32, since the data of the (1-1)th data group DTG1-1 includes 32 bits, the maximum number of data 1 included in each data group is 32. When the decimal number 32 is converted to a binary number, 32 becomes 100000, so J can be set to an integer of at least 6 or greater. That is, the first count value CTV1 can include at least 6 bits of data. In an embodiment, assuming that the data of the (1-1)th data group DTG1-1 includes 32-bit data 01000111010101110010101010000101, the number of data 1 included in the (1-1)th data group DTG1-1 is 15. The CRC controller 32 can convert the count value, i.e., 15, into a binary number 001111, and the converted value 001111 can be the first count value CTV1. In this way, the remaining second to mth count values CTV2 to CTVm can be calculated.

[0092] At S92 , the CRC controller 32 may generate an m-bit compressed count value CTV_CP by performing an XOR operation on each of the first to mth count values CTV1 to CTVm.

[0093] For example, the value obtained by performing an XOR operation on all bits included in the first count value CTV1 can be the first compressed data C1 of the compressed count value CTV_CP, and the value obtained by performing an XOR operation on all bits included in the second count value CTV2 can be the second compressed data C2 of the compressed count value CTV_CP. In this way, the value obtained by performing an XOR operation on each of the remaining third to mth count values CTV3 to CTVm can be the third to mth compressed data of the compressed count value CTV_CP. Therefore, the number of bits of the compressed count value CTV_CP is m, where m is the same as the number of data groups DTG1-1 to DTG1-m.

[0094] At S93, the CRC controller 32 may generate a total count value CV by processing the compressed count value CTV_CP. For example, the total count value CV may be obtained by performing an XOR operation on all bits, ie, m bits, of the compressed count value CTV_CP.

[0095] Reference Figure 10B , specifically showing the reference Figure 9 S94 to S96 described.

[0096] At S94 , compressed data DATA_CP may be generated by performing an XOR operation on data stored in cells at the same position in the (1-1)th to (1-m)th data groups DTG1 - 1 to DTG1 - m. For example, the value obtained by performing an XOR operation on the m data in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m and stored in the first unit R1 can be the first compressed data C1 of the compressed data DATA_CP; the value obtained by performing an XOR operation on the m data in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m and stored in the second unit R2 can be the second compressed data C2 of the compressed data DATA_CP; the value obtained by performing an XOR operation on the m data in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m and stored in the third unit R3 can be the third compressed data C3 of the compressed data DATA_CP; and, the value obtained by performing an XOR operation on the m data in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m and stored in the Kth unit RK can be the Kth compressed data CK of the compressed data DATA_CP. Therefore, the number of bits of the compressed data DATA_CP is the same as the number of bits of each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. For example, assuming that each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m includes K bits of data, the compressed data DATA_CP may also be generated to have K bits of data.

[0097] At S95, the CRC controller 32 can generate a cyclic redundancy check code CRCC including L bits by performing a cyclic redundancy check operation using the K-bit compressed data DATA_CP. In the prior art, the cyclic redundancy check operation is performed by using N-bit data, while in this embodiment, the cyclic redundancy check operation is performed by using K-bit compressed data DATA_CP, which is smaller than the N-bit data. Therefore, in this embodiment, the cyclic redundancy check operation can be simplified and its operation time can also be shortened.

[0098] At S96 , the CRC controller 32 may generate a cyclic redundancy check count code CRCCv by performing an XOR operation on the cyclic redundancy check code CRCC and the total count value CV.

[0099] Figure 11 is a flowchart illustrating a method of operating a controller according to a fourth embodiment of the present disclosure. Figure 4 describe Figure 11 method.

[0100] Reference Figure 11 , when data DATA including N bits is input to the buffer 31 , the CRC controller 32 may divide the data DATA into first to mth data groups DTG1 to DTGm, each data group including K bits of data.

[0101] At S111, the CRC controller 32 can calculate the first to mth count values CTV1 to CTVm by counting the number of selected data included in each of the first to mth data groups DTG1 to DTGm. For example, when the selected data is 1, the number of data 1 included in the first data group DTG1 can be calculated as the first count value CTV1. Each of the first to mth count values CTV1 to CTVm can be generated as a binary notation code. The number of bits of the first to mth count values CTV1 to CTVm can be the same. For example, when the first count value CTV1 includes J bits of data (J is a positive integer), each of the remaining second to mth count values CTV2 to CTVm can also include J bits of data.

[0102] At S112, the CRC controller 32 may generate a sub-count value CTV_S by processing the first to m-th count values CTV1 to CTVm. The sub-count value CTV_S includes J-bit data. For example, a value obtained by performing an XOR operation on all data constituting the first to m-th count values CTV1 to CTVm may be generated as the sub-count value CTV_S.

[0103] At S113 , the CRC controller 32 may generate a total count value CV by processing the sub-count value CTV_S. For example, the total count value CV may be obtained by performing an XOR operation on all bits of the sub-count value CTV_S.

[0104] At S114, the CRC controller 32 may compress the data DATA of the first to mth data groups DTG1 to DTGm to generate compressed data DATA_CP. For example, the CRC controller 32 may logically combine data stored in cells at the same position among the data in the first to mth data groups DTG1 to DTGm to generate compressed data DATA_CP having K bits.

[0105] At S115, the CRC controller 32 may generate a cyclic redundancy check code CRCC by processing the compressed data DATA_CP having K bits. Since the compressed data DATA_CP includes K bits of data which is smaller than the N bits of data, the cyclic redundancy check operation performed by the CRC controller 32 may be simplified, thereby shortening the time required for the cyclic redundancy check operation.

[0106] Among the above-mentioned S111 to S115 , the order between S111 to S113 for generating the total count value CV and S114 to S115 for generating the cyclic redundancy check code CRCC may be changed.

[0107] At S116, the CRC controller 32 may generate a cyclic redundancy check count code CRCCv by logically combining the cyclic redundancy check code CRCC and the total count value CV. For example, the cyclic redundancy check count code CRCCv may be calculated by performing an XOR operation on the cyclic redundancy check code CRCC and the total count value CV.

[0108] At S117 , when the cyclic redundancy check count code CRCCv is generated, the CRC controller 32 may output a data set DATA+CRCCv in which the cyclic redundancy check count code CRCCv is added to the data DATA.

[0109] The following describes in more detail the Figure 11 The operating method of the fourth embodiment is described.

[0110] Figure 12A and Figure 12B A method of operating a controller according to a fourth embodiment of the present disclosure is specifically illustrated.

[0111] Reference Figure 12A , specifically showing the reference Figure 11 S111 to S113 described.

[0112] At S111, the number of selected data included in each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m can be calculated as the first to mth count values CTV1 to CTVm. For example, it is assumed that the selected data is 1, and each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m includes K bits of data. In this case, each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m can include data stored in the first to Kth units R1 to RK. When describing the (1-1)th data group DTG1-1 as an example, the data included in the (1-1)th data group DTG1-1 can be stored in the first to Kth units R1 to RK with 1 bit. The data includes 0 or 1, and 1 is the selected data in this embodiment. Therefore, the CRC controller 32 can calculate the first count value CTV1 by counting the number of data 1 included in the (1-1)th data group DTG1-1. Each of the first to mth count values CTV1 to CTVm can be generated as a binary notation code. The number of bits included in each of the first to mth count values CTV1 to CTVm can be the same. For example, when the first count value CTV1 includes a J-bit code (J is a positive integer), each of the remaining second to mth count values CTV2 to CTVm can also include a J-bit code.

[0113] At S112 , the CRC controller 32 may generate a sub count value CTV_S including J-bit data by performing an XOR operation on the first to mth count values CTV1 to CTVm.

[0114] At S113 , the CRC controller 32 may generate a total count value CV by processing the sub-count values CTV_S. For example, the total count value CV may be obtained by performing an XOR operation on all bits of the compressed count value CTV_CP.

[0115] Reference Figure 12B , specifically showing the reference Figure 11 Steps S114 to S116 are described.

[0116] At S114 , compressed data DATA_CP may be generated by performing an XOR operation on data at the same position in the (1-1)th to (1-m)th data groups DTG1 - 1 to DTG1 - m. For example, the value obtained by performing an XOR operation on the data stored in the first unit R1 in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m may be the first compressed data C1 of the compressed data DATA_CP; the value obtained by performing an XOR operation on the data stored in the second unit R2 in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m may be the second compressed data C2 of the compressed data DATA_CP; the value obtained by performing an XOR operation on the data stored in the third unit R3 in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m may be the third compressed data C3 of the compressed data DATA_CP; and, the value obtained by performing an XOR operation on the data stored in the Kth unit RK in the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m may be the Kth compressed data CK of the compressed data DATA_CP. Therefore, the number of bits of the compressed data DATA_CP is the same as the number of bits of each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m. For example, assuming that each of the (1-1)th to (1-m)th data groups DTG1-1 to DTG1-m includes K bits of data, the compressed data DATA_CP can also be generated to have K bits of data.

[0117] At S115 , the CRC controller 32 may generate a cyclic redundancy check code CRCC including L bits by performing a cyclic redundancy check operation using the K-bit compressed data DATA_CP.

[0118] At S116, the CRC controller 32 may calculate a cyclic redundancy check count code CRCCv by performing an XOR operation on the cyclic redundancy check code CRCC and the total count value CV. The cyclic redundancy check count code CRCCv may include L bits.

[0119] Figure 13 A memory card system 3000 to which the controller of the present disclosure is applied is shown.

[0120] Reference Figure 13 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0121] The controller 3100 is connected to the memory device 3200. The controller 3100 is configured to access the memory device 3200. For example, the controller 3100 may be configured to control a program operation, a read operation, or an erase operation of the memory device 3200 or control a background operation. The controller 3100 may perform a reference operation. Figure 2 The functions of the controller 3100 are described. The controller 3100 is configured to provide an interface between the memory device 3200 and a host (not shown). The controller 3100 is configured to drive firmware for controlling the memory device 3200.

[0122] For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction circuit.

[0123] The controller 3100 can communicate with an external device (e.g., a host) through the connector 3300. The controller 3100 can communicate with the external device according to one or more of the following communication standards: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WIFI, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the above-mentioned communication standards.

[0124] For example, the memory device 3200 can be configured by one or more of various non-volatile memory devices such as: electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), spin transfer torque magnetic RAM (STT-MRAM), etc.

[0125] The controller 3100 and the memory device 3200 can be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a standard flash card (CF), a smart media card (SM or SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC or eMMC), an SD card (SD, mini SD, micro SD or SDHC), a universal flash memory (UFS), etc.

[0126] Figure 14 A solid-state drive (SSD) system 4000 to which the controller of the present disclosure is applied is shown.

[0127] Reference Figure 14 , an SSD system 4000 includes a host 4100 and an SSD 4200. The SSD 4200 exchanges signals with the host 4100 through a signal connector 4001 and receives power through a power connector 4002. The SSD 4200 includes a controller 4210, a plurality of non-volatile memories (NVMs) 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0128] The controller 4210 may perform a reference Figure 2 The functions of the controller 1200 are described.

[0129] The controller 4210 may control the plurality of non-volatile memories 4221 to 422n in response to a signal received from the host 4100. For example, the signal may include a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WIFI, Bluetooth, and NVMe.

[0130] The auxiliary power supply 4230 is connected to the host 4100 via the power connector 4002. The auxiliary power supply 4230 can receive a power voltage from the host 4100 and be charged using the power voltage. When the power supply from the host 4100 is unstable, the auxiliary power supply 4230 can provide a power voltage to the SSD 4200. For example, the auxiliary power supply 4230 can be located in the SSD 4200 or external to the SSD 4200. For example, the auxiliary power supply 4230 can be located on the motherboard and can provide auxiliary power to the SSD 4200.

[0131] The buffer memory 4240 serves as a buffer memory for the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of non-volatile memories 4221 to 422n, or may temporarily store metadata (e.g., a mapping table) of the non-volatile memories 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, or the like, or a non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, or the like.

Claims

1. A controller comprising: A buffer storing N bits of data; as well as a cyclic redundancy check controller that divides the N-bit data stored in the buffer into m data groups each including K-bit data, generates compressed data including K bits by processing the data included in the m data groups, and generates a cyclic redundancy check code using the compressed data, The cyclic redundancy check controller further counts the number of selected data included in each of the m data groups and generates a plurality of count values corresponding to the m data groups respectively, each of the count values including J-bit data, where J is a positive integer.

2. The controller according to claim 1, wherein N, m and K are positive integers, and N satisfies m×K.

3. The controller according to claim 1, wherein the buffer includes a plurality of cell groups corresponding to the m data groups respectively, each cell group includes K cells, and the K cells of each cell group respectively store K bits of data included in a corresponding data group among the m data groups.

4. The controller of claim 3 , wherein the cyclic redundancy check controller generates compressed data comprising K bits, each of the K bits being obtained by performing an XOR operation on data stored in an I-th cell of the cell group, where I ranges from 1 to K. 5 . The controller according to claim 1 , wherein the cyclic redundancy check controller further outputs a data set obtained by adding the cyclic redundancy check code to the N-bit data.

6. The controller according to claim 1, wherein the cyclic redundancy check controller further generates a compressed count value by logically combining data constituting the plurality of count values, and generates a total count value by performing an XOR operation on data included in the compressed count value.

7. The controller according to claim 6, wherein the cyclic redundancy check controller further generates a cyclic redundancy check count code by performing an XOR operation on the total count value and the cyclic redundancy check code, and outputs a data set obtained by adding the cyclic redundancy check count code to the N-bit data.

8. The controller according to claim 1 , wherein the cyclic redundancy check controller further generates a sub-count value by performing an XOR operation on an I-th bit among J-bit data in each of the plurality of count values, and generates a total count value by performing an XOR operation on all bits of the sub-count value, where I ranges from 1 to J.

9. The controller according to claim 8, wherein the cyclic redundancy check controller generates a cyclic redundancy check count code by performing an XOR operation on the total count value and the cyclic redundancy check code, and outputs a data set obtained by adding the cyclic redundancy check count code to the N-bit data.

10. A method of operating a controller, the method comprising: Divide the input data into multiple data groups; generating a plurality of count values respectively corresponding to the plurality of data groups by counting the number of selected data included in each of the data groups; generating compressed data by logically combining the data included in the plurality of data groups in bit units; and A cyclic redundancy check code is generated by performing a cyclic redundancy check operation on the compressed data.

11. The method according to claim 10, wherein when the input data includes N bits and the plurality of data groups is m data groups, each of the plurality of data groups includes K bits of data, K is N / m, and K, m and N are positive integers.

12. The method according to claim 11, wherein when the input data is divided into the plurality of data groups, the plurality of cells included in the buffer of the controller are divided into a plurality of cell groups corresponding to the plurality of data groups, respectively, each cell group includes K cells, and the K cells respectively store K bits of data included in each of the plurality of data groups.

13. The method of claim 12 , wherein generating the compressed data comprises generating the compressed data including K bits, each of the K bits being obtained by performing an XOR operation on data stored in an I-th cell of the cell group, I ranging from 1 to K.

14. The method according to claim 10, further comprising: After the cyclic redundancy check code is generated, a data set obtained by adding the cyclic redundancy check code to the input data is output.

15. The method of claim 10, further comprising, between dividing the input data into the plurality of data groups and generating the compressed data: generating a compressed count value by performing an XOR operation on all bits included in each of the plurality of count values; and A total count value is generated by performing an XOR operation on all bits of the compressed count value.

16. The method according to claim 15, further comprising, after generating the cyclic redundancy check code: Generate a cyclic redundancy check count code by performing an XOR operation on the cyclic redundancy check code and the total value; and A data set obtained by adding the cyclic redundancy check counting code to the input data is output.

17. The method of claim 10, further comprising, between dividing the input data into the plurality of data groups and generating the compressed data: generating a sub-count value by performing an XOR operation on an I-th bit among J-bit data in each of the plurality of count values, I ranging from 1 to J; and A total count value is generated by performing an XOR operation on all bits of the sub-count values.

18. The method according to claim 17, further comprising, after generating the cyclic redundancy check code: Generate a cyclic redundancy check count code by performing an XOR operation on the cyclic redundancy check code and the total value; and A data set obtained by adding the cyclic redundancy check counting code to the input data is output.

Images