A method, device, system, electronic device and storage medium for processing missing pages

Abstract

The present application discloses a page fault processing method, device, system, electronic device and storage medium. The method includes: receiving a page fault processing request from a central processing unit, wherein the page fault processing request is triggered when the central processing unit determines that there is a page fault in a page table entry; parsing the page fault processing request to obtain the page fault processing information carried by the page fault processing request; performing a data write operation or a data read operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; and feeding back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result. The present application requests the FPGA chip to perform a page fault processing operation when the central processing unit determines that there is a page fault in a page table entry, and uses access to the FPGA chip instead of the original method of accessing the disk, which facilitates fast access by the central processing unit and no longer consumes a large amount of central processing unit resources.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a page fault processing method, device, system, electronic device and storage medium. Background Art

[0002] Modern operating systems have implemented virtual memory technology, which treats the main memory as an address space cache stored on the disk, and only saves active areas in the main memory. When the system's physical memory is insufficient, the operating system will perform page swapping, transferring pages back and forth between the disk and the main memory. Because the disk access speed is very slow, frequent disk access will inevitably lead to a decrease in system performance.

[0003] During the address mapping process, if the page to be accessed is found to be not in the memory, a page fault interrupt will be generated. When a page fault interrupt occurs, if there is no free page in the operating system memory, the operating system must select a page in the memory and move it out of the memory to make room for the page to be called in. The rule used to select which page to eliminate is called the page replacement algorithm. Currently, the commonly used page replacement algorithms are the best replacement algorithm (OPT), the first-in-first-out replacement algorithm (FIFO), and the least recently used algorithm (LRU).

[0004] The above algorithms are considered from the software perspective. They use reasonable swap strategies to reduce the page swap between main memory and disk, thereby reducing the number of page swaps. However, the swap medium is still disk or flash memory. It takes hundreds of clock cycles for the CPU to access the main memory, while it takes millions of clock cycles to access the disk. Therefore, each page swap consumes a lot of CPU resources, which reduces the overall performance. Summary of the invention

[0005] In order to solve the above technical problems or at least partially solve the above technical problems, the present application provides a page fault processing method, device, system, electronic device and storage medium.

[0006] According to one aspect of an embodiment of the present application, a page fault processing method is provided, which is applied to an FPGA chip, and the method includes:

[0007] Receiving a page fault processing request from a central processing unit, wherein the page fault processing request is triggered when the central processing unit determines that a page fault exists in a page table entry;

[0008] Parsing the page fault processing request to obtain page fault processing information carried by the page fault processing request;

[0009] Performing a data write operation or a data read operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip;

[0010] The processing result is fed back to the central processing unit so that the central processing unit updates the page table entry according to the processing result.

[0011] Further, the parsing of the page fault handling request to obtain the page fault handling information carried by the page fault handling request includes:

[0012] Invoke a computer quick link protocol to parse the page fault processing request to obtain original page fault processing information;

[0013] A target identifier and associated data of the target identifier are extracted from the original page fault processing information, and the target identifier and the associated data are determined as the page fault processing information, wherein the target identifier is used to indicate the execution of a data write operation or a data read operation.

[0014] Furthermore, before performing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result, the method further includes:

[0015] The target storage object is determined based on the target identifier in the page fault processing information, wherein, when the target identifier is used to indicate the execution of a data write operation, the target storage object is the memory of the FPGA chip, and when the target identifier is used to indicate the execution of a data read operation, the target storage object is the random access memory of the FPGA chip.

[0016] Further, performing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result includes:

[0017] When the target identifier carried in the page fault processing information is used to indicate the execution of a data write operation, an interrupt operation is performed on the communication link between the FPGA chip and the central processing unit;

[0018] Detecting whether the first data exists in the buffer connected to the FPGA chip;

[0019] In the case where the first data exists in the buffer, writing the first data from the buffer to the memory, wherein the first data is the data written to the buffer by the central processor after the communication link is interrupted;

[0020] The page table information of the page table in the memory is updated by using the first data to obtain updated page table information, and the updated page table information is determined as the processing result.

[0021] Further, performing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result includes:

[0022] When the target identifier carried in the page fault processing information is used to indicate the execution of a data read operation, obtaining the page fault address from the associated data of the target identifier;

[0023] Query whether the missing page address exists in the buffer connected to the FPGA chip, and obtain a query result;

[0024] Execute the data reading operation corresponding to the query result to obtain the processing result.

[0025] Further, the executing the data reading operation corresponding to the query result includes:

[0026] If the query result indicates that the page fault address exists, generating first notification information, wherein the first notification information is used to notify the central processor to read second data corresponding to the page fault address from the buffer;

[0027] When the query result is that the page fault address does not exist, update data is read from the MEM controller connected to the FPGA chip, the update data is written into the buffer, the cache information in the random access memory is updated, and a second notification message is sent to the central processing unit, wherein the second notification message is used to notify the central processing unit to read the second data corresponding to the page fault address from the buffer.

[0028] According to another aspect of an embodiment of the present application, a page fault processing device is provided, including:

[0029] A receiving module, configured to receive a page fault processing request from a central processing unit, wherein the page fault processing request is triggered when the central processing unit determines that a page fault exists in a page table entry;

[0030] A parsing module, used for parsing the page fault processing request to obtain the page fault processing information carried by the page fault processing request;

[0031] An execution module, configured to execute a data write operation or a data read operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip;

[0032] The sending module is used to feed back the processing result to the central processing unit, so that the central processing unit updates the page table entry according to the processing result.

[0033] According to another aspect of the embodiment of the present application, a page fault processing system is also provided, including: a central processing unit and an FPGA chip;

[0034] The central processing unit is used to obtain a virtual address, generate a page table entry address according to the virtual address, read a page table entry from a memory according to the page table entry address, and detect the page table entry. If there is a page fault in the page table entry, a page fault processing request is sent to the FPGA chip;

[0035] The FPGA chip is used to receive a page fault processing request from a central processing unit; parse the page fault processing request to obtain page fault processing information carried by the page fault processing request; perform a data write operation or a data read operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; and feed back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.

[0036] According to another aspect of an embodiment of the present application, a storage medium is further provided, which includes a stored program, and the above steps are executed when the program is run.

[0037] According to another aspect of an embodiment of the present application, there is also provided an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; wherein: the memory is used to store computer programs; and the processor is used to execute the steps in the above method by running the program stored in the memory.

[0038] The embodiment of the present application also provides a computer program product including instructions, which, when executed on a computer, enables the computer to execute the steps in the above method.

[0039] The above technical solution provided by the embodiment of the present application has the following advantages over the prior art: when the central processing unit determines that a page fault exists in a page table entry, the present application requests the FPGA chip to perform a page fault processing operation, and uses access to the FPGA chip instead of the original method of accessing the disk, which facilitates fast access by the central processing unit and no longer requires the consumption of a large amount of central processing unit resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0042] Figure 1 A flow chart of a page fault processing method provided in an embodiment of the present application;

[0043] Figure 2 An internal schematic diagram of an FPGA chip provided in an embodiment of the present application;

[0044] Figure 3 A flowchart of a page fault processing method provided by another embodiment of the present application;

[0045] Figure 4 A block diagram of a page fault processing device provided in an embodiment of the present application;

[0046] Figure 5 A block diagram of a page fault processing system provided in an embodiment of the present application;

[0047] Figure 6 An external schematic diagram of an FPGA chip provided in an embodiment of the present application;

[0048] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0050] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another similar entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0051] The embodiments of the present application provide a method, device, system, electronic device and storage medium for processing a page fault. The method provided by the embodiments of the present invention can be applied to any required electronic device, for example, it can be an electronic device such as a server or a terminal, which is not specifically limited here. For the convenience of description, it is referred to as an electronic device in the following.

[0052] According to one aspect of the embodiments of the present application, a method embodiment of a page fault processing method is provided. Figure 1 A flow chart of a page fault processing method provided in an embodiment of the present application is shown in FIG1 , and the method includes:

[0053] Step S11, receiving a page fault processing request from a central processing unit, wherein the page fault processing request is triggered when the central processing unit determines that a page fault exists in a page table entry.

[0054] The method provided in the embodiment of the present application is applied to an FPGA chip, and the FPGA chip is deployed in a page fault processing system, and the FPGA chip is connected to a central processing unit in the page fault processing system. It should be noted that the central processing unit will obtain a virtual address, generate a page table entry address according to the virtual address, read a page table entry from the memory according to the page table entry address, and detect the page table entry. If there is a page fault in the page table entry, a page fault processing request is sent to the FPGA chip. After receiving the page fault processing request, the FPGA chip will perform a corresponding page fault processing operation according to the page fault processing request.

[0055] Specifically, Figure 2As shown in the figure, the FPGA chip includes: CXL subsystem (including CXL.io, CXL.mem subprotocol layer, CXL Coherency Engine and CXL phy), fast table control unit, bus arbitration management module, MEM controller, control register, status register, etc. Among them, CXL.io subprotocol is used to realize IO communication between HOST and FPGA, including link training, command sending, msi-x interrupt and other functions, CXL.mem subprotocol is used for MEM access control, and TLB fast table control unit is a cache for MEM. The bus arbitration management module is responsible for the access arbitration of multiple MEMs.

[0056] In an embodiment of the present application, before receiving a page fault processing request, the FPGA chip will initialize the communication link between the FPGA chip and the central processing unit to wait for the central processing unit to send a page fault processing request. After the page fault processing request exists in the communication link, the CXL.Engine of the FPGA chip will receive the page fault processing request.

[0057] Step S12, parsing the page fault processing request to obtain the page fault processing information carried by the page fault processing request.

[0058] In the embodiments of the present application, Figure 3 As shown, step S12, parsing the page fault processing request to obtain the page fault processing information carried by the page fault processing request, includes the following steps A1-A2:

[0059] Step A1, calling the computer quick link protocol to parse the page fault processing request to obtain original page fault processing information.

[0060] In the embodiment of the present application, the FPGA chip will call the computer fast link protocol (CXL.io sub-protocol) to parse the page fault processing request, and the original page fault processing information obtained includes: target identifier, data source, address, page fault or exchange information. Among them, the target identifier is used to indicate the execution of data write operation or data read operation. It should be noted that if the target identifier is a data write identifier, a page exchange operation needs to be performed. If the target identifier is a data read identifier, a page fault operation needs to be performed.

[0061] Step A2: extracting the target identifier and the associated data of the target identifier from the original page fault processing information, and determining the target identifier and the associated data as the page fault processing information.

[0062] In an embodiment of the present application, the target identifier and the associated data of the target identifier are extracted from the original page fault processing information. When the target identifier is a data write identifier, there is no need to extract the associated data of the target identifier from the original page fault processing information. When the target identifier is a data read identifier, the page fault address is extracted from the original page fault processing information, and the page fault address is used as the associated data. After obtaining the target identifier and the associated address, the target identifier and the associated data are determined as the page fault processing information.

[0063] Step S13, performing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in an FPGA chip.

[0064] In an embodiment of the present application, before performing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result, the method also includes: determining the target storage object based on a target identifier in the page fault processing information.

[0065] In the embodiment of the present application, since the target identifier is used to indicate the execution of a data write operation or a data read operation. At this time, different target storage objects will be set according to the data read operation or the data write operation, and the memory of the FPGA chip stores a page table, and the random access memory of the FPGA chip stores a fast table. Therefore, when the target identifier is used to indicate the execution of a data write operation, the target storage object is the memory of the FPGA chip, and when the target identifier is used to indicate the execution of a data read operation, the target storage object is the random access memory of the FPGA chip.

[0066] In the embodiment of the present application, step S13, performing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result, includes the following steps B1-B4:

[0067] Step B1, when the target identifier carried in the page fault processing information is used to indicate the execution of a data write operation, an interrupt operation is performed on the communication link between the FPGA chip and the central processing unit.

[0068] Step B2, detecting whether there is first data in the buffer connected to the FPGA chip.

[0069] Step B3, when there is first data in the buffer, write the first data from the buffer into the memory, wherein the first data is data written into the buffer by the central processing unit after the communication link is interrupted.

[0070] Step B4: using the first data to update the page table information of the page table in the memory, to obtain updated page table information, and to determine the updated page table information as the processing result.

[0071] In an embodiment of the present application, when the target identifier is used to indicate the execution of a data write operation, an interrupt operation is performed on the communication link between the FPGA chip and the central processing unit. At this time, the central processing unit will detect the interruption of the communication link, and the central processing unit will directly write the first data to the buffer. It should be noted that the FPGA chip notifies the central processing unit by interrupting the communication link, so that the central processing unit sends the first data to the buffer when the communication link is interrupted.

[0072] In the embodiment of the present application, whether there is first data in the buffer of the FPGA chip, if there is first data in the buffer, the first data is written from the buffer to the memory of the FPGA chip. Then the page table information in the memory is updated, and the updated page table information is determined as the processing result. It should be noted that the embodiment of the present application sets the page table in the FPGA chip, and can store the data sent by the central processing unit in the memory of the FPGA chip when the page is exchanged, so that the page table is transferred from the system disk to the internal storage of the FPGA chip, which is convenient for the central processing unit to quickly access, does not consume a large amount of resources of the central processing unit, and improves the access efficiency of the central processing unit.

[0073] In the embodiment of the present application, step S13, performing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result, includes the following steps C1-C3:

[0074] Step C1, when the target identifier carried in the page fault processing information is used to indicate the execution of a data read operation, the page fault address is obtained from the associated data of the target identifier.

[0075] Step C2, query whether there is a missing page address in the buffer connected to the FPGA chip, and obtain the query result.

[0076] Step C3, execute the data reading operation corresponding to the query result to obtain the processing result.

[0077] In an embodiment of the present application, when the target identifier is used to indicate the execution of a data read operation, the FPGA chip can directly obtain the page fault address from the associated data, and then query whether the page fault address exists in the buffer, and perform the corresponding data read operation according to the query result.

[0078] Specifically, executing the data reading operation corresponding to the query result includes the following steps C301-C302:

[0079] When the query result indicates that there is a missing page address, first notification information is generated, and the first notification information is used to notify the central processing unit to read second data corresponding to the missing page address from the buffer.

[0080] Alternatively, when the query result shows that there is no page fault address, update data is read from the MEM controller connected to the FPGA chip, the update data is written to the buffer, the cache information in the random access memory is updated, and a second notification message is sent to the central processing unit. The second notification message is used to notify the central processing unit to read the second data corresponding to the page fault address from the buffer.

[0081] In the embodiment of the present application, when the query result is that there is a missing page address, the first notification information is used as the processing result. When the query result is that there is no missing page address, the second notification information is used as the processing result.

[0082] Step S14, feeding back the processing result to the central processor, so that the central processor updates the page table entry according to the processing result.

[0083] When the central processing unit determines that a page table entry has a page fault, the application requests the FPGA chip to perform a page fault processing operation, and uses access to the FPGA chip instead of the original method of accessing the disk, which facilitates rapid access by the central processing unit and no longer requires consuming a large amount of central processing unit resources.

[0084] Figure 4 This is a block diagram of a page fault processing device provided in an embodiment of the present application. The device can be implemented as part or all of an electronic device through software, hardware, or a combination of both. Figure 4 As shown, the device comprises:

[0085] A receiving module 31, configured to receive a page fault processing request from a central processing unit, wherein the page fault processing request is triggered when the central processing unit determines that a page fault exists in a page table entry;

[0086] The parsing module 32 is used to parse the page fault processing request and obtain the page fault processing information carried by the page fault processing request;

[0087] An execution module 33 is used to execute a data write operation or a data read operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in an FPGA chip;

[0088] The sending module 34 is used to feed back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.

[0089] In an embodiment of the present application, a parsing module is used to call a computer quick link protocol to parse a page fault processing request to obtain original page fault processing information; extract a target identifier and associated data of the target identifier from the original page fault processing information, and determine the target identifier and the associated data as page fault processing information, wherein the target identifier is used to indicate the execution of a data write operation or a data read operation.

[0090] In an embodiment of the present application, the page fault processing device also includes: a determination module, used to determine the target storage object based on the target identifier in the page fault processing information, wherein, when the target identifier is used to indicate the execution of a data write operation, the target storage object is the memory of the FPGA chip, and when the target identifier is used to indicate the execution of a data read operation, the target storage object is the random access memory of the FPGA chip.

[0091] In an embodiment of the present application, an execution module is used to interrupt the communication link between the FPGA chip and the central processing unit when the target identifier carried in the page fault processing information is used to indicate the execution of a data write operation; detect whether there is first data in the buffer connected to the FPGA chip; if the first data exists in the buffer, write the first data from the buffer to the memory, wherein the first data is data written to the buffer by the central processing unit after the communication link is interrupted; use the first data to update the page table information of the page table in the memory to obtain updated page table information, and determine the updated page table information as the processing result.

[0092] In an embodiment of the present application, an execution module is used to obtain a page fault address from associated data of a target identifier when a target identifier carried in page fault processing information indicates execution of a data read operation; query whether there is a page fault address in a buffer connected to the FPGA chip to obtain a query result; and execute a data read operation corresponding to the query result.

[0093] In an embodiment of the present application, an execution module is used to, when a query result shows that there is a page fault address, send a first notification message to a central processing unit, so that the central processing unit reads second data corresponding to the page fault address from a buffer according to the first notification message; when a query result shows that there is no page fault address, read update data from a MEM controller connected to the FPGA chip, write the update data into the buffer, and send a second notification message to the central processing unit, so that the central processing unit reads second data corresponding to the page fault address from the update data in the buffer according to the second notification message.

[0094] Figure 5 This is a block diagram of a page fault processing system provided in an embodiment of the present application. The system can be implemented as part or all of an electronic device through software, hardware, or a combination of both. Figure 5 As shown, the system includes: a central processing unit 51 and an FPGA chip 52;

[0095] The central processing unit 51 is used to obtain a virtual address, generate a page table entry address according to the virtual address, read a page table entry from the memory according to the page table entry address, and detect the page table entry. If there is a page fault in the page table entry, a page fault processing request is sent to the FPGA chip;

[0096] The FPGA chip 52 is used to receive a page fault processing request from a central processing unit; parse the page fault processing request to obtain page fault processing information carried by the page fault processing request; perform a data write operation or a data read operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; and feed back the processing result to the central processing unit so that the central processing unit updates the page table entry according to the processing result.

[0097] In the embodiment of the present application, the FPGA chip is connected to the CPLD, the flash memory and multiple MEM controllers, such as Figure 6 As shown, the system uses FPGA as the main processing chip, CPLD is used for power management and board management, supports 4-way large-capacity DDR, and the interface uses CXL protocol. It is compatible with PCIe protocol in physical form, and the board can be directly inserted into the motherboard PCIe slot through gold fingers.

[0098] In the application embodiment, the processing flow of the system is as follows:

[0099] Step 1: The CPU generates a virtual address.

[0100] Step 2: The memory management unit of the CPU generates a page table entry address based on the virtual address generated by the CPU.

[0101] Step 3: Read the memory to obtain the page table entry corresponding to the page table entry address.

[0102] Step 4: The memory management unit determines whether the valid flag bit of the page table entry is 0. If it is 0, it indicates a page fault. The page table entry triggers a page fault processing request, and the FPGA chip executes a page fault exception handler.

[0103] Step 5: The page fault exception handler determines the information related to the page fault or page swap and sends it to the CXL HOST.

[0104] Step 6: CXL HOST implements MEM read and write operations on the FPGA side through CXL.io and CXL.mem. The new page is transferred to the local memory, and the system updates the page table entry in the local memory.

[0105] Step 7: The page fault handler returns to the original process and executes the instruction that caused the page fault again. Because the new page is cached in memory, the memory management unit will hit it, thus generating a physical address, and the process continues to execute.

[0106] The present application also provides an electronic device, such as Figure 7As shown, the electronic device may include: a processor 1501 , a communication interface 1502 , a memory 1503 and a communication bus 1504 , wherein the processor 1501 , the communication interface 1502 , and the memory 1503 communicate with each other via the communication bus 1504 .

[0107] Memory 1503, used for storing computer programs;

[0108] The processor 1501 is used to implement the steps of the above embodiment when executing the computer program stored in the memory 1503.

[0109] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0110] The communication interface is used for communication between the above terminal and other devices.

[0111] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0112] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0113] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which instructions are stored. When the computer-readable storage medium is executed on a computer, the computer executes the page fault processing method described in any one of the above embodiments.

[0114] In another embodiment provided in the present application, a computer program product including instructions is also provided, and when the computer is run on the computer, the computer executes the page fault processing method described in any one of the above embodiments.

[0115] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk SolidState Disk), etc.

[0116] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

[0117] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A page fault processing method, characterized in that: Applied to FPGA chip, the method comprises: Receiving a page fault processing request from a central processing unit, wherein the page fault processing request is triggered when the central processing unit determines that a page fault exists in a page table entry; Parsing the page fault processing request to obtain page fault processing information carried by the page fault processing request; Performing a data write operation or a data read operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; Feedback the processing result to the central processing unit, so that the central processing unit updates the page table entry according to the processing result; The parsing of the page fault processing request to obtain the page fault processing information carried by the page fault processing request includes: calling a computer quick link protocol to parse the page fault processing request to obtain original page fault processing information; extracting a target identifier and associated data of the target identifier from the original page fault processing information, and determining the target identifier and the associated data as the page fault processing information, wherein the target identifier is used to indicate the execution of a data write operation or a data read operation.

2. The method according to claim 1, characterized in that Before performing a data write operation or a data read operation in the target storage object based on the page fault processing information to obtain a processing result, the method further includes: The target storage object is determined based on the target identifier in the page fault processing information, wherein, when the target identifier is used to indicate the execution of a data write operation, the target storage object is the memory of the FPGA chip, and when the target identifier is used to indicate the execution of a data read operation, the target storage object is the random access memory of the FPGA chip.

3. The method according to claim 2, characterized in that The performing a data writing operation or a data reading operation in the target storage object based on the page fault processing information to obtain a processing result includes: When the target identifier carried in the page fault processing information is used to indicate the execution of a data write operation, an interrupt operation is performed on the communication link between the FPGA chip and the central processing unit; Detecting whether there is first data in the buffer connected to the FPGA chip; In the case where the first data exists in the buffer, writing the first data from the buffer to the memory, wherein the first data is the data written to the buffer by the central processor after the communication link is interrupted; The page table information of the page table in the memory is updated by using the first data to obtain updated page table information, and the updated page table information is determined as the processing result.

4. The method according to claim 2, characterized in that: The performing a data writing operation or a data reading operation in the target storage object based on the page fault processing information to obtain a processing result includes: When the target identifier carried in the page fault processing information is used to indicate the execution of a data read operation, obtaining the page fault address from the associated data of the target identifier; Query whether the missing page address exists in the buffer connected to the FPGA chip, and obtain a query result; Execute the data reading operation corresponding to the query result to obtain the processing result.

5. The method according to claim 4, characterized in that The executing the data reading operation corresponding to the query result includes: If the query result indicates that the page fault address exists, generating first notification information, wherein the first notification information is used to notify the central processor to read second data corresponding to the page fault address from the buffer; When the query result is that the page fault address does not exist, update data is read from the MEM controller connected to the FPGA chip, the update data is written to the buffer, the cache information in the random access memory is updated, and a second notification message is sent to the central processing unit, wherein the second notification message is used to notify the central processing unit to read the second data corresponding to the page fault address from the buffer.

6. A disk space processing device, characterized in that: include: A receiving module, configured to receive a page fault processing request from a central processing unit, wherein the page fault processing request is triggered when the central processing unit determines that a page fault exists in a page table entry; A parsing module, used for parsing the page fault processing request to obtain the page fault processing information carried by the page fault processing request; An execution module, configured to execute a data write operation or a data read operation in a target storage object based on the page fault processing information to obtain a processing result, wherein the target storage object is deployed in an FPGA chip; A sending module, used for feeding back the processing result to the central processing unit, so that the central processing unit updates the page table entry according to the processing result; The parsing module is used to call the computer quick link protocol to parse the page fault processing request to obtain original page fault processing information; extract the target identifier and the associated data of the target identifier from the original page fault processing information, and determine the target identifier and the associated data as the page fault processing information, wherein the target identifier is used to indicate the execution of a data write operation or a data read operation.

7. A disk space processing system, characterized in that: include: Central processing unit and FPGA chip; The central processing unit is used to obtain a virtual address, generate a page table entry address according to the virtual address, read a page table entry from a memory according to the page table entry address, and detect the page table entry. If there is a page fault in the page table entry, a page fault processing request is sent to the FPGA chip; The FPGA chip is used to receive a page fault processing request from a central processing unit; parse the page fault processing request to obtain page fault processing information carried by the page fault processing request; Based on the page fault processing information, a data write operation or a data read operation is performed in the target storage object to obtain a processing result, wherein the target storage object is deployed in the FPGA chip; the processing result is fed back to the central processor so that the central processor updates the page table entry according to the processing result; The FPGA chip is used to call the computer quick link protocol to parse the page fault processing request to obtain original page fault processing information; extract the target identifier and the associated data of the target identifier from the original page fault processing information, and determine the target identifier and the associated data as the page fault processing information, wherein the target identifier is used to indicate the execution of a data write operation or a data read operation.

8. A storage medium, characterized in that: The storage medium includes a stored program, wherein the program executes the method steps of any one of claims 1 to 5 when executed.

9. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; wherein: Memory, used to store computer programs; A processor, configured to execute the method steps of any one of claims 1 to 5 by running a program stored in a memory.

Images