Optoelectronic integrated device and method of fabrication

Abstract

This invention discloses an optoelectronic integrated device and its fabrication method, comprising: multiple ordered basic units, each basic unit including a multi-quantum-well MicroLED and a vertical GaN MOSFET; a bonding dielectric layer is provided on the top layer of the sapphire substrate, and the bottom layer of the sapphire substrate is the light-emitting surface of the device; the multi-quantum-well MicroLED is disposed on the top layer of the bonding dielectric layer; the vertical GaN MOSFET is disposed above the multi-quantum-well MicroLED, and the drain region of the vertical GaN MOSFET and the N-region of the multi-quantum-well MicroLED are connected in series through a shared diode N-GaN structure layer; the light-emitting device and the driving electronic device of this invention are fabricated on the same chip, which not only enables mass production using existing GaN process platforms, reducing production costs, but also has significant advantages such as small size, high speed, and high reliability; the GaN MOSFET adopts a novel vertical structure design, which can greatly shorten the channel length of the driving transistor, which is of great significance for improving the performance and integration density of the integrated device.

Description

Technical Field

[0001] This invention relates to an optoelectronic integrated device and its fabrication method, belonging to the field of integrated optoelectronic technology. Background Technology

[0002] The band gap of GaN and its alloys, belonging to the III-V group, covers the spectral range from infrared to visible light, and has achieved great success in fields such as solid-state lighting, displays, high-density storage, and underwater communications. Meanwhile, GaN-based transistor technology has also received significant attention from the industry in recent years, developing rapidly and showing promising application prospects in high-power and high-frequency devices. Currently, research on GaN in optoelectronics and electronics is independent, but in practical applications, optoelectronics and electronics are inseparable and interdependent. For example, GaN light-emitting diodes (LEDs) must be driven by electronic transistor circuits. Existing electronic transistor circuits are fabricated separately on silicon-based platforms and electrically connected to optoelectronic components through off-chip packaging.

[0003] Integrating GaN optoelectronic devices and electronic devices onto the same platform forms what is known as a monolithic optoelectronic integrated circuit. Compared with traditional off-chip packaging and interconnection, it has significant advantages such as small size, light weight, low cost, high speed, fewer parasites, multiple functions, and high reliability. Summary of the Invention

[0004] The purpose of this invention is to provide an optoelectronic integrated device and its fabrication method to solve the problem that existing electronic transistor circuits are based on silicon-based platforms and are large in size.

[0005] An optoelectronic integrated device, comprising:

[0006] Multiple ordered basic units, the basic units including multi-quantum-well Micro LEDs and vertical GaN MOSFETs;

[0007] A sapphire substrate, wherein the top layer of the sapphire substrate is provided with a bonding dielectric layer, and the bottom layer of the sapphire substrate is the light-emitting surface of the device;

[0008] The multi-quantum-well Micro LED is disposed on the top layer of the bonding dielectric layer; the vertical structure GaN MOSFET is disposed above the multi-quantum-well Micro LED, and the drain region of the vertical structure GaN MOSFET and the N region of the multi-quantum-well Micro LED are connected in series through a shared diode N-GaN structure layer.

[0009] Furthermore, the active region of the multi-quantum-well Micro LED includes, from bottom to top, a diode P-GaN structure layer, a diode multi-quantum-well structure layer, and a diode N-GaN structure layer. The basic unit is surrounded by diode positive electrodes and is in direct contact with the diode P-GaN structure layer. The diode positive electrodes are distributed in a grid pattern.

[0010] Furthermore, the vertical GaN MOSFET comprises, from bottom to top, a diode N-GaN structure layer, a transistor P-GaN channel layer, a transistor source region N-GaN structure layer, and a transistor source metal layer;

[0011] The diode N-GaN structure layer, the transistor P-GaN channel layer, and the transistor source region N-GaN structure layer are covered with a transistor gate metal layer, and an isolation gate dielectric layer is provided on the outside of the transistor gate metal layer.

[0012] Furthermore, the sidewall tilt angle of the transistor P-GaN channel layer and the transistor source region N-GaN structure layer is less than 1 degree.

[0013] A method for fabricating the above-mentioned optoelectronic integrated device, the method comprising:

[0014] The first step is to coat a layer of photoresist on the sapphire on the back of the integrated chip epitaxial wafer and then perform photolithography to form a patterned structure on the light-emitting surface.

[0015] The second step is to coat a layer of photoresist on the epitaxial wafer of the integrated chip, and use the photoresist reflow method to form the sidewall tilt angle. After photolithography, the area to be etched on the platform is exposed. Etching stops at the diode N-GaN structure layer to form the sidewall of the transistor gate.

[0016] The third step is to coat another layer of photoresist and perform photolithography to expose the area that needs to be etched. The etching stops when the diode P-GaN structure layer is reached, forming a light-emitting platform region.

[0017] The fourth step is to anneal the etched epitaxial wafer of the integrated chip in nitrogen to remove hydrogen elements from the P-GaN channel layer of the transistor and activate the P-GaN.

[0018] The fifth step is to grow a gate dielectric layer on the epitaxial wafer of the integrated chip and then etch it after photolithography.

[0019] The sixth step involves using a stripping method to form the diode positive electrode, the transistor gate metal layer, and the metal transistor source metal layer, respectively.

[0020] The seventh step involves using an isolation medium as an electrical isolation layer between different interconnect metal layers to grow several interconnect metal layers, thereby connecting the same type of electrodes of different basic units into a unified whole and forming the entire optoelectronic integrated device.

[0021] Furthermore, a gate dielectric layer is grown on the epitaxial wafer of the integrated chip using pressure chemical vapor deposition or atomic layer deposition.

[0022] Furthermore, the annealing conditions are as follows: annealing at 700 degrees Celsius for 30 minutes.

[0023] Furthermore, the method for fabricating the integrated chip epitaxial wafer includes:

[0024] The first step is to select a multi-quantum-well LED epitaxial wafer as the LED wafer. The epitaxial materials of the multi-quantum-well LED epitaxial wafer are, from bottom to top, a first sapphire, a buffer layer, an unintentionally doped GaN layer, an N-GaN layer, a multi-quantum-well, and a P-GaN layer. A second sapphire is set as a transfer substrate in the P-GaN layer.

[0025] The second step is to grow a transparent bonding dielectric layer on top of the second sapphire or P-GaN layer, and to achieve bonding between the LED wafer and the transfer substrate under pressure, temperature and gas environment.

[0026] The third step is to remove the first sapphire layer of the bonded wafer, then remove the buffer layer and the unintentionally doped GaN layer of the bonded wafer to expose the N-GaN layer.

[0027] The fourth step involves sequentially epitaxially growing a P-GaN epitaxial layer and an N-GaN epitaxial layer on top of the N-GaN layer to obtain the integrated chip epitaxial wafer.

[0028] Furthermore, the bonding dielectric layer is located between the LED wafer and the transfer substrate.

[0029] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0030] The light-emitting device of the present invention can be fabricated on the same chip as the driving electronic device. It can not only achieve mass production using the existing GaN process platform and reduce production costs, but also has significant advantages such as small size, high speed and high reliability.

[0031] GaN MOSFETs employ a novel vertical structure design, which can significantly shorten the channel length of the driving transistor, and is of great significance for improving the performance and integration density of integrated devices.

[0032] The drain region of GaN MOSFETs shares the same N-type doped region with the N-region of Micro LEDs, eliminating the need for metal interconnects. This results in higher reliability of electrical interconnects between devices, less parasitic effects, and saves area on the integrated chip. Attached Figure Description

[0033] Figure 1This is a schematic diagram of the epitaxial wafer fabrication process of the optoelectronic integrated device of the present invention;

[0034] Figure 2 This is a top view of the structure of the optoelectronic integrated device of the present invention;

[0035] Figure 3 This is a cross-sectional view of the optoelectronic integrated device of the present invention along the A-A' direction;

[0036] Figure 4 This is the equivalent circuit diagram of the optoelectronic integrated device of the present invention;

[0037] In the figure: 1. First sapphire; 2. Buffer layer; 3. Unintentionally doped GaN layer; 4. N-GaN layer; 5. Multiple quantum wells; 6. P-GaN layer; 7. Second sapphire; 8. Bonding dielectric layer; 9. P-GaN epitaxial layer; 10. N-GaN epitaxial layer; 11. Basic unit; 12. Sapphire substrate; 13. Micro LED; 14. Vertical structure GaN MOSFET; 15. Diode P-GaN structure layer; 16. Diode multiple quantum well structure layer; 17. Diode N-GaN structure layer; 18. Diode anode; 19. Transistor P-GaN channel layer; 20. Transistor source region N-GaN structure layer; 21. Transistor source metal layer; 22. Gate dielectric layer; 23. Transistor gate metal layer. Detailed Implementation

[0038] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.

[0039] See Figure 1-4 This invention proposes an optoelectronic integrated device, comprising:

[0040] Multiple ordered basic units 11, each basic unit 11 including a multi-quantum-well Micro LED 13 and a vertical GaN MOSFET 14;

[0041] A sapphire substrate 12 has a bonding dielectric layer 8 on its top layer and a light-emitting surface of the device on its bottom layer. The bottom surface of the sapphire substrate 12 adopts a patterned structure to reduce the reflection of incident light, thereby improving the light emission efficiency.

[0042] The multi-quantum-well Micro LED 13 is disposed on the top layer of the bonding dielectric layer 8; the vertical structure GaN MOSFET 14 is disposed above the multi-quantum-well Micro LED 13, and the drain region of the vertical structure GaN MOSFET 14 and the N region of the multi-quantum-well Micro LED 13 are connected in series through a shared diode N-GaN structure layer 17.

[0043] In this technical solution, the multi-quantum-well Micro LED The active region of 13, from bottom to top, includes a diode P-GaN structure layer 15, a diode multi-quantum-well structure layer 16, and a diode N-GaN structure layer 17. Diode anodes 18 are arranged around the basic unit 11 and are in direct contact with the diode P-GaN structure layer 15. The diode anodes 18 are arranged in a grid pattern, with the diode anodes 18 located around the basic unit 11 and in direct contact with the lower diode P-GaN structure layer 15. The contact type is ohmic contact. The grid pattern of diode anodes 18 in the entire optoelectronic integrated device is beneficial for improving the current distribution during LED operation. The transistor gate metal layers 23 of different basic units 11 are electrically connected through interconnect metal layers, forming a unified whole. The transistor source metal layers 21 of different basic units 11 are electrically connected through another interconnect metal layer, forming a unified whole. There is no electrical connection between the transistor gate metal layer 23, the transistor source metal layer 21, and the diode anode 18; different interconnect metal layers are electrically isolated through an isolation medium.

[0044] like Figure 3 As shown, the vertical structure GaN MOSFET 14 includes, from bottom to top, a diode N-GaN structure layer 17, a transistor P-GaN channel layer 19, a transistor source region N-GaN structure layer 20, and a transistor source metal layer 21.

[0045] The sidewalls of the diode N-GaN structure layer 17, the transistor P-GaN channel layer 19, and the transistor source region N-GaN structure layer 20 are covered with a transistor gate metal layer 23, and a gate dielectric layer 22 is provided on the outside of the transistor gate metal layer 23 for isolation.

[0046] Furthermore, the sidewall tilt angles of the transistor P-GaN channel layer 19 and the transistor source region N-GaN structure layer 20 are less than 90 degrees, which facilitates the step coverage of the gate dielectric layer 22 and the transistor source metal layer 23.

[0047] A method for fabricating the above-mentioned optoelectronic integrated device, the method comprising:

[0048] The first step is to coat a layer of photoresist on the second sapphire 7 on the back side of the integrated chip epitaxial wafer and perform photolithography to expose the area to be etched. Inductively coupled plasma (ICP) dry etching is then used to form a patterned structure on the light-emitting surface.

[0049] The second step is to coat a layer of photoresist on the epitaxial wafer of the integrated chip, and use photoresist reflow technology to form a certain sidewall tilt angle. After photolithography, the area to be etched on the platform is exposed. Then, ICP dry etching is performed until the diode N-GaN structure layer 17 is reached, forming the sidewall of the transistor gate.

[0050] The third step is to coat a layer of photoresist and perform photolithography to expose the area to be etched. Then, perform ICP dry etching until the diode P-GaN structure layer 15 is reached, forming the light-emitting platform area.

[0051] The fourth step is to anneal the P-GaN channel layer 19 in a nitrogen atmosphere at 700 degrees Celsius for 30 minutes to remove hydrogen elements and activate the P-GaN.

[0052] The fifth step involves growing a high-quality gate dielectric layer 22 using low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD), and etching it after photolithography.

[0053] The sixth step involves forming the diode anode 18, the transistor gate metal layer 23, and the metal transistor source metal layer 21 using a stripping method.

[0054] The seventh step involves using an isolation medium as an electrical isolation layer between different interconnect metal layers to grow several interconnect metal layers that connect the same type of electrodes of different basic units 11 into a unified whole, forming the positive electrode, negative electrode and gate of the entire optoelectronic integrated device.

[0055] The working principle of the multi-quantum-well GaN MOSFET 13 is as follows: When no forward bias voltage is applied to the transistor gate metal layer 23 of the multi-quantum-well GaN MOSFET 13, the transistor P-GaN channel layer 19 covered by the transistor gate metal layer 23 is in the off state; when a certain forward bias voltage is applied to the transistor gate metal layer 23 of the multi-quantum-well GaN MOSFET 13, the carriers in the transistor P-GaN channel layer 19 covered by the transistor gate metal layer 23 are inverted, the channel becomes the conducting state, and the multi-quantum-well GaN MOSFET 13 is turned on.

[0056] The working principle of the multi-quantum-well Micro LED 13 is as follows: When a certain forward bias voltage is applied across the LED, that is, the voltage of the diode P-GaN structure layer 15 is higher than that of the diode N-GaN structure layer 17, holes are injected from the diode P-GaN structure layer 15 into the diode multi-quantum-well structure layer 16, and electrons are injected from the diode N-GaN structure layer 17 into the diode multi-quantum-well structure layer 16. Utilizing the confinement effect of the multi-quantum-well on the charge carriers, most of the electrons and holes are confined in the diode multi-quantum-well structure layer 16 and undergo radiative recombination, thereby achieving light emission.

[0057] The diode multi-quantum-well structure layer can be selected from InGaN / GaN or AlGaN / GaN multi-quantum-well structures. The emission wavelength can be tuned by changing the ratio of In or Al.

[0058] The working principle of the optoelectronic integrated device is as follows: A certain positive voltage is applied to the positive electrode 18 of the diode, and the source metal layer 21 of the transistor is grounded or a certain negative voltage is applied. By changing the bias voltage on the gate metal layer 23 of the transistor, the source and drain current of the vertical structure multi-quantum well GaN MOSFET 13 can be controlled, thereby controlling the luminous intensity of the multi-quantum well Micro LED 13.

[0059] By loading an input signal onto the gate metal layer 23 of the transistor, the input voltage signal can be converted into a modulated output optical signal, which can be used for visible light communication or pulse width modulation of light intensity.

[0060] In this embodiment, the gate dielectric layer 22 is grown on the epitaxial wafer of the integrated chip using pressure chemical vapor deposition or atomic layer deposition.

[0061] In this embodiment, the annealing conditions are: annealing at 700 degrees Celsius for 30 minutes.

[0062] like Figure 1 As shown, the method for fabricating the integrated chip epitaxial wafer includes:

[0063] The epitaxial wafer of the integrated chip of optoelectronic integrated device is fabricated through processes such as bonding, laser lift-off, epitaxial layer thinning and epitaxial growth; the first step is to select a common sapphire substrate GaN-based multi-quantum well LED epitaxial wafer as the LED wafer, and a second sapphire 7 as the transfer substrate. The epitaxial materials of the sapphire substrate GaN-based multi-quantum well LED epitaxial wafer from bottom to top are: first sapphire 1, buffer layer 2, unintentionally doped GaN layer 3, N-GaN layer 4, multi-quantum well 5 and P-GaN layer 6;

[0064] The second step is to grow a transparent bonding dielectric layer 8 on top of the second sapphire 7 or P-GaN layer 6, and to achieve bonding between the LED wafer and the transfer substrate under appropriate pressure, temperature and gas environment. The bonding dielectric layer 8 is located between the LED wafer and the transfer substrate.

[0065] The third step involves using laser lift-off technology to remove the first sapphire 1 of the bonded sheet, and then using thinning techniques such as chemical mechanical polishing or reactive ion etching to remove the buffer layer 2 and the unintentionally doped GaN layer 3 of the bonded sheet, exposing the N-GaN layer 4.

[0066] The fourth step involves sequentially epitaxially extending a P-GaN epitaxial layer 9 and an N-GaN epitaxial layer 10 above the N-GaN layer 4, which serve as the P-GaN channel layer 19 and the N-GaN structure layer 20 of the transistor source region, respectively.

[0067] The bonding dielectric layer 8 of different basic units 11 and the diode P-GaN structure layer 15 are a unified whole. The epitaxial layer above the diode P-GaN structure layer 15 is etched with isolation trenches to form a platform structure and achieve the separation of physical structures.

[0068] The criteria for distinguishing whether something belongs to this structure are as follows:

[0069] The present invention discloses an optoelectronic integrated device based on a multi-quantum-well Micro LED and a vertical GaN MOSFET, comprising multiple ordered basic units 11, each basic unit 11 including a Micro LED 13 and a vertical GaN MOSFET 14; the sapphire substrate 12, bonding dielectric layer 8, and P-GaN structure layer 15 of different basic units 11 are integrated; the diode P-GaN structure layer 15, the diode multi-quantum-well structure layer 16, and the diode N-GaN structure layer 17 above the bonding dielectric layer 8 constitute the multi-quantum-well Micro LED. The active layer of 13 has a diode anode 18 located around the light-emitting platform, directly contacting the diode P-GaN structure layer 15 below. Above the diode N-GaN structure layer 17 are, in sequence, a transistor P-GaN channel layer 19, a transistor source region N-GaN structure layer 20, and a transistor source metal layer 21. The transistor gate metal layer 23 covers the sidewalls of the diode N-GaN structure layer 17, the transistor P-GaN channel layer 19, and the transistor source region N-GaN structure layer 20, and is isolated from the diode N-GaN structure layer 17, the transistor P-GaN channel layer 19, and the transistor source region N-GaN structure layer 20 by a gate dielectric layer 22. The gate sidewall tilt angle is less than 90 degrees.

[0070] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An optoelectronic integrated device, characterized in that, include: Multiple ordered basic units, the basic units including multi-quantum-well MicroLEDs and vertical GaN MOSFETs; A sapphire substrate, wherein the top layer of the sapphire substrate is provided with a bonding dielectric layer, and the bottom layer of the sapphire substrate is the light-emitting surface of the device; The multi-quantum-well Micro LED is disposed on the top layer of the bonding dielectric layer; the vertical structure GaN MOSFET is disposed above the multi-quantum-well Micro LED, and the drain region of the vertical structure GaN MOSFET and the N region of the multi-quantum-well Micro LED are connected in series through a shared diode N-GaN structure layer. The vertical GaN MOSFET comprises, from bottom to top, a diode N-GaN structure layer, a transistor P-GaN channel layer, a transistor source region N-GaN structure layer, and a transistor source metal layer; The diode N-GaN structure layer, the transistor P-GaN channel layer, and the transistor source region N-GaN structure layer are covered with a transistor gate metal layer, and an isolation gate dielectric layer is provided on the outside of the transistor gate metal layer.

2. The optoelectronic integrated device according to claim 1, characterized in that, The active region of the multi-quantum-well Micro LED includes, from bottom to top, a diode P-GaN structure layer, a diode multi-quantum-well structure layer, and a diode N-GaN structure layer. The basic unit is surrounded by diode positive electrodes, which are in direct contact with the diode P-GaN structure layer. The diode positive electrodes are distributed in a grid pattern.

3. The optoelectronic integrated device according to claim 1, characterized in that, The sidewall tilt angles of the transistor P-GaN channel layer and the transistor source region N-GaN structure layer are less than 90 degrees.

4. A method for fabricating an optoelectronic integrated device according to any one of claims 1-3, characterized in that, The method includes: The first step is to coat a layer of photoresist on the sapphire on the back of the integrated chip epitaxial wafer and then perform photolithography to form a patterned structure on the light-emitting surface. The second step is to coat a layer of photoresist on the epitaxial wafer of the integrated chip, and use the photoresist reflow method to form the sidewall tilt angle. After photolithography, the area to be etched on the platform is exposed. Etching stops at the diode N-GaN structure layer to form the sidewall of the transistor gate. The third step is to coat another layer of photoresist and perform photolithography to expose the area that needs to be etched. The etching stops when the diode P-GaN structure layer is reached, forming a light-emitting platform region. The fourth step is to anneal the etched epitaxial wafer of the integrated chip in nitrogen to remove hydrogen elements from the P-GaN channel layer of the transistor and activate the P-GaN. The fifth step is to grow a gate dielectric layer on the epitaxial wafer of the integrated chip and then etch it after photolithography. The sixth step involves using a stripping method to form the diode positive electrode, the transistor gate metal layer, and the metal transistor source metal layer, respectively. The seventh step involves using an isolation medium as an electrical isolation layer between different interconnect metal layers to grow several interconnect metal layers, thereby connecting the same type of electrodes of different basic units into a unified whole to form the entire optoelectronic integrated device. The method for fabricating the epitaxial wafer of the integrated chip includes: The first step is to select a multi-quantum-well LED epitaxial wafer as the LED wafer. The epitaxial materials of the multi-quantum-well LED epitaxial wafer are, from bottom to top, a first sapphire, a buffer layer, an unintentionally doped GaN layer, an N-GaN layer, a multi-quantum-well, and a P-GaN layer. A second sapphire is set as a transfer substrate in the P-GaN layer. The second step is to grow a transparent bonding dielectric layer on top of the second sapphire or P-GaN layer, and to achieve bonding between the LED wafer and the transfer substrate under pressure, temperature and gas environment. The third step is to remove the first sapphire layer of the bonded wafer, then remove the buffer layer and the unintentionally doped GaN layer of the bonded wafer to expose the N-GaN layer. The fourth step involves sequentially epitaxially growing a P-GaN epitaxial layer and an N-GaN epitaxial layer on top of the N-GaN layer to obtain the integrated chip epitaxial wafer.

5. The method for fabricating an optoelectronic integrated device according to claim 4, characterized in that, The integrated chip epitaxial wafer grows a gate dielectric layer using pressure chemical vapor deposition or atomic layer deposition.

6. The method for fabricating an optoelectronic integrated device according to claim 4, characterized in that, The annealing conditions are as follows: annealing at 700 degrees Celsius for 30 minutes.

7. The method for fabricating an optoelectronic integrated device according to claim 4, characterized in that, The bonding dielectric layer is located between the LED wafer and the transfer substrate.

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