A memory, a preparation method thereof, and a storage system

Abstract

The application discloses a memory, a preparation method thereof and a storage system. A gate line gap is formed through a stop layer and a step structure, an isolation structure is formed at the junction of the stop layer and the gate line gap, an interlayer sacrificial layer is replaced by an interlayer gate layer through the gate line gap, and a contact hole is formed through the stop layer. The bottom of the contact hole is located on the interlayer gate layer at each step of the step structure. Since the isolation structure is arranged between the gate line gap and the stop layer, the stop layer is not removed in the process of replacing the interlayer sacrificial layer, and the stop layer can be used as an etching stop layer in the subsequent etching process of forming the contact hole, so that the process difficulty and the process cost are reduced.

Description

Technical Field

[0001] This invention relates generally to the field of electronic devices, and more specifically to a memory, a method for its fabrication, and a storage system. Background Technology

[0002] In 3D NAND, a stepped structure and a dielectric layer covering the stepped structure are generally formed first. Then, the dielectric layer is etched on each step to form contact holes, and then conductive material is filled into the contact holes to form word line contacts.

[0003] As the number of layers in 3D NAND increases, the process of etching contact holes becomes increasingly difficult. For example, the requirements for the etching selectivity of gate layers (e.g., tungsten) and dielectric layers (e.g., silicon oxide) become increasingly stringent in order to ensure that the etching of contact holes stops within each gate layer.

[0004] How to reduce the difficulty of etching contact holes is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a memory, its fabrication method, and a memory system, which aims to reduce the difficulty of contact hole etching.

[0006] In a first aspect, embodiments of the present invention provide a method for fabricating a memory, comprising:

[0007] Provide substrate;

[0008] A stacked layer is formed on the substrate, the stacked layer comprising alternating layers of interlayer insulating layers and interlayer sacrificial layers, the stacked layer including a stepped region and having a stepped structure in the stepped region;

[0009] A stop layer is formed covering the stepped structure;

[0010] Forming grid line gaps that penetrate the stop layer and the stepped structure;

[0011] An isolation structure is formed at the junction of the stop layer and the gate wire gap;

[0012] The interlayer sacrificial layer is replaced with an interlayer gate layer through the gate line gap;

[0013] A contact hole is formed that penetrates the stop layer, and the bottom of the contact hole is located on the interlayer gate layer at each step of the stepped structure.

[0014] Furthermore, the step of forming an isolation structure at the junction of the stop layer and the gate wire gap includes:

[0015] The stop layer is etched through the gate line gaps to form a first isolation groove at the junction of the stop layer and the gate line gaps;

[0016] The isolation structure is formed in the first isolation groove.

[0017] Furthermore, the stop layer and the interlayer sacrificial layer comprise the same material, and the method for fabricating the memory further includes:

[0018] The stop layer is processed so that, under the same conditions, the etching rate of the stop layer is greater than the etching rate of the interlayer sacrificial layer.

[0019] Furthermore, the step of etching the stop layer through the gate line gap includes:

[0020] The stop layer and the interlayer sacrificial layer are etched through the gate line gaps to form the first isolation groove at the junction of the stop layer and the gate line gaps, and the second isolation groove at the junction of the interlayer sacrificial layer and the gate line gaps.

[0021] Wherein, the width of the first isolation groove in the first direction is greater than the width of the second isolation groove in the first direction, and the first direction is perpendicular to the extension direction of the grid line gap.

[0022] Furthermore, the step of forming the isolation structure in the first isolation groove includes:

[0023] Deposit insulating material in the first isolation trench, the second isolation trench, and the grid line gaps;

[0024] The isolation material is etched back to remove the isolation material located in the second isolation groove and the grid line gap, while retaining a portion of the isolation material located in the first isolation groove to form the isolation structure;

[0025] The isolation structure has a groove between it and the grid line gap.

[0026] Furthermore, prior to the step of depositing isolation material in the first isolation trench, the second isolation trench, and the gate wire gap, the method for fabricating the memory further includes:

[0027] A barrier layer is formed in the first isolation groove and the second isolation groove, as well as at the interface between the interlayer insulation layer and the gate wire gap;

[0028] After the step of etching back the isolation material, the method for fabricating the memory further includes etching the barrier layer to remove the barrier layer located in the second isolation trench.

[0029] Furthermore, the step of replacing the interlayer sacrificial layer with an interlayer gate layer through the gate line gap includes:

[0030] The cavity is formed by removing the interlayer sacrificial layer;

[0031] A gate material layer is filled in the cavity and the groove to form the interlayer gate layer at the location of the interlayer sacrificial layer.

[0032] Furthermore, the reproducibility of the stop layer is greater than that of the interlayer sacrificial layer, and the step of forming an isolation structure at the junction of the stop layer and the gate wire gap includes:

[0033] The stop layer and the interlayer sacrificial layer are oxidized through the gate line gap to form a first oxide at the junction of the stop layer and the gate line gap, and a second oxide at the junction of the interlayer sacrificial layer and the gate line gap. The width of the first oxide in a first direction is greater than the width of the second oxide in the first direction, and the first direction is perpendicular to the extension direction of the gate line gap.

[0034] The first oxide and the second oxide are etched to remove the second oxide, while retaining a portion of the first oxide to form the isolation structure.

[0035] Furthermore, the reducibility of the stop layer is equal to the reducibility of the interlayer sacrificial layer, and prior to the step of forming an isolation structure at the junction of the stop layer and the gate line gap, the method for fabricating the memory further includes:

[0036] The stop layer is subjected to an ion implantation process to make the reducibility of the stop layer greater than that of the interlayer sacrificial layer.

[0037] Furthermore, the material of the stop layer includes silicon nitride, and the implanted ions in the ion implantation process include silicon.

[0038] Furthermore, the step of forming a contact hole penetrating the stop layer includes:

[0039] A dielectric layer covering the stop layer is formed on the stepped structure;

[0040] The dielectric layer and part of the stop layer on each step are etched to form contact holes, the bottom of which is located in the stop layer;

[0041] The contact hole is etched further so that the bottom of the contact hole is located on the interlayer gate layer at each step.

[0042] Furthermore, prior to the step of forming the stop layer covering the stepped structure, the method for fabricating the memory further includes:

[0043] An isolation layer is formed between the stepped structure and the stop layer.

[0044] In a second aspect, embodiments of the present invention provide a memory, the memory comprising:

[0045] Semiconductor layer;

[0046] A stacked structure is located on the semiconductor layer and includes a step region, wherein the stacked structure is a stepped structure in the step region;

[0047] A stop layer that covers at least a portion of the stepped structure;

[0048] A grid line slot structure extends through the stepped structure, the grid line slot structure passes through the stop layer and has a gap between it and the grid line slot structure;

[0049] An isolation structure that covers part of the stepped structure and is located in the interval area;

[0050] The letter contact points are located on each step of the stepped structure and penetrate the stop layer.

[0051] Furthermore, the stacked structure includes alternately stacked interlayer insulating layers and interlayer gate layers; the memory also includes:

[0052] A dielectric layer is located on the stepped structure and covers the stop layer;

[0053] The word line contact penetrates the dielectric layer and the stop layer, and the bottom of the word line contact is connected to the interlayer gate layer at each step.

[0054] Furthermore, the memory also includes:

[0055] A barrier layer, the barrier layer comprising a first barrier layer, a second barrier layer and a third barrier layer;

[0056] The first barrier layer is located between the isolation structure and the stop layer, the second barrier layer is located between the isolation structure and the dielectric layer, and the third barrier layer is located between the isolation structure and the interlayer insulation layer.

[0057] Furthermore, the memory also includes:

[0058] A gate material layer is located between the isolation structure and the gate line gap structure, and partially covers the stepped structure.

[0059] Furthermore, the gate material layer and the interlayer gate layer comprise the same material.

[0060] Furthermore, the memory also includes:

[0061] An isolation layer is located between the stepped structure and the stop layer.

[0062] Furthermore, both the isolation structure and the interlayer insulation layer comprise oxides.

[0063] Thirdly, embodiments of the present invention provide a storage system, including:

[0064] The memory as described in any one of items 13-19 above;

[0065] A controller, electrically connected to the memory, is used to control the memory to store data.

[0066] This invention provides a memory, its fabrication method, and a memory system. First, a gate line gap is formed penetrating a stop layer and a stepped structure. Then, an isolation structure is formed at the junction of the stop layer and the gate line gap. Next, an interlayer sacrificial layer is replaced with an interlayer gate layer through the gate line gap. Finally, a contact hole is formed penetrating the stop layer, with the bottom of the contact hole located on the interlayer gate layer at each step of the stepped structure. Because an isolation structure separates the gate line gap from the stop layer, the stop layer is not removed during the replacement of the interlayer sacrificial layer. Therefore, the stop layer can be used as an etching stop layer in the subsequent etching process for forming the contact hole, reducing process difficulty and cost. Attached Figure Description

[0067] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0068] Figure 1 This is a schematic flowchart of the method for fabricating a memory according to an embodiment of the present invention;

[0069] Figures 2a-2p This is a schematic diagram of the structure of the memory provided in the embodiment of the present invention during the manufacturing process;

[0070] Figure 3 This is a schematic flowchart of a method for fabricating a memory according to another embodiment of the present invention;

[0071] Figures 4a-4c This is a schematic diagram of the structure of a memory during its fabrication process according to another embodiment of the present invention;

[0072] Figure 5 This is a schematic diagram of the structure of the memory provided in an embodiment of the present invention;

[0073] Figure 6 This is a schematic diagram of the structure of a memory provided in another embodiment of the present invention;

[0074] Figure 7 This is a schematic diagram of the storage system provided in an embodiment of the present invention. Detailed Implementation

[0075] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0076] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0077] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0078] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0079] This paper uses a Cartesian coordinate system (X, Y, and Z) to represent the cross-section of the memory in various directions, where the XY plane is parallel to the substrate and the Z direction is perpendicular to the substrate.

[0080] It should be noted that the illustrations provided in the embodiments of the present invention are only schematic representations of the basic concept of the present invention. Although the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the layout of the components may also be more complex.

[0081] The memory in this embodiment of the invention can be applied to wafers or three-dimensional memory. Three-dimensional memory can be applied to communication products, consumer electronics, automotive products, aerospace products, artificial intelligence products, or big data, etc. Consumer electronics include, but are not limited to, mobile phones, computers, tablets, cameras, smart glasses, or gaming products, etc.

[0082] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the method for fabricating a memory according to an embodiment of the present invention. Please also refer to... Figures 2a-2p , Figures 2a-2p This is a schematic diagram of the structure of the memory provided in the embodiment of the present invention during the fabrication process. The fabrication method of the memory includes the following steps S1-S7.

[0083] Please see Figure 1 Steps S1-S2 and Figure 2a .

[0084] Step S1: Provide substrate 10.

[0085] The substrate 10 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). The semiconductor substrate can also be a substrate containing other elemental semiconductors or compound semiconductors, and can also be a multilayer structure, such as Si / SiGe.

[0086] Step S2: A stacked layer 20 is formed on the substrate 10. The stacked layer 20 includes alternating layers of interlayer insulating layer 21 and interlayer sacrificial layer 22. The stacked layer 20 includes a step region and has a step structure in the step region.

[0087] Specifically, an interlayer insulating layer 21 and an interlayer sacrificial layer 22 are alternately deposited on the substrate 10. An exemplary material for the interlayer insulating layer 21 is silicon oxide, and an exemplary material for the interlayer sacrificial layer 22 is silicon nitride. The interlayer insulating layer 21 and the interlayer sacrificial layer 22 have different etching selectivity. The formed stacked layer 20 may include a core region 20A and a step region 20B. The step region 20B may be located around the core region 20A or in the middle of the core region 20A. Then, the stacked layer 20 located in the step region 20B is further etched to form... Figure 2a The step structure is shown. In one embodiment, the step structure may expose the interlayer sacrificial layer 22 at each step, that is, the interlayer sacrificial layer 22 covers the interlayer insulating layer 21 at each step.

[0088] In another embodiment, the interlayer insulating layer 21 may cover the interlayer sacrificial layer 22 at each step of the stepped structure. The method of fabricating the memory may further include forming a spacer layer between the substrate 10 and the stacked layers 20.

[0089] Please see Figure 2b Following step S2, the fabrication of the memory may further include forming an isolation layer 30 (e.g., silicon oxide) covering the stepped structure. Specifically, the isolation layer 30 can be deposited on the stacked layer 20 first, and then the isolation layer 30 in the core region 20A can be removed to form an isolation layer 30 covering the stepped structure in the stepped region 20B. The main function of the isolation layer 30 is to separate the stop layer formed in step S3 below from the interlayer sacrificial layer 22 in the stepped structure, so as to prevent the stop layer from being affected when the interlayer sacrificial layer 22 is replaced.

[0090] Please see Figure 1 Step S3 and Figure 2c .

[0091] Step S3: Form a stop layer 40 covering the stepped structure.

[0092] In one embodiment, a stop layer 40 may be deposited on the isolation layer 30, and the material of the stop layer 40 may include silicon nitride. Specifically, the stop layer 40 may first be deposited on the stacked layer 20 and the isolation layer 30 of the core region 20A, and then the stop layer 40 located in the core region 20A may be removed to form a stop layer 40 covering the stepped structure and located on the isolation layer 30. The deposition methods include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0093] In one embodiment, the thickness of the stop layer 40 is greater than the thickness of the isolation layer 30. For example, the thickness of the isolation layer 30 can be [missing information - likely a value]. The thickness of the stop layer 40 can be 80-200 nm. The thickness of the stop layer 40 can be adjusted as needed, for example, according to the requirements of the subsequent contact hole etching process.

[0094] Please see Figure 2d After forming the stop layer 40, the method for fabricating the memory may further include forming a dielectric layer 50 covering the stop layer 40. The material of the dielectric layer 50 may include an insulating material such as silicon oxide.

[0095] Please see Figure 1 Step S4 and Figure 2e .

[0096] Step S4: Form a grid line gap 60 that penetrates the stop layer 40 and the stepped structure.

[0097] After the dielectric layer 50 is formed, an etching process can be used to form gate line gaps 60, which penetrate the dielectric layer 50, the stop layer 40, the isolation layer 30 and the step structure.

[0098] Please see Figure 1 Step S5 and Figure 2f .

[0099] Step S5: Etch the stop layer 40 through the gate line gap 60 to form a first isolation groove 401 at the junction of the stop layer 40 and the gate line gap 60.

[0100] In one embodiment, the etching rates of the stop layer 40 and the interlayer sacrificial layer 22 are equal, or their etching selectivity ratio is equal to 1. For example, the stop layer 40 and the interlayer sacrificial layer 22 comprise the same material (e.g., both comprise silicon nitride). During the etching process of the stop layer 40, the interlayer sacrificial layer 22 is etched simultaneously. After the stop layer 40 is formed (step S3), it can be treated to make its etching rate greater than that of the interlayer sacrificial layer 22 under the same conditions. Specifically, nitrogen or argon gas can be used to bombard the stop layer 40, thereby disrupting its structure and breaking its bond energy. Therefore, the treated stop layer 40 is easier to etch (i.e., has a higher etching rate) than the interlayer sacrificial layer 22.

[0101] In some embodiments, other suitable processes may be employed to increase the etching rate of the stop layer 40 or to make the etching selectivity ratio of the stop layer 40 to the interlayer sacrificial layer 22 greater than 1. It is understood that other suitable processing techniques that make the etching rate of the stop layer 40 greater than the etching rate of the interlayer sacrificial layer 22 are also within the scope of protection of these embodiments.

[0102] After modifying the stop layer 40, the portion of the stop layer 40 and the interlayer sacrificial layer 22 near the gate line slot 60 are simultaneously etched to form the first isolation trench 401 at the junction of the stop layer 40 and the gate line slot 60, and the second isolation trench 221 at the junction of the interlayer sacrificial layer 22 and the gate line slot 60. Since the etching rate of the stop layer 40 is greater than the etching rate of the interlayer sacrificial layer 22, the width W1 of the first isolation trench 401 in the first direction (Y) is greater than the width W2 of the second isolation trench 221 in the first direction (Y), which is perpendicular to the extension direction (Z) of the gate line slot 60.

[0103] Please see Figure 1Step S6 and Figure 2g-Figure 2j .

[0104] Step S6: Form an isolation structure 42 in the first isolation groove 401.

[0105] Specifically, in one embodiment, the insulating material 41 can be made of the same material as the interlayer insulating layer 21, for example, both being silicon oxide. Figure 2g As shown, a barrier layer 402 is first formed in the first isolation trench 401 and the second isolation trench 221, and at the interface between the interlayer insulating layer 21 and the gate wire gap 60. The material of the barrier layer 402 may include aluminum oxide.

[0106] like Figure 2h As shown, isolation material 41 is deposited in the first isolation trench 401, the second isolation trench 221, and the gate line slot 60. Since the isolation material 41 is uniformly deposited on all surfaces, and the width of the gate line slot 60 in the Y direction is small, the thickness of the first isolation trench 401 in the Z direction is large, and the thickness of the second isolation trench 221 in the Z direction is small, the isolation material 41 in the gate line slot 60 may be sealed prematurely before the first isolation trench 401 is completely filled. Therefore, during the deposition of the isolation material 41, an alternating etching process is required to open the seal in the gate line slot 60, and then the deposition of the isolation material 41 continues until the first isolation trench 401, the second isolation trench 221, and the gate line slot 60 are completely filled. Then, an etching process (e.g., dry etching) can be used to carve a groove (e.g., a groove in the isolation material 41 in the gate line slot 60) into the isolation material 41. Figure 2h (as shown), so as to facilitate the subsequent etching of the isolation material 41.

[0107] like Figure 2i As shown, the isolation material 41 is then etched back to remove the isolation material 41 located in the second isolation trench 221 and the gate line gap 60, while retaining a portion of the isolation material 41 located in the first isolation trench 401. The isolation material 41 retained in the first isolation trench 401 becomes the isolation structure 42. Specifically, the isolation material 41 is further etched back using an etching process (e.g., wet etching), and the etching solution can enter... Figure 2hThe isolation material 41 is etched in a groove. During the etchback process of the isolation material 41, the barrier layer 402 can be used as an etching stop layer to avoid etching the interlayer insulating layer 21 and affecting the structure. This also improves process reliability and reduces the difficulty of the etchback process. Since there is more isolation material 41 in the first isolation groove 401 than in the second isolation groove 221 or the gate line gap 60, the etchback time is controlled until the isolation material 41 in the second isolation groove 221 and the gate line gap 60 is completely removed. The remaining isolation material 41 in the first isolation groove 401 can then form the isolation structure 42.

[0108] In this embodiment, the main purpose of the etch-back process is to remove the isolation material 41 located in the second isolation trench 221, but at the same time, it will partially etch the isolation material 41 in the first isolation trench 401. Therefore, there is a groove 403 between the isolation structure 42 and the gate line gap 60. That is, the part of the isolation structure 42 that does not fill the first isolation trench 401 (is etched back) forms the groove 403, which is located in the first isolation trench 401 and communicates with the gate line gap 60.

[0109] After the isolation material 41 is etched back, as Figure 2j As shown, the fabrication method of this memory may further include: etching the barrier layer 402 to remove the barrier layer 402 located in the second isolation trench 221. Removing the barrier layer 402 in the second isolation trench 221 exposes the interlayer sacrificial layer 22, allowing for subsequent replacement of the interlayer sacrificial layer 22. During the etching process of the barrier layer 402, the barrier layer 402 in the groove 403, the barrier layer 402 at the interface between the interlayer insulating layer 21 and the gate line gap 60, and the barrier layer 402 at the bottom of the gate line gap 60 are all removed. Only the barrier layer 402 between the isolation structure 42 and the first isolation trench 401 remains.

[0110] Please see Figure 1 Step S7 and Figure 2k-Figure 2m .

[0111] Step S7: Replace the interlayer sacrificial layer 22 with the interlayer gate layer 22a through the gate line gap 60.

[0112] Specifically, the interlayer sacrificial layer 22 and the interlayer insulating layer 21 have different etching selectivity, such as Figure 2k As shown, the interlayer sacrificial layer 22 can be removed by etching to form a cavity. Since an isolation structure 42 is formed between the gate gap 60 and the stop layer 40, the stop layer 40 is not etched when the interlayer sacrificial layer 22 is removed, and thus the stop layer 40 is retained for subsequent formation of contact holes.

[0113] like Figure 2land Figure 2m As shown, a gate material layer is then deposited in the cavity as an interlayer gate layer 22a. The gate material layer can be tungsten or a combination of tungsten and other materials. After the interlayer sacrificial layer 22 is replaced by the interlayer gate layer 22a, the interlayer insulating layer 21 and the interlayer gate layer 22a form a stacked structure 20a. Since there is a groove 403 between the isolation structure 42 and the gate line gap 60, a gate material layer 43 is simultaneously formed in the groove 403 during the deposition of the gate material layer.

[0114] Please see Figures 2n-2p After forming the interlayer gate layer 22a, the method for fabricating this memory further includes the following steps.

[0115] 1) such as Figure 2n As shown, the dielectric layer 50 and part of the stop layer 40 on each step are etched to form contact holes 70, the bottom of which is located in the stop layer 40. 2) As Figure 2o As shown, the contact hole 70 is further etched so that the bottom of the contact hole 70 is located on or in the interlayer gate layer 22a at each step. 3) As shown Figure 2p As shown, a conductive material (e.g., tungsten) is finally filled into the contact hole 70 to form a word line contact 71, which is connected to the interlayer gate layer 22a.

[0116] like Figure 2n As shown, due to the very large etching selectivity of the dielectric layer 50 and the stop layer 40, the first etching can ensure that all contact holes 70 are stopped in the stop layer 40. The depths of the contact holes 70 formed by the first etching vary, with the contact holes 70 on the bottommost step having the greatest depth. For example... Figure 2o As shown, all contact holes 70 are then etched a second time for the same duration, so that the contact holes 70 are all increased to the same depth. Thus, the bottom of each contact hole 70 can be located on the interlayer gate layer 22a, thereby reducing the etching difficulty of the contact holes 70 and increasing the process window of the contact holes 70.

[0117] In some embodiments, the contact hole 70 can also be formed in a single etching process, that is, the bottom of the contact hole 70 is etched to contact the interlayer gate layer 22a in a single etching process.

[0118] The memory fabrication method provided in this embodiment of the invention first processes the stop layer 40 to achieve an etching rate greater than that of the interlayer sacrificial layer 22. Then, the stop layer 40 and the interlayer sacrificial layer 22 are simultaneously etched through the gate gap 60. Because the stop layer 40 has a faster etching rate, the width W1 of the first isolation trench 401 formed by the etching is greater than the width W2 of the second isolation trench 221. Next, the first isolation trench 401 and the second isolation trench 221 are filled with isolation material 41 and etched back. This completely removes the isolation material 41 located in the second isolation trench 221, while retaining a portion of the isolation material 41 in the first isolation trench 401 to form an isolation structure 42. Thus, when the interlayer sacrificial layer 22 is replaced to form the interlayer gate layer 22a, the isolation structure 42 blocks the etching of the stop layer 40, preventing its removal. Consequently, the stop layer 40 can be used as an etching stop layer when forming the contact hole 70, reducing etching difficulty and process cost. Furthermore, the thickness of the stop layer 40 can be adjusted according to the process. Compared with the process of directly etching the dielectric layer 50 and the interlayer gate layer 22a to form the contact hole 70, increasing the thickness of the stop layer 40 can reduce the etching selectivity requirement and increase the process window for etching the contact hole 70.

[0119] Please see Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for fabricating a memory according to another embodiment of the present invention. Please also refer to... Figures 4a-4c , Figures 4a-4c This is a schematic diagram of the structure of a memory provided in another embodiment of the present invention during the fabrication process. For ease of understanding and brief description, the same structures as those in the above embodiments are referred to by the same reference numerals. The fabrication method of this memory includes the following steps S100-S700, wherein the steps that are the same as those in the above embodiments will not be described again.

[0120] Please see Figure 3 Steps S100-S500 in the reference Figures 2a-2e .

[0121] Step S100: Provide substrate 10 (e.g.) Figure 2a (As shown).

[0122] Step S200: A stacked layer 20 is formed on the substrate 10. The stacked layer 20 includes alternating layers of interlayer insulating layers 21 and interlayer sacrificial layers 22. The stacked layer 20 includes a stepped region and has a stepped structure in the stepped region (e.g., ...). Figure 2a (As shown).

[0123] Following step S200, the fabrication of the memory may further include: forming an isolation layer 30 (e.g., silicon oxide) covering the stepped structure. Figure 2b (As shown).

[0124] Step S300: Form a stop layer 40 covering the stepped structure (e.g.) Figure 2c (As shown).

[0125] Step S400: Perform an ion implantation process on the stop layer 40 to make the reducibility of the stop layer 40 greater than that of the interlayer sacrificial layer 22.

[0126] In this embodiment, both the stop layer 40 and the interlayer sacrificial layer 22 are made of SiN (both have equal reducing power). The stop layer 40 can be ion-implanted, with the implanted ions including Si, to increase the Si-to-N ratio in the stop layer 40, thereby increasing its reducing power. This makes the reduced power of the treated stop layer 40 greater than that of the deposited interlayer sacrificial layer 22. It is understood that higher reducing power means easier oxidation; that is, the stop layer 40 is more easily oxidized after ion implantation than the interlayer sacrificial layer 22.

[0127] In one embodiment, a stop layer with greater reducibility than the interlayer sacrificial layer 22 can be directly formed, that is, step S400 can be omitted, and then subsequent steps can be performed.

[0128] After forming the stop layer 40, the method for fabricating the memory may further include: forming a dielectric layer 50 covering the stop layer 40 (e.g., ...). Figure 2d (As shown).

[0129] Step S500: Forming a grid line gap 60 that penetrates the stop layer 40 and the stepped structure (e.g. Figure 2e (As shown).

[0130] Please see Figure 3 Step S600 and Figures 4a-4c .

[0131] Step S600: The stop layer 40 and the interlayer sacrificial layer 22 are oxidized and etched through the gate line gap 60 to form an isolation structure 42a at the junction of the stop layer 40 and the gate line gap 60.

[0132] like Figure 4a As shown, an oxidation process is performed first. Specifically, the stop layer 40 and the interlayer sacrificial layer 22 are oxidized through the gate line gap 60 to form the first oxide 41a at the junction of the stop layer 40 and the gate line gap 60, and the second oxide 221a at the junction of the interlayer sacrificial layer 22 and the gate line gap 60. Since the stop layer 40 is more easily oxidized than the interlayer sacrificial layer 22 after processing, the stop layer 40 will be oxidized more than the interlayer sacrificial layer 22, resulting in the width W3 of the first oxide 41a being greater than the width W4 of the second oxide 221a.

[0133] like Figure 4b As shown, an etching process is then performed. Specifically, the first oxide 41a and the second oxide 221a are etched through the gate gap 60 to completely remove the second oxide 221a and expose the interlayer sacrificial layer 22. In the same etching process, since the width W3 of the first oxide 41a is greater than the width of the second oxide 221a, the first oxide 41a is not completely removed when the second oxide 221a is etched, and the remaining portion of the first oxide 41a becomes the isolation structure 42a.

[0134] In another embodiment, since the width of the first oxide 41a is W3, when ion implanting the stop layer 40 in step S400, the stop layer 40 can be modified only at the location corresponding to the gate gap 60. The width of the modified stop layer 40 only needs to be W3. Therefore, after modification, the reducibility of the stop layer 40 with a width of W3 at the location corresponding to the gate gap 60 increases, while the reducibility of the stop layer 40 in other areas remains unchanged. Thus, the first oxide 41a with a width of W3 can also be generated during the oxidation process in step S600.

[0135] like Figure 4b As shown, after the etching process, the width of the gate line gap 60 increases, and its width W5 is equal to the width W4 of the second oxide 221a. Therefore, the gate line gap 60 contacts the interlayer sacrificial layer 22 to facilitate the subsequent replacement process. An isolation structure 42a is provided between the stop layer 40 and the gate line gap 60.

[0136] Please see Figure 3 Step S700 and Figure 4c .

[0137] Step S700: Replace the interlayer sacrificial layer 22 with the interlayer gate layer 22a through the gate line gap 60.

[0138] The memory fabrication method provided in this embodiment first performs a special treatment on the stop layer 40 to make its reducibility greater than that of the interlayer sacrificial layer 22, meaning the stop layer 40 is more easily oxidized. Then, an oxidation process is performed on the stop layer 40 and the interlayer sacrificial layer 22 through the gate line gap 60 to form a first oxide 41a and a second oxide 221a (the width W3 of the first oxide 41a is greater than the width W4 of the second oxide 221a). Following this, an etching process is performed to completely remove the second oxide 221a while retaining a portion of the first oxide 41a to form the isolation structure 42a. Thus, when the interlayer sacrificial layer 22 is replaced to form the interlayer gate layer 22a, the stop layer 40 is not removed. Therefore, the stop layer 40 can reduce the etching difficulty and process cost when forming the contact hole 70. Furthermore, the thickness of the stop layer 40 can be adjusted according to the process. Compared to the process of directly etching the dielectric layer 50 and the interlayer gate layer 22a to form the contact hole 70, increasing the thickness of the stop layer 40 can reduce the etching selectivity requirement and increase the process window for etching the contact hole 70.

[0139] Please see Figure 5 and Figure 2p , Figure 5 This is a schematic diagram of the structure of the memory provided in an embodiment of the present invention.

[0140] The memory 100 includes a semiconductor layer 10', a stacked structure 20a, a stop layer 40, an isolation structure 42a, and a gate line slot structure 61. The stacked structure 20a is located on the semiconductor layer 10' and includes a stepped region. The stacked structure 20a has a stepped structure in the stepped region, and the stop layer 40 covers at least a portion of the stepped structure. The gate line slot structure 61 extends through the stepped structure, passes through the stop layer 40, and has a gap region 40a between it and the stop layer 40. The gap region 40a surrounds the gate line slot structure 61 and is surrounded by the stop layer 40. The isolation structure 42a covers a portion of the stepped structure and is located in the gap region 40a. That is, the orthographic projection of the isolation structure 42a onto the semiconductor layer 10' overlaps with the orthographic projection of the interlayer insulating layer 21 or interlayer gate layer 22a in the stacked structure 20a onto the semiconductor layer 10'. Alternatively, the stop layer 40 covers a portion of the stepped structure, and the isolation structure 42a covers the remaining portion of the stepped structure.

[0141] In this embodiment, both the isolation structure 42a and the interlayer insulating layer 21 can comprise oxides, such as silicon oxide. Thus, in the process of replacing the interlayer sacrificial layer with the interlayer gate layer 22a, the isolation structure 42a can function as an isolation layer 40 from being etched.

[0142] The stacked structure 20a includes alternately stacked interlayer insulating layers 21 and interlayer gate layers 22a. An exemplary material for the interlayer insulating layer 21 is silicon oxide, and an exemplary material for the interlayer gate layer 22a is tungsten. The stop layer 40 may be made of silicon nitride, and the isolation structure 42a may be made of silicon oxide. The gate gap structure 61 may be made of an insulating layer, or it may include an insulating material and a conductive material surrounded by the insulating material.

[0143] In one embodiment, the memory 100 further includes an isolation layer 30 located between the stepped structure and the stop layer 40. The isolation layer 30 may be made of silicon oxide, and its thickness may be less than that of the stop layer 40.

[0144] In this embodiment, the memory 100 further includes a dielectric layer 50 and word line contacts 71. The dielectric layer 50 is located on a stepped structure and covers the stop layer 40. The word line contacts 71 are located on each step, penetrating the dielectric layer 50 and the stop layer 40, and are connected to the interlayer gate layer 22a at each step.

[0145] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a memory provided in another embodiment of the present invention.

[0146] The memory 200 may further include a barrier layer 402, which includes a first barrier layer 4021, a second barrier layer 4022, and a third barrier layer 4023. The first barrier layer 4021 is located between the isolation structure 42 and the stop layer 40, the second barrier layer 4022 is located between the isolation structure 42 and the dielectric layer 50, and the third barrier layer 4023 is located between the isolation structure 42 and the interlayer insulating layer 21.

[0147] Furthermore, the memory 200 may also include a gate material layer 43, which is located between the isolation structure 42 and the gate line gap structure 61, and partially covers the stepped structure. The gate material layer 43 and the interlayer gate layer 22a comprise the same material, such as tungsten.

[0148] In the memory provided in this embodiment of the invention, an isolation structure 42 / 42a is spaced between the stop layer 40 located on the stepped structure and the gate line gap structure 61. Therefore, the stop layer 40 is not removed during the process of replacing the interlayer sacrificial layer with the interlayer gate layer 22a. Thus, the stop layer 40 serves as an etching stop layer when forming the word line contact 71, which can reduce the etching process difficulty and increase the process window during the formation of the word line contact 71.

[0149] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a storage system provided in an embodiment of the present invention. The storage system 300 includes a memory 301 and a controller 302. The memory 301 can be the memory in any of the above embodiments. The controller 302 is electrically connected to the memory 301 and is used to control the memory 301 to store data. The memory 301 can perform data storage operations based on the control of the controller 302.

[0150] In some implementations, the storage system may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0151] The memory 301 includes a substrate, a stacked structure, a stop layer, an isolation structure, and a gate line slot structure. The stacked structure is located on the substrate and includes a stepped region, wherein the stacked structure is stepped in the stepped region, and the stop layer covers the stepped structure. The gate line slot structure extends through the stop layer and the stepped structure. The isolation structure is located between the gate line slot structure and the stop layer.

[0152] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention; those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a memory, characterized in that, include: Provide substrate; A stacked layer is formed on the substrate, the stacked layer comprising alternating layers of interlayer insulating layers and interlayer sacrificial layers, the stacked layer including a stepped region and having a stepped structure in the stepped region; A stop layer is formed covering the stepped structure; Forming grid line gaps that penetrate the stop layer and the stepped structure; An isolation structure is formed at the junction of the stop layer and the gate wire gap; The interlayer sacrificial layer is replaced with an interlayer gate layer through the gate line gap; A contact hole is formed that penetrates the stop layer, and the bottom of the contact hole is located on the interlayer gate layer at each step of the stepped structure.

2. The method for fabricating a memory according to claim 1, characterized in that, The step of forming an isolation structure at the junction of the stop layer and the gate wire gap includes: The stop layer is etched through the gate line gaps to form a first isolation groove at the junction of the stop layer and the gate line gaps; The isolation structure is formed in the first isolation groove.

3. The method for fabricating a memory according to claim 2, characterized in that, The stop layer and the interlayer sacrificial layer comprise the same material, and the method for fabricating the memory further includes: The stop layer is processed so that, under the same conditions, the etching rate of the stop layer is greater than the etching rate of the interlayer sacrificial layer.

4. The method for fabricating a memory according to claim 3, characterized in that, The step of etching the stop layer through the gate line gaps includes: The stop layer and the interlayer sacrificial layer are etched through the gate line gaps to form the first isolation groove at the junction of the stop layer and the gate line gaps, and the second isolation groove at the junction of the interlayer sacrificial layer and the gate line gaps. Wherein, the width of the first isolation groove in the first direction is greater than the width of the second isolation groove in the first direction, and the first direction is perpendicular to the extension direction of the grid line gap.

5. The method for fabricating a memory according to claim 4, characterized in that, The step of forming the isolation structure in the first isolation groove includes: Deposit insulating material in the first isolation trench, the second isolation trench, and the grid line gaps; The isolation material is etched back to remove the isolation material located in the second isolation groove and the grid line gap, while retaining a portion of the isolation material located in the first isolation groove to form the isolation structure; The isolation structure has a groove between it and the grid line gap.

6. The method for fabricating a memory according to claim 5, characterized in that, Prior to the step of depositing isolation material in the first isolation trench, the second isolation trench, and the gate wire gap, the method for fabricating the memory further includes: A barrier layer is formed in the first isolation groove and the second isolation groove, as well as at the interface between the interlayer insulation layer and the gate wire gap; After the step of etching back the isolation material, the method for fabricating the memory further includes etching the barrier layer to remove the barrier layer located in the second isolation trench.

7. The method for fabricating a memory according to claim 5, characterized in that, The step of replacing the interlayer sacrificial layer with an interlayer gate layer through the gate line gap includes: The cavity is formed by removing the interlayer sacrificial layer; A gate material layer is filled in the cavity and the groove to form the interlayer gate layer at the location of the interlayer sacrificial layer.

8. The method for fabricating a memory according to claim 1, characterized in that, The reproducibility of the stop layer is greater than that of the interlayer sacrificial layer, and the step of forming an isolation structure at the junction of the stop layer and the gate wire gap includes: The stop layer and the interlayer sacrificial layer are oxidized through the gate line gap to form a first oxide at the junction of the stop layer and the gate line gap, and a second oxide at the junction of the interlayer sacrificial layer and the gate line gap. The width of the first oxide in a first direction is greater than the width of the second oxide in the first direction, and the first direction is perpendicular to the extension direction of the gate line gap. The first oxide and the second oxide are etched to remove the second oxide, while retaining a portion of the first oxide to form the isolation structure.

9. The method for fabricating a memory according to claim 1, characterized in that, The reducibility of the stop layer is equal to the reducibility of the interlayer sacrificial layer. Prior to the step of forming an isolation structure at the junction of the stop layer and the gate line gap, the method for fabricating the memory further includes: The stop layer is subjected to an ion implantation process to make the reducibility of the stop layer greater than that of the interlayer sacrificial layer.

10. The method for fabricating a memory according to claim 9, characterized in that, The stop layer is made of silicon nitride, and the implanted ions in the ion implantation process are silicon.

11. The method for fabricating a memory according to any one of claims 1-10, characterized in that, The step of forming a contact hole through the stop layer includes: A dielectric layer covering the stop layer is formed on the stepped structure; The dielectric layer and part of the stop layer on each step are etched to form contact holes, the bottom of which is located in the stop layer; The contact hole is etched further so that the bottom of the contact hole is located on the interlayer gate layer at each step.

12. The method for fabricating a memory according to any one of claims 1-10, characterized in that, Prior to the step of forming the stop layer covering the stepped structure, the method for fabricating the memory further includes: An isolation layer is formed between the stepped structure and the stop layer.

13. A memory, characterized in that, The memory includes: Semiconductor layer; A stacked structure is located on the semiconductor layer and includes a step region, wherein the stacked structure is a stepped structure in the step region; A stop layer that covers at least a portion of the stepped structure; A grid line slot structure extends through the stepped structure, the grid line slot structure passes through the stop layer and has a gap between it and the grid line slot structure; An isolation structure that covers part of the stepped structure and is located in the interval area; The letter contact points are located on each step of the stepped structure and penetrate the stop layer.

14. The memory according to claim 13, characterized in that, The stacked structure includes alternately stacked interlayer insulating layers and interlayer gate layers; the memory further includes: A dielectric layer is located on the stepped structure and covers the stop layer; The word line contact penetrates the dielectric layer and the stop layer, and the bottom of the word line contact is connected to the interlayer gate layer at each step.

15. The memory according to claim 14, characterized in that, The memory also includes: A barrier layer, the barrier layer comprising a first barrier layer, a second barrier layer and a third barrier layer; The first barrier layer is located between the isolation structure and the stop layer, the second barrier layer is located between the isolation structure and the dielectric layer, and the third barrier layer is located between the isolation structure and the interlayer insulation layer.

16. The memory according to claim 14, characterized in that, The memory also includes: A gate material layer is located between the isolation structure and the gate line gap structure, and partially covers the stepped structure.

17. The memory according to claim 16, characterized in that, The gate material layer and the interlayer gate layer comprise the same material.

18. The memory according to claim 13, characterized in that, The memory also includes: An isolation layer is located between the stepped structure and the stop layer.

19. The memory according to claim 14, characterized in that, Both the isolation structure and the interlayer insulation layer comprise oxides.

20. A storage system, characterized in that, include: The memory as described in any one of claims 13-19; A controller, electrically connected to the memory, is used to control the memory to store data.

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