Method of josephson junction fabrication

Abstract

The invention provides a method of Josephson junction fabrication. The invention relates to the fabrication of Josephson junctions. Such Josephson junctions can be suitable for use in terms of quantum bits. A high quality, possible single-crystal electrode and dielectric layer is formed using blanket deposition; the structure of one of the multiple Josephson junctions is then formed by using multi-photon lithography to create openings in a resist, followed by etching of the electrode and dielectric layer.

Description

Technical Field

[0001] The present invention relates to the fabrication of a Josephson junction, for example, which may be suitable for use in the field of qubits. Background Technology

[0002] The Josephson junction is the core component of a superconducting qubit, and its quality is a major factor in the qubit's lifetime. Traditionally, Josephson junctions used in superconducting qubits are fabricated using shadow evaporation: a hollow structure is defined on a resist by photolithography, allowing aluminum films deposited at different angles to overlap, with in-situ oxidation occurring in the middle, followed by stripping. The aluminum films and alumina layers formed in this way are typically polycrystalline, with a grain size of approximately 10 nm, significantly smaller than the junction size of approximately 100 nm.

[0003] In reality, a "macro" Josephson junction is composed of many smaller "micro" junctions seamed together. Due to the different lattice orientations and thicknesses of the alumina layers in each of the "micro" junctions, the supercurrent density is non-uniform. Therefore, the critical current (and normal-state resistance) of the "macro" junction is difficult to control. Non-uniform tunneling at grain boundaries and two-stage systems also shorten the lifetime of the qubit. Summary of the Invention

[0004] According to the present invention, a method for manufacturing a Josephson knot is provided. The method includes:

[0005] • A first stack is formed on a substrate, the first stack including a first electrode layer, a dielectric layer and a second electrode layer, the first stack being defined on at least an upper surface of the first stack opposite to the substrate and two side surfaces adjacent to the substrate and the upper surface;

[0006] • Trenches are formed in the stack via a first opening in the resist, extending across the entire width of the stack and across the entire depth of the second electrode layer and the dielectric layer; and

[0007] • A tunnel is formed in the stack via a second and a third opening in the resist, which is formed by multiphoton lithography. The tunnel extends from the second opening to the third opening across the entire width of the stack and across the entire depth of the first electrode layer and the dielectric layer.

[0008] Prior to forming the first stack, the method may include: forming a first electrode layer, a dielectric layer, and a second electrode layer, and etching the first electrode layer, dielectric layer, and second electrode layer into the shape of a superconducting quantum interference device (SQUID) ring. The SQUID ring shape is characterized by an elongated body extending parallel to the substrate and including an opening extending perpendicularly to the substrate through the first electrode layer, dielectric layer, and second electrode layer. The opening is surrounded on all sides by the first electrode layer, dielectric layer, and second electrode layer. The side of the opening extending parallel to the longitudinal axis of the elongated body is referred to as a “branch” of the SQUID ring.

[0009] The SQUID ring shape can be formed by etching the first electrode layer, the dielectric layer, and the second electrode layer through openings in the resist.

[0010] The first stack can be formed from one of the branches of the SQUID ring.

[0011] The first electrode layer, dielectric layer, and second electrode layer can be formed by blanket deposition using physical vapor deposition (PVD) or molecular beam epitaxy (MBE) after substrate pretreatment such as HF rinsing and / or in-situ annealing.

[0012] Forming a trench may include: forming a first resist over a first stack, the first resist covering at least the upper surface and side surfaces; creating a first opening in the first resist that exposes a portion of the upper surface of the stack; and performing wet etching or dry etching on the stack to form the trench.

[0013] Forming a tunnel may include: forming a second resist over a first stack, the second resist covering at least the upper surface and side surfaces; creating a second opening and a third opening in the second resist, the second opening exposing a portion of the first side surface of the stack, the third opening exposing a portion of the second side surface of the stack opposite to the first side surface, the third opening being the same size as the second opening and being positioned opposite to the second opening; and performing wet etching or dry etching on the stack to form a tunnel.

[0014] Alternatively, forming a tunnel may include: creating a second opening and a third opening in a first resist, the second opening exposing a portion of a first side surface of the stack, the third opening exposing a portion of a second side surface of the stack opposite to the first side surface, the third opening being the same size as the second opening and being positioned opposite to the second opening; and performing wet etching or dry etching on the stack to form a tunnel, while simultaneously performing wet etching or dry etching on the stack to form a trench.

[0015] The method may further include: controlling the etching time of the trench such that etching is stopped before the first electrode layer is completely etched; and / or controlling the etching time of the trench such that etching is stopped before the second electrode layer is completely etched.

[0016] The first and second electrode layers can be aluminum, and the dielectric layer can be aluminum oxide.

[0017] The alumina dielectric layer can have a single-crystal structure.

[0018] The method may also include the step of connecting a first electrode layer and / or a second electrode layer to one or more additional electrical components to form a quantum bit. Attached Figure Description

[0019] Figures 1 to 9 illustrate different stages of the method for manufacturing the Josephson junction of the present invention.

[0020] Figures 1A-9A A cross-sectional view of the stack at each stage of the method is shown.

[0021] Figures 1B-9B A perspective view of the stack at each stage of the method is shown.

[0022] Figure 10 A perspective view of a SQUID ring comprising two Josephson knots formed according to the method of the present invention is shown.

[0023] Figure 11 This is a flowchart depicting a method for manufacturing a Josephson junction according to the present invention. Detailed Implementation

[0024] At the first stage of the manufacturing process, Figure 1A and Figure 1B The final result is depicted in the diagram, where a stack is formed on a substrate 1. This stack includes a first electrode layer 2, a dielectric layer 3, and a second electrode layer 4. The first electrode layer 2 is adjacent to the substrate 1, and its lower surface 11 facing the substrate 1 is also referred to as the lower surface 11 of the stack. The dielectric layer 3 is located between the first electrode layer 2 and the second electrode layer 4. The second electrode layer 4, situated above the first electrode layer 2 and the dielectric layer 3 relative to the substrate 1, has an upper surface 12, which is also referred to as the upper surface 12 of the stack. The first electrode layer 2, the dielectric layer 3, and the second electrode layer 4 are generally flat and parallel to the substrate 1.

[0025] like Figure 1B As shown, the stack also has a first side 13 and a second side 14, which are generally perpendicular to the substrate 1 and extend through the first electrode layer 2, the dielectric layer 3 and the second electrode layer 4.

[0026] Substrate 1 can be a silicon wafer or any other suitable substrate. The wafer can be bare or have a superconducting film (e.g., Nb / Al / TiN, etc.) patterned with elements based on coplanar waveguides. The first electrode layer 2 and the second electrode layer 4 are preferably formed of aluminum, and the dielectric layer 3 is preferably formed of aluminum oxide (AlxOy, for example, Al2O3). This material selection can be referred to as an Al / AlxOy / Al trilayer. Methods for producing single-crystal aluminum oxide dielectric layers using in-situ annealing or oxidation are known in the art, for example, as described in Fritz et al., “Optimization of Al / AlOx / Al-layer systems for Josephson junctions from a microstructure point of view”, Journal of Applied Physics 125, 165301 (2019).

[0027] In an alternative embodiment of the present invention, the Al / AlxOy / Al trilayers 2, 3, and 4 are formed by physical vapor deposition (PVD), such as sputtering or electron beam evaporation and molecular beam epitaxy (MBE), after necessary pretreatment of the substrate, such as HF rinsing and / or in-situ annealing.

[0028] However, the process for producing high-quality single-crystal Al / AlxOy / Al trilayers using in-situ annealing requires high temperatures to form the trilayers, which hinders the use of shadow evaporation to form Josephson junction structures. Furthermore, MBE is incompatible with shadow evaporation because the resist used in shadow evaporation can contaminate the MBE chamber.

[0029] The method of this invention enables the Josephson junction structure to be formed from an Al / AlxOy / Al three-layer structure through blanket deposition, thereby providing a Josephson junction with the excellent properties provided by a high-quality single-crystal three-layer structure, such as improved critical current control, uniform tunneling, and reduced occurrence of two-stage systems within the Josephson junction. However, the method for fabricating a Josephson junction does not require these specific materials to be used for the three layers; therefore, other materials can be used for the first electrode layer 2, the second electrode layer 4, and the insulating layer, provided that the selected materials are capable of forming a Josephson junction.

[0030] After forming the first electrode layer 2, dielectric layer 3, and second electrode layer 4, the first electrode layer 2, dielectric layer 3, and second electrode layer 4 are patterned by wet / dry etching to form... Figure 1B The stack shown. Figure 1BThe stack shown has an elongated shape, wherein the length of the stack is greater than its width and height; however, it will be understood that, as shown, the relative size and shape of the stack are merely exemplary. Furthermore, as depicted in FIG9 and explained in more detail below, layers 2, 3, and 4 of the stack may extend beyond the figures or be part of a larger stack. The method of the invention can be performed as long as the upper surface 12 and sides 13, 14 are exposed.

[0031] Figure 2A and Figure 2B The following steps in the process are shown, in which substrate 1 and stacks 2, 3, and 4 are coated with resist 5. Figure 3A and Figure 3B An opening 21 is shown formed in the upper surface of the resist 5 to expose a portion of the upper surface 12 of the stacks 2, 3, and 4. The opening in the resist is formed by photolithography. The stacks are then wet / dry etched through the opening 21 in the resist 5 to form trenches 31, which... Figure 4A and Figure 4B As shown in the figure. After etching, the resist is removed, exposing the trench 31. The etching time is controlled so that the depth and width of the trench 31 extend through the second electrode layer 4 and the dielectric layer 3, but the depth of the trench does not extend through the first electrode layer 2.

[0032] like Figure 5A and Figure 5B As shown, a second photoresist 6 is formed above stacks 2, 3, and 4. The second photoresist 6 includes an opening 22 that exposes a portion of sides 13 and 14 of the stack. The opening 22 is positioned on opposite sides 13 / 14 of stacks 2, 3, and 4. The opening 22 in the photoresist 6 is formed using multiphoton lithography. After forming the photoresist 6 and the opening 22, the stack is again wet / dry etched to form a tunnel 32 extending from one side 13 / 14 of the stack to the other side. The tunnel 32... Figure 6A and Figure 6B As shown in the diagram, the size of the opening 22 and the etching time are controlled so that the height and width of the tunnel extend through the first electrode layer 2 and the dielectric layer 3, but the height of the tunnel does not extend through the second electrode layer 4. Figure 6A and Figure 6B As depicted in the text, the result of this process is the formation of a Josephson knot between trench 31 and tunnel 32.

[0033] As Figure 3A , Figure 3B , Figure 5A and Figure 5BAlternatives to the individual photoresists 5 and 6 shown, the steps illustrated in these figures can be combined into a single step, wherein a single photoresist provides two openings 21 and 22, and both trench 31 and tunnel 32 can be etched in the same step. This can be achieved by selecting appropriate sizes for openings 21 and 22 and etching times to simultaneously form trenches 31 and tunnels 32 of desired sizes. In this case, multiphoton lithography is used to form the two openings 21 and 22.

[0034] Figure 7A and Figures 7B-9A and Figure 9B Additional process steps related to the formation of the overall structure of a superconducting quantum interference device (SQUID), of which the Josephson junction is a component, are illustrated. The Josephson junction or SQUID formed through this process can be used as part of a superconducting quantum bit. In particular, the superconducting quantum bit is a nonlinear microwave resonator comprising a Josephson junction / SQUID and a capacitor. Figure 7A and Figures 7B-9A and Figure 9B The steps described therein can be Figure 1A and Figures 1B-6A and Figure 6B The steps described herein are performed prior to this. Figure 7A and Figure 7B The results of the first step of depositing three layers—a first electrode layer 2, a dielectric layer 3, and a second electrode layer 4—onto a substrate are shown. The formation of the three layers and the material of each layer are related to the above. Figure 1A and Figure 1B The description is the same.

[0035] Figure 8A and Figure 8B The image depicts a three-layer or stacked configuration 2, 3, 4, after resist 7 has been applied and the stack has been etched in the general form of a SQUID ring. An opening 23 is provided in the middle of the resist to define an opening 33 in the middle of the stack 2, 3, 4. As described above, resist 7 can be formed using conventional photolithography techniques relative to resist 5, and the three layers 2, 3, 4 are etched using a wet / dry etching process.

[0036] After etching to form the stacked shapes 2, 3, and 4, resist 7 is removed, leaving... Figure 9A and Figure 9B The shape depicted in the figure. After the resist is removed, the remaining stacks 2, 3, 4 include an opening 33 extending through the stacks 2, 3, 4 to the substrate 1. Each of the portions 41 and 42 of the stacks 2, 3, 4—which is adjacent to the opening 33 on the opposite side of the opening—can then be formed as shown in the figure. Figure 1A and Figures 1B-6A andFigure 6B Stacks 2, 3, and 4 are depicted in the diagram. Sections 41 and 42 can be referred to as "branches" of the SQUID ring. Based on the above... Figure 1A and Figures 1B-6A and Figure 6B The described method allows for the formation of Josephson knots on each of sections 41 and 42. The resulting SQUID loop comprises two Josephson knots 51 and 52. Figure 10 It is shown in the middle.

[0037] Figure 11 The above describes the manufacturing process. Figure 1A and Figures 1B-10 The method for creating a Josephson junction is described above. In step 101, a first stack of a first electrode layer 2, a dielectric layer 3, and a second electrode layer 4 is formed, as described above. Figure 1A and Figure 1B As described, or if the Josephson knot is formed as part of a SQUID ring, then as Figures 7A-7B As shown in Figure 102. In optional step 102, the stack can be etched into the form of a SQUID ring, as described above. Figure 7A / Figures 7B-9A / Figure 9B As described. If the Josephson junction is formed alone or is part of another structure, the method can continue in step 102 without etching the shape of the SQUID ring; alternatively, it can be formed by etching. Figure 1B The stacked shape shown. At step 103, as in... Figure 2A and Figure 2B The descriptions in the text and as mentioned above Figure 2A and Figure 2B As described, resist 5 is formed; and as in Figure 3A and Figure 3B The descriptions and information in the book Figure 3A and Figure 3B As described, a first opening 21 is formed in the resist. Optionally, if trenches 31 and tunnels 32 are formed simultaneously in the same etching step, a second opening 22 can also be formed in the first resist 5, which... Figure 5A and Figure 5B The depiction and about Figure 5A and Figure 5B As described. At step 104, trench 31 and optional tunnel 32 are etched, as described above regarding Figure 4A / Figure 4B and Figure 6A / Figure 6BAs described above. At step 105, if the tunnel 32 and trench 31 are not etched simultaneously, a second resist 6 can be formed over the stack, and a second opening 22 can be formed in the stack, as described above. Figure 5A and Figure 5B As described. Subsequently, the tunnel can be etched, as per [the description]. Figure 6A and Figure 6B As described. Once all the resist has been removed, the resulting Josephson junction... Figure 6A and Figure 6B The diagram is depicted in the image. With the stack first etched into the shape of a SQUID ring, two Josephson junctions 51 and 52 can be simultaneously formed by performing process steps on each portion 41, 42 of the SQUID ring concurrently. In this case, the resulting device... Figure 10 It is shown in the middle.

[0038] exist Figure 6B In cases where the Josephson junctions 51 and 52 shown are intended to form part of a qubit, other components besides the Josephson junction, such as capacitors and waveguides for the qubit, can be fabricated before or after the Josephson junction. If the capacitor for the qubit is fabricated before the Josephson junction, it will be connected to the first electrode layers on both sides of the Josephson junction. If the capacitor for the qubit is fabricated after the junction, it will be connected to the top Al on both sides of the Josephson junction. The “trench-tunnel” structure described above allows leads to be connected to either the first or second electrode layer on either side of the Josephson junction, thus eliminating the challenge of connecting to the second electrode layer without a direct electrical short circuit to the first electrode layer. For example, if the first electrode layer is connected to both sides of the Josephson junction, then on the trench side of the junction, the supercurrent flows exactly through the first electrode layer. On the tunnel side of the junction, the presence of the tunnel allows the supercurrent to flow from the first electrode layer to the second electrode layer. Essentially, the Josephson junction defined by the “trench and tunnel” can therefore be considered as being in series with a much larger Josephson junction on the tunnel side (or on the trench side if we connect to the top Al on both sides). Since the series Josephson junction is much larger in size, it will not affect the properties of the qubit.

Claims

1. A method of fabricating a Josephson junction, the method comprising: forming a first stack on a substrate, the first stack comprising a first electrode layer, a dielectric layer, and a second electrode layer, the first stack defining at least an upper surface on a surface of the first stack opposite the substrate and two side surfaces adjacent to the substrate and the upper surface; forming a trench in the stack via a first opening in a first resist, the trench extending across an entire width of the stack and across an entire depth of the second electrode layer and the dielectric layer; and forming a tunnel in the stack via a second opening and a third opening in the first resist or a second resist, the second and third openings formed by multiphoton lithography, the tunnel extending from the second opening to the third opening across an entire width of the stack and across an entire depth of the first electrode layer and the dielectric layer, such that a Josephson junction is formed between the trench and the tunnel.

2. The method of claim 1, wherein, Prior to forming the first stack, the method comprises: forming the first electrode layer, the dielectric layer, and the second electrode layer, and etching the first electrode layer, the dielectric layer, and the second electrode layer into a SQUID ring shape.

3. The method of claim 2, wherein, The SQUID ring shape is formed by etching the first electrode layer, the dielectric layer, and the second electrode layer via an opening in a resist.

4. The method of claim 2 or 3, wherein, The SQUID ring shape comprises an elongated body extending parallel to the substrate and comprises an opening extending through the first electrode layer, the dielectric layer, and the second electrode layer perpendicular to the substrate, wherein the opening is surrounded on all sides by the first electrode layer, the dielectric layer, and the second electrode layer, and wherein a side of the opening extending parallel to a longitudinal axis of the elongated body is referred to as a branch of the SQUID ring.

5. The method of claim 4, wherein, The first stack is formed from one of the branches of the SQUID ring.

6. The method of claim 1, wherein, The first electrode layer, the dielectric layer, and the second electrode layer are formed by, after a pre-treatment, blanket deposition using physical vapor deposition (PVD) or molecular beam epitaxy (MBE).

7. The method of claim 1, wherein, Forming the trench comprises: forming the first resist over the first stack, the first resist covering at least the upper surface and the side surfaces; creating a first opening in the first resist exposing a portion of the upper surface of the stack; wet etching or dry etching the stack to form the trench.

8. The method of claim 1, wherein, Forming the tunnel comprises: forming the second resist over the first stack, the second resist covering at least the upper surface and the side surfaces; creating the second and third openings in the second resist, the second opening exposing a portion of a first side surface of the stack, the third opening exposing a portion of a second side surface of the stack opposite the first side surface, the third opening being the same size as the second opening and positioned opposite the second opening; wet etching or dry etching the stack to form the tunnel.

9. The method of claim 1, wherein, forming the tunnel comprises: creating the second opening and the third opening in the first resist, the second opening exposing a portion of a first side surface of the stack, the third opening exposing a portion of a second side surface of the stack opposite the first side surface, the third opening being the same size as the second opening and positioned opposite the second opening; wet etching or dry etching the stack to form the tunnel while wet etching or dry etching the stack to form the trench.

10. The method of any one of claims 7 to 9, wherein, The method further comprises controlling the etching time of the trench such that etching is stopped before the first electrode layer is completely etched and / or controlling the etching time of the tunnel such that etching is stopped before the second electrode layer is completely etched.

11. The method of claim 1, wherein, The first electrode layer and the second electrode layer are aluminum and wherein the dielectric layer is aluminum oxide.

12. The method of claim 11, wherein, The aluminum oxide of the dielectric layer has a single crystal structure.

13. The method of claim 1, further comprising the step of: connecting the first electrode layer and / or the second electrode layer to one or more further electrical components to form a quantum bit.

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