A static amplifier and control method thereof

Abstract

The present invention discloses a static amplifier and a control method thereof, and relates to the field of circuit technology. The static amplifier comprises: a switch module, a PMOS tube module and an NMOS tube module; the switch module comprises a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; the PMOS tube module comprises a first PMOS tube and a second PMOS tube; the NMOS tube comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; the initial comparison voltage of the static amplifier can be transferred to the vicinity of the maximum amplification factor, and the influence caused by the mismatch on both sides of the static amplifier can be covered, thereby improving the sensitivity of the static amplifier, and improving the stability and reliability of the static amplifier.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a static amplifier and a control method thereof. Background Art

[0002] Static amplifiers are used in many scenarios. Static amplifiers compare and amplify two input signals with small differences and convert them into digital signal outputs. Static amplifiers have the advantages of low power consumption and high sensitivity.

[0003] at present, Figure 1 A circuit diagram of a conventional static amplifier is shown in FIG. Figure 1 As shown, the static amplifier consists of two groups of inverters (P1N1 / P2N2) and four switches (S0 / S0 / S2 / S3), and the input signal difference is amplified by the competition between the inverters.

[0004] However, as the feature size decreases, the mismatch between inverters increases, and the sensitivity of the traditional static amplifier is greatly affected, resulting in lower sensitivity of the traditional static amplifier and reduced stability and reliability of the static amplifier. Summary of the invention

[0005] The purpose of the present invention is to provide a new static amplifier and a control method thereof, so as to solve the problem that as the feature size decreases, the mismatch between inverters increases, the sensitivity of the traditional static amplifier is greatly affected, resulting in lower sensitivity of the traditional static amplifier and reduced stability and reliability of the static amplifier.

[0006] In a first aspect, the present invention provides a static amplifier, the static amplifier comprising: a switch module, a PMOS tube module and an NMOS tube module;

[0007] The switch module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; the PMOS tube module includes a first PMOS tube and a second PMOS tube; the NMOS tube includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube;

[0008] The drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the gate of the first PMOS tube is connected to the gate of the first NMOS tube, forming a first inverter; the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is connected to the gate of the second NMOS tube, forming a second inverter; the source of the first PMOS tube is connected to the source of the second PMOS tube and is connected to the power supply voltage, the first switch is provided between the drain and the gate of the first PMOS tube, and the second switch is provided between the drain and the gate of the second PMOS tube; the source of the first NMOS tube is connected to the common voltage ground terminal through the third switch, and is connected to the third NMOS tube through the fifth switch; the source of the second NMOS tube is connected to the common voltage ground terminal through the fourth switch, and is connected to the fourth NMOS tube through the sixth switch; the source of the third NMOS tube is connected to the source of the fourth NMOS tube, and is connected to the drain of the fifth NMOS tube, and the gate of the fifth NMOS tube is connected to the bias voltage.

[0009] In the case of adopting the above technical solution, the static amplifier provided in the embodiment of the present application includes: the static amplifier includes: a switch module, a PMOS tube module and an NMOS tube module; the switch module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; the PMOS tube module includes a first PMOS tube and a second PMOS tube; the NMOS tube includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; wherein the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the gate of the first PMOS tube is connected to the gate of the first NMOS tube to form a first inverter; the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is connected to the gate of the second NMOS tube to form a second inverter; the source of the first PMOS tube and The source of the second PMOS tube is connected and connected to the power supply voltage, the first switch is arranged between the drain and the gate of the first PMOS tube, and the second switch is arranged between the drain and the gate of the second PMOS tube; the source of the first NMOS tube is connected to the common voltage ground terminal through the third switch, and is connected to the third NMOS tube through the fifth switch; the source of the second NMOS tube is connected to the common voltage ground terminal through the fourth switch, and is connected to the fourth NMOS tube through the sixth switch; the source of the third NMOS tube is connected to the source of the fourth NMOS tube, and is connected to the drain of the fifth NMOS tube, and the gate of the fifth NMOS tube is connected to the bias voltage, so that the initial comparison voltage of the static amplifier can be transferred to the vicinity of the maximum amplification factor, and can cover the influence caused by the mismatch on both sides of the static amplifier, thereby improving the sensitivity of the static amplifier and improving the stability and reliability of the static amplifier.

[0010] In a possible implementation manner, a gate of the third NMOS transistor is connected to a first input signal.

[0011] In a possible implementation manner, a gate of the fourth NMOS transistor is connected to a second input signal.

[0012] In a possible implementation manner, the working range of the static amplifier and the input signal are configured to be isolated.

[0013] In a second aspect, the present invention further provides a control method for a static amplifier, which is applied to any static amplifier described in the first aspect, and the control method comprises:

[0014] In the presetting stage, the fifth switch and the sixth switch are controlled to be in an open state, the first switch, the second switch, the third switch and the fourth switch are in a closed state, the first inverter and the second inverter are connected end to end, and the target voltage value in the current state is determined;

[0015] In the amplification stage, the input voltage is controlled to be connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube, the first switch, the second switch, the third switch and the fourth switch are in an open state, and the fifth switch and the sixth switch are in a closed state. Based on the input voltage, in combination with the first inverter and the second inverter, the secondary amplification output of the input signal difference is completed.

[0016] In a possible implementation, in the amplification stage, controlling the input voltage to be connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube includes:

[0017] In the amplification stage, the first input voltage corresponding to the first input signal is controlled to be connected to the gate of the third NMOS tube, and the second input voltage corresponding to the second input signal is controlled to be connected to the gate of the fourth NMOS tube.

[0018] In a possible implementation, the step of completing secondary amplification and outputting the input signal difference based on the input voltage in combination with the first inverter and the second inverter includes:

[0019] When the first input voltage is greater than the second input voltage, the difference between the first input voltage and the second input voltage is amplified by the third NMOS tube and the fourth NMOS tube, and the secondary amplification output is completed in combination with the competitive amplification effect of the first inverter and the second inverter.

[0020] In a possible implementation, in the presetting stage, determining the target voltage value in the current state includes:

[0021] In the presetting stage, the target voltage value of the static amplifier is set near the maximum gain, and the error caused by the left-right mismatch is eliminated.

[0022] The beneficial effects of the control method of the static amplifier provided in the second aspect are the same as the beneficial effects of the static amplifier described in the first aspect or any possible implementation of the first aspect, and are not elaborated here.

[0023] In a third aspect, the present invention further provides an operational amplifier device, comprising any static amplifier described in the first aspect.

[0024] The beneficial effects of the operational amplifier device provided in the third aspect are the same as the beneficial effects of the static amplifier described in the first aspect or any possible implementation of the first aspect, and are not elaborated here.

[0025] In a fourth aspect, the present invention further provides an electronic device comprising: one or more processors; and one or more machine-readable media having instructions stored thereon, which, when executed by the one or more processors, enables the electronic device to execute the operational amplifier device described in any possible implementation method of the third aspect.

[0026] The beneficial effects of the electronic device provided in the fourth aspect are the same as the beneficial effects of the operational amplifier device described in the third aspect or any possible implementation of the third aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0028] Figure 1 A circuit diagram of a conventional static amplifier is shown;

[0029] Figure 2 A schematic diagram of the circuit structure of a static amplifier provided in an embodiment of the present application is shown;

[0030] Figure 3 A schematic diagram of input and output curves of a static amplifier provided in an embodiment of the present application is shown;

[0031] Figure 4 A schematic diagram of input and output curves of another static amplifier provided in an embodiment of the present application is shown;

[0032] Figure 5 A schematic flow chart of a control method for a static amplifier provided in an embodiment of the present application is shown;

[0033] Figure 6 A schematic flow chart of another method for controlling a static amplifier provided in an embodiment of the present application is shown;

[0034] Figure 7 A schematic diagram of the hardware structure of an electronic device provided by an embodiment of the present invention;

[0035] Figure 8 A schematic diagram of the structure of a chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0037] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0038] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0039] Figure 2 A circuit diagram of a static amplifier provided in an embodiment of the present application is shown. Figure 2 As shown, the static amplifier comprises:

[0040] Switch module, PMOS tube module and NMOS tube module;

[0041] The switch module includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5 and a sixth switch S6; the PMOS transistor module includes a first PMOS transistor P1 and a second PMOS transistor P2; the NMOS transistor includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4 and a fifth NMOS transistor N5;

[0042] The drain of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1, and the gate of the first PMOS transistor P1 is connected to the gate of the first NMOS transistor N1, forming a first inverter INV1;

[0043] The drain of the second PMOS transistor P2 is connected to the drain of the second NMOS transistor N2, and the gate of the second PMOS transistor P2 is connected to the gate of the second NMOS transistor N2, forming a second inverter INV2;

[0044] The source of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2 and is also connected to the power supply voltage VDD, the first switch S1 is provided between the drain and the gate of the first PMOS transistor P1, and the second switch S2 is provided between the drain and the gate of the second PMOS transistor P2;

[0045] The source of the first NMOS transistor N1 is connected to the common voltage ground terminal VSS through the third switch S3, and is connected to the third NMOS transistor N3 through the fifth switch S5; the source of the second NMOS transistor N2 is connected to the common voltage ground terminal VSS through the fourth switch S4, and is connected to the fourth NMOS transistor N4 through the sixth switch S6; the source of the third NMOS transistor N3 is connected to the source of the fourth NMOS transistor N4, and is connected to the drain of the fifth NMOS transistor N5, and the gate of the fifth NMOS transistor N5 is connected to the bias voltage.

[0046] In summary, the static amplifier provided in the embodiment of the present application includes: the static amplifier includes: a switch module, a PMOS tube module and an NMOS tube module; the switch module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; the PMOS tube module includes a first PMOS tube and a second PMOS tube; the NMOS tube includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; wherein the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the gate of the first PMOS tube is connected to the gate of the first NMOS tube to form a first inverter; the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is connected to the gate of the second NMOS tube to form a second inverter; the source of the first PMOS tube is connected to the source of the second The source of the first PMOS tube is connected to the power supply voltage, the first switch is arranged between the drain and the gate of the first PMOS tube, and the second switch is arranged between the drain and the gate of the second PMOS tube; the source of the first NMOS tube is connected to the common voltage ground terminal through the third switch, and is connected to the third NMOS tube through the fifth switch; the source of the second NMOS tube is connected to the common voltage ground terminal through the fourth switch, and is connected to the fourth NMOS tube through the sixth switch; the source of the third NMOS tube is connected to the source of the fourth NMOS tube, and is connected to the drain of the fifth NMOS tube, and the gate of the fifth NMOS tube is connected to the bias voltage, so that the initial comparison voltage of the static amplifier can be transferred to the vicinity of the maximum amplification factor, and the influence caused by the mismatch on both sides of the static amplifier can be covered, thereby improving the sensitivity of the static amplifier and improving the stability and reliability of the static amplifier.

[0047] Optional, see Figure 1 The gate of the third NMOS tube N3 is connected to the first input signal In1, and the gate of the fourth NMOS tube N4 is connected to the second input signal In1.

[0048] Optionally, the operating range of the static amplifier and the input signal are configured to be isolated.

[0049] For example, Figure 3 FIG. 4 shows a schematic diagram of an input-output curve of a static amplifier provided in an embodiment of the present application. Figure 3 As shown in the figure, when the static amplifier compares data, the initial voltage value of each node is determined by the voltage being compared. If the voltage being compared deviates far from the center point, the inverter gain is small and the flip is slow. In addition, in an ideal situation, the two inverters are exactly the same, and their input and output curves are as follows: Figure 3As shown, the dotted line represents VDD / 2.

[0050] Figure 4 FIG. 1 shows a schematic diagram of input-output curves of another static amplifier provided in an embodiment of the present application. If there is a mismatch between two inverters, the input-output curves of the two inverters are as follows: Figure 4 As shown, if the difference between the two input signals is Δv, an erroneous output result will be obtained. The present invention sets the initial voltage value of the inverter to the intersection of the two input and output curves. At this time, the amplification factor of the inverter is the largest, and the data can be quickly compared. At this time, the difference of the input signal is based on the intersection as the reference point, eliminating the influence of mismatch.

[0051] In summary, the static amplifier provided in the embodiment of the present application includes: the static amplifier includes: a switch module, a PMOS tube module and an NMOS tube module; the switch module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; the PMOS tube module includes a first PMOS tube and a second PMOS tube; the NMOS tube includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; wherein the drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the gate of the first PMOS tube is connected to the gate of the first NMOS tube to form a first inverter; the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is connected to the gate of the second NMOS tube to form a second inverter; the source of the first PMOS tube is connected to the source of the second The source of the first PMOS tube is connected to the power supply voltage, the first switch is arranged between the drain and the gate of the first PMOS tube, and the second switch is arranged between the drain and the gate of the second PMOS tube; the source of the first NMOS tube is connected to the common voltage ground terminal through the third switch, and is connected to the third NMOS tube through the fifth switch; the source of the second NMOS tube is connected to the common voltage ground terminal through the fourth switch, and is connected to the fourth NMOS tube through the sixth switch; the source of the third NMOS tube is connected to the source of the fourth NMOS tube, and is connected to the drain of the fifth NMOS tube, and the gate of the fifth NMOS tube is connected to the bias voltage, so that the initial comparison voltage of the static amplifier can be transferred to the vicinity of the maximum amplification factor, and the influence caused by the mismatch on both sides of the static amplifier can be covered, thereby improving the sensitivity of the static amplifier and improving the stability and reliability of the static amplifier.

[0052] Figure 5 A schematic diagram showing a control method for a static amplifier provided in an embodiment of the present application is shown. Figure 2The static amplifier shown in Figure 5 As shown, the control method includes:

[0053] Step 101: In a preset stage, the fifth switch and the sixth switch are controlled to be in an open state, the first switch, the second switch, the third switch and the fourth switch are in a closed state, the first inverter and the second inverter are connected end to end, and a target voltage value in a current state is determined.

[0054] Step 102: In the amplification stage, the input voltage is controlled to be connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube, the first switch, the second switch, the third switch and the fourth switch are in the open state, the fifth switch and the sixth switch are in the closed state, and based on the input voltage, combined with the first inverter and the second inverter, the secondary amplification output of the input signal difference is completed.

[0055] The control method of the static amplifier provided in the embodiment of the present application, in the pre-setting stage, the fifth switch and the sixth switch are controlled to be in the open state, the first switch, the second switch, the third switch and the fourth switch are in the closed state, the first inverter and the second inverter are connected end to end, and the target voltage value in the current state is determined; in the amplification stage, the input voltage is controlled to be connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube, the first switch, the second switch, the third switch and the fourth switch are in the open state, and the fifth switch and the sixth switch are in the closed state; based on the input voltage, in combination with the first inverter and the second inverter, the secondary amplification output of the input signal difference is completed, so that the initial comparison voltage of the static amplifier can be transferred to the vicinity of the maximum amplification factor, and the influence caused by the mismatch on both sides of the static amplifier can be covered, thereby improving the sensitivity of the static amplifier and improving the stability and reliability of the static amplifier.

[0056] Figure 6 FIG. 4 is a flow chart showing another method for controlling a static amplifier provided in an embodiment of the present application. Figure 6 As shown, the control method includes:

[0057] Step 201: In the preset stage, the fifth switch and the sixth switch are controlled to be in an open state, the first switch, the second switch, the third switch and the fourth switch are in a closed state, the first inverter and the second inverter are connected end to end, and the target voltage value in the current state is determined.

[0058] In the present application, in the presetting stage, the target voltage value of the static amplifier is set near the maximum gain, and the error caused by the left-right mismatch is eliminated.

[0059] Step 202: In the amplification stage, the first input voltage corresponding to the first input signal is controlled to be connected to the gate of the third NMOS tube, and the second input voltage corresponding to the second input signal is controlled to be connected to the gate of the fourth NMOS tube, the first switch, the second switch, the third switch and the fourth switch are in an open state, and the fifth switch and the sixth switch are in a closed state. When the first input voltage is greater than the second input voltage, the difference between the first input voltage and the second input voltage is amplified by the third NMOS tube and the fourth NMOS tube, and the secondary amplification output is completed in combination with the competitive amplification effect of the first inverter and the second inverter.

[0060] See also Figure 2 In the amplification stage, the input voltages In1 and In2 are first connected to the gates of N3 and N4 respectively, then the switches S1 / S2 / S3 / S4 are opened, and the switches S5 / S6 are closed. The difference in the input signals will cause different conduction capabilities of N3 and N4. If the voltage of In1 is greater than that of In2, the voltage at point A will drop rapidly, and the voltage at point D will drop briefly before rising due to the conduction of P2. The difference in the input signals is first amplified by N3 / N4, and then amplified twice under the competitive amplification of the INV1 / INV2 inverters, and finally the amplified data is output through points A and D.

[0061] The control method of the static amplifier provided in the embodiment of the present application, in the pre-setting stage, the fifth switch and the sixth switch are controlled to be in the open state, the first switch, the second switch, the third switch and the fourth switch are in the closed state, the first inverter and the second inverter are connected end to end, and the target voltage value in the current state is determined; in the amplification stage, the input voltage is controlled to be connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube, the first switch, the second switch, the third switch and the fourth switch are in the open state, and the fifth switch and the sixth switch are in the closed state; based on the input voltage, in combination with the first inverter and the second inverter, the secondary amplification output of the input signal difference is completed, so that the initial comparison voltage of the static amplifier can be transferred to the vicinity of the maximum amplification factor, and the influence caused by the mismatch on both sides of the static amplifier can be covered, thereby improving the sensitivity of the static amplifier and improving the stability and reliability of the static amplifier.

[0062] The present invention provides a control method for a static amplifier, which can achieve the following Figure 2 The static amplifier shown will not be described here in detail to avoid repetition.

[0063] The present invention also provides an operational amplifier device, comprising Figure 2The quiescent amplifier is shown.

[0064] The electronic device in the embodiment of the present invention may be a device, or a component, integrated circuit, or chip in a terminal. The device may be a mobile electronic device or a non-mobile electronic device. For example, the mobile electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc. The non-mobile electronic device may be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, etc., which is not specifically limited in the embodiment of the present invention.

[0065] The electronic device in the embodiment of the present invention may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present invention.

[0066] Figure 7 FIG. 1 is a schematic diagram showing the hardware structure of an electronic device provided by an embodiment of the present invention. Figure 7 As shown, the electronic device 300 includes a processor 310 .

[0067] like Figure 7 As shown, the processor 310 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention.

[0068] like Figure 7 As shown, the electronic device 300 may further include a communication line 340. The communication line 340 may include a path for transmitting information between the above components.

[0069] Optional, such as Figure 7 As shown, the electronic device may further include a communication interface 320. There may be one or more communication interfaces 320. The communication interface 320 may use any transceiver or other device for communicating with other devices or communication networks.

[0070] Optional, such as Figure 7As shown, the electronic device may further include a memory 330. The memory 330 is used to store computer-executable instructions for executing the solution of the present invention, and is controlled to execute by a processor. The processor is used to execute the computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the present invention.

[0071] like Figure 7 As shown, the memory 330 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 330 may exist independently and be connected to the processor 310 via a communication line 340. The memory 330 may also be integrated with the processor 310.

[0072] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0073] In a specific implementation, as an example, Figure 7 As shown, the processor 310 may include one or more CPUs, such as Figure 7 CPU0 and CPU1 in.

[0074] In a specific implementation, as an example, Figure 7 As shown, the terminal device may include multiple processors, such as Figure 7 The processor 310 in the embodiment of the present invention. Each of these processors can be a single-core processor or a multi-core processor.

[0075] Figure 8 Schematic diagram of the structure of the chip provided by the embodiment of the present invention. Figure 8 As shown, the chip 400 includes one or more (including two) processors 310 .

[0076] Optional, such as Figure 8As shown, the chip also includes a communication interface 320 and a memory 330. The memory 330 may include a read-only memory and a random access memory, and provide operation instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory (NVRAM).

[0077] In some embodiments, Figure 8 As shown, the memory 330 stores the following elements, execution modules or data structures, or their subsets, or their extended sets.

[0078] In the embodiment of the present invention, Figure 8 As shown, the corresponding operation is performed by calling the operation instruction stored in the memory (the operation instruction may be stored in the operating system).

[0079] like Figure 8 As shown, the processor 310 controls the processing operations of any one of the terminal devices, and the processor 310 may also be referred to as a central processing unit (CPU).

[0080] like Figure 8 As shown, the memory 330 may include a read-only memory and a random access memory, and provide instructions and data to the processor. A portion of the memory 330 may also include an NVRAM. For example, in an application, the memory, the communication interface, and the memory are coupled together through a bus system, wherein the bus system may include a power bus, a control bus, and a status signal bus in addition to a data bus. However, for the sake of clarity, in Figure 8 Various buses are labeled as bus system 410 .

[0081] like Figure 8As shown, the method disclosed in the above embodiment of the present invention can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor may be a general-purpose processor, a digital signal processor (digital signal processing, DSP), an ASIC, a field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present invention can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0082] On the one hand, a computer-readable storage medium is provided, in which instructions are stored. When the instructions are executed, the functions performed by the terminal device in the above embodiment are implemented.

[0083] On the one hand, a chip is provided, which is applied to a terminal device. The chip includes at least one processor and a communication interface. The communication interface is coupled to the at least one processor, and the processor is used to run instructions to implement the functions performed by the static amplifier in the above embodiment.

[0084] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present invention is executed in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user device or other programmable device. The computer program or instruction can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program or instruction can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, a hard disk, or a tape; it can also be an optical medium, such as a digital video disc (DVD); it can also be a semiconductor medium, such as a solid state drive (SSD).

[0085] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0086] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A static amplifier, characterized in that: The static amplifier comprises: Switch module, PMOS tube module and NMOS tube module; The switch module includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch and a sixth switch; the PMOS tube module includes a first PMOS tube and a second PMOS tube; the NMOS tube includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; The drain of the first PMOS tube is connected to the drain of the first NMOS tube, and the gate of the first PMOS tube is connected to the gate of the first NMOS tube, forming a first inverter; the drain of the second PMOS tube is connected to the drain of the second NMOS tube, and the gate of the second PMOS tube is connected to the gate of the second NMOS tube, forming a second inverter; the source of the first PMOS tube is connected to the source of the second PMOS tube and is connected to the power supply voltage, the first switch is provided between the drain and the gate of the first PMOS tube, and the second switch is provided between the drain and the gate of the second PMOS tube; The source of the first NMOS tube is connected to the common voltage ground terminal through the third switch, and is connected to the drain of the third NMOS tube through the fifth switch; the source of the second NMOS tube is connected to the common voltage ground terminal through the fourth switch, and is connected to the drain of the fourth NMOS tube through the sixth switch; the source of the third NMOS tube is connected to the source of the fourth NMOS tube, and is connected to the drain of the fifth NMOS tube, and the gate of the fifth NMOS tube is connected to the bias voltage; the source of the fifth NMOS tube is grounded; the gate of the third NMOS tube is connected to the first input signal; and the gate of the fourth NMOS tube is connected to the second input signal.

2. The static amplifier according to claim 1, characterized in that: The operating range of the static amplifier and the input signal are configured to be isolated.

3. A control method for a static amplifier, characterized in that: Applied to the static amplifier according to any one of claims 1 to 2, the control method comprises: In the presetting stage, the fifth switch and the sixth switch are controlled to be in an open state, the first switch, the second switch, the third switch and the fourth switch are in a closed state, the first inverter and the second inverter are connected end to end, and the target voltage value in the current state is determined; In the amplification stage, the input voltage is controlled to be connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube, the first switch, the second switch, the third switch and the fourth switch are in an open state, and the fifth switch and the sixth switch are in a closed state. Based on the input voltage, in combination with the first inverter and the second inverter, the secondary amplification output of the input signal difference is completed.

4. The control method of the static amplifier according to claim 3, characterized in that: In the amplification stage, controlling the input voltage to be connected to the gate of the third NMOS tube and the gate of the fourth NMOS tube includes: In the amplification stage, the first input voltage corresponding to the first input signal is controlled to be connected to the gate of the third NMOS tube, and the second input voltage corresponding to the second input signal is controlled to be connected to the gate of the fourth NMOS tube.

5. The control method of the static amplifier according to claim 4, characterized in that: The method of completing secondary amplification and outputting the input signal difference based on the input voltage and combining the first inverter and the second inverter includes: When the first input voltage is greater than the second input voltage, the difference between the first input voltage and the second input voltage is amplified by the third NMOS tube and the fourth NMOS tube, and the secondary amplification output is completed in combination with the competitive amplification effect of the first inverter and the second inverter.

6. The control method of the static amplifier according to any one of claims 3 to 5, characterized in that: In the presetting stage, the target voltage value under the current state is determined, including: In the presetting stage, the target voltage value of the static amplifier is set near the maximum gain, and the error caused by the left-right mismatch is eliminated.

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