Control method, system, device and medium for large bit width data bus segment storage

Abstract

The present invention belongs to the technical field of data transmission and storage, and discloses a control method, system, device and medium for segmented storage of a large-bit-width data bus, which calculates the starting address and the ending address of each data; calculates the cross-row flag; calculates the byte enable of the segmented memory; calculates the segment enable of the segmented memory; and calculates the address and data format of the segmented memory. Since the present invention empties the bubble space in the memory, the number of additional memory accesses required due to small batches of data is reduced, and each memory access is guaranteed to be 100% bandwidth, thereby improving the throughput of the memory. Since the present invention empties the bubble space in the memory, there is no memory fragmentation in the memory, and each bit can be used, and the utilization rate of the memory space is greatly improved. The present invention improves the throughput rate of storing large-bit-width bus data, ensures that each memory access is 100% bandwidth, and improves the utilization rate of the memory storage space.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission and storage, and in particular to a control method, system, device and medium for large-bit-width data bus segmented storage. Background Art

[0002] At present, large-bit-width data buses are often used in parallel high-speed buses, with the characteristics of large bit width and high bandwidth; they are used in fields such as PCIe, USB, and high-speed Ethernet. In the process of data transmission on large-bit-width data buses, it is necessary to store or read large amounts of data in the buffer memory, and the way data is accessed will affect the memory bandwidth, and thus affect the performance of the system.

[0003] Currently, in data transmission applications with large bit width data buses, dual-port RAM or FIFO is used to implement data receiving buffering. However, due to different system functions, the memory access process may need to follow the address boundary rule, which may cause the first data of the data frame on the data bus to carry only a small amount of data due to the memory access address boundary; the last data in the data frame also carries a small amount of data due to the small amount of remaining data. When using traditional RAM or FIFO cache, although these two data carry a small amount of data, they still need to occupy two storage spaces. The subsequent processing circuit also needs to read this part of the data in the memory twice, which wastes the system bandwidth. It takes more time to read a small amount of data, and the small amount of data will occupy the storage unit alone, forming memory fragmentation, wasting storage resources.

[0004] Through the above analysis, the problems and defects of the prior art are as follows:

[0005] (1) The existing technology does not fully utilize the bandwidth of the memory and cannot achieve maximum efficiency when facing small batches of data in transmission. It takes more time to read and process.

[0006] (2) The prior art does not fully utilize the memory space. A small amount of data in transmission will occupy a storage unit alone, and other storage space in this storage unit cannot be used, resulting in memory fragmentation and reducing the effective memory space.

[0007] The difficulty of solving the above problems and defects is: it is necessary to divide the memory into memory segments, establish a mapping relationship between the common memory interface and the segmented memory, and make the use of the segmented memory as convenient as the use of the common memory.

[0008] The significance of solving the above problems and defects is that the present invention improves the throughput of storing large-bit-width bus data, ensures 100% bandwidth each time the memory is accessed, and improves the utilization of the memory storage space. Summary of the invention

[0009] In view of the problems existing in the prior art, the present invention provides a control method, system, device and medium for large-bit-width data bus segmented storage, which are used to improve memory throughput and increase memory utilization.

[0010] The present invention is implemented in this way: a control method for large bit width data bus segmented storage, the control method for large bit width data bus segmented storage comprising the following steps:

[0011] Step 1, calculate the starting address and ending address of each data;

[0012] Step 2, calculating the cross-line flag;

[0013] Step 3, calculating the byte enable of the segmented memory;

[0014] Step 4, calculating the segment enable of the segmented memory;

[0015] Step 5, calculating the address of the segmented memory;

[0016] Step six, calculate the data format of the segmented memory.

[0017] Further, the calculation of the starting address and the ending address of each data in step 1 includes:

[0018] When storing data other than the last one in a data stream, the address input by the Local-Link write interface is used as the starting address, and the width of the Local-Link data bus is accumulated in bytes each time as the starting address of the data, and the starting address in bytes plus the width of the data bus is used as the ending address; when storing the last data in a data stream, the starting address of the previous data is used as the reference, and the width of the data bus is added in bytes as the starting address, and the starting address plus the number of valid bytes of the last data in a data stream is used as the ending address; when storing a single data frame, the starting address is the address input by the Local-Link write interface, and the starting address plus the number of valid bytes of this data is used as the ending address.

[0019] The Local-Link write interface is defined as follows:

[0020] Data bus, the bit width is the same as the bit width of a memory segment;

[0021] The address bus has a bit width equal to the sum of the address bit width of a segment of the segment memory and the logarithm of the bit width of all segment bytes of the segment memory with base 2;

[0022] Byte is valid, indicating the last valid byte of the last data in a frame;

[0023] The start signal indicates the first data of a frame;

[0024] End signal, indicating the last data of a frame;

[0025] Valid signal, indicating that all signals transmitted on the bus are valid;

[0026] Ready signal, indicating that the RAM is not full.

[0027] Further, the calculation of the cross-bank flag in step 2 includes:

[0028] Use logical right shift to divide the starting address in bytes by the data bit width of all storage segments, and the result is the row number of the memory where the starting address is located; use logical right shift to divide the ending address in bytes by the data bit width of all storage segments, and the result is the row number of the memory where the ending address is located; compare the two results, if they are consistent, the stored data does not cross rows, otherwise the data that crosses rows will be processed.

[0029] Further, the byte enable of the calculation segment memory in step 3 includes:

[0030] If the stored data does not cross rows, shift the sequence with all bits as 1 to the left by the low bit of the starting address to obtain the byte enable from the perspective of the starting address, and shift the sequence with all bits as 1 to the right by the complement of the low bit of the ending address to obtain the byte enable from the perspective of the ending address; perform bitwise AND on the byte enable from the perspective of the starting address and the byte enable from the perspective of the ending address to obtain the byte enable used by this data in the segmented memory; if the stored data crosses rows, perform bitwise OR on the byte enable from the perspective of the starting address and the byte enable from the perspective of the ending address to obtain the byte enable used by this data in the segmented memory.

[0031] Further, the segment enable of the computing segment memory in step 4 includes:

[0032] Divide the byte enable by storage segment. If all the byte enables of the storage segment are 0, the segment enable of the storage segment is cleared; if the byte enable of the storage segment is not 0, the segment enable of the storage segment is set.

[0033] The address of the segment memory calculated in step 5 includes:

[0034] If the stored data does not cross rows, take the high bit of the storage row number expressed by the starting address and use it as the row address of each segment of the segmented memory; if the stored data crosses rows, add 1 to the original row address of the storage segment with segment number 0, and the calculation method of the row addresses of the remaining segments remains unchanged;

[0035] The data format of the calculation segment memory in step 6 includes:

[0036] Copy the data into the number of segments plus 1 and splice them into one data. Take the low bit of the starting address to represent the offset of the starting address in a storage segment. Perform a logical right shift operation on the spliced ​​data according to the offset. Align the 0 bit of one of the data segments in the spliced ​​data with the position of the starting address.

[0037] Further, the read operation of the controller for large bit width data bus segment storage includes:

[0038] (1) Calculate the read start address of each data:

[0039] When reading the first data in a frame of data stream, the address input by the Local-Link read interface is used as the read start address; when reading data other than the first data in a frame of data stream, the read start address is the address input by the Local-Link read interface plus the bit width of a single storage segment in bytes;

[0040] (2) Calculate the segment enable of the segmented memory:

[0041] The segment enable of the segmented memory is consistent with the value of the read mask;

[0042] (3) Calculate the address of the segmented memory:

[0043] When the bit corresponding to the segment number in the mask is 1, the high bit of the storage row number expressed by the start address is taken and used as the row address of each segment of the segmented memory; when the bit corresponding to the segment number in the mask is 0, the row address of the segment remains unchanged;

[0044] (4) Calculate the byte enable of the last data of the output data frame:

[0045] The number of bytes remaining after the Local-Link request data amount is aligned with the bit width of the data bus, and converted to the byte enable of the last data of the data frame through logical right shift;

[0046] (5) Calculate output data:

[0047] The segment enable of the memory places the data in the enabled segment on the output data bus of the Local-Link.

[0048] The Local-Link read request interface in step (1) is defined as follows:

[0049] Read address, the starting address of the read memory;

[0050] Read length, the length of the read memory data, in bytes;

[0051] Read enable, read address valid, start reading;

[0052] The memory empty flag indicates that the memory has been read empty.

[0053] The Local-Link read response interface in step (1) is defined as follows:

[0054] Read data, the data read out has a bit width equal to the bit width of a storage segment;

[0055] Read byte enable, read the byte enable of the last data in the data frame;

[0056] The start signal indicates the first data of the output frame;

[0057] End signal, indicating the last data of the output frame;

[0058] Valid signal, indicating that the output data is valid;

[0059] Ready signal, indicating that the reader is ready to receive data.

[0060] The read mask in step (2) is the result of performing a modulo 2 operation on the high bit of the read start address representing the non-circular segment number, representing the cyclic segment number, and has a value range of [0, segment number - 1].

[0061] Another object of the present invention is to provide a control system for large-bit-width data bus segmented storage that implements the control method for large-bit-width data bus segmented storage, the control system for large-bit-width data bus segmented storage comprising:

[0062] A data address calculation module is used to calculate the starting address and the ending address of each data;

[0063] An inter-bank flag calculation module, used for calculating the inter-bank flag;

[0064] A byte enable calculation module, used for calculating the byte enable of the segmented memory;

[0065] A segment enable calculation module, used for calculating the segment enable of the segmented memory;

[0066] An address calculation module, used for calculating the address of the segment memory;

[0067] The data format calculation module is used to calculate the data format of the segmented memory.

[0068] Another object of the present invention is to provide a computer device, the computer device comprising a memory and a processor, the memory storing a computer program, and when the computer program is executed by the processor, the processor performs the following steps:

[0069] Calculate the starting address and ending address of each data; calculate the cross-row flag; calculate the byte enable of the segmented memory; calculate the segment enable of the segmented memory; calculate the address and data format of the segmented memory.

[0070] Another object of the present invention is to provide a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the following steps:

[0071] Calculate the starting address and ending address of each data; calculate the cross-row flag; calculate the byte enable of the segmented memory; calculate the segment enable of the segmented memory; calculate the address and data format of the segmented memory.

[0072] Another object of the present invention is to provide an information data processing terminal, which is used to implement the control system of the large-bit-width data bus segmented storage.

[0073] In combination with all the above technical solutions, the advantages and positive effects of the present invention are as follows: the control method for segmented storage of a large-bit-width data bus provided by the present invention is composed of a memory and a controller, and a memory is divided into multiple segments for management. The user-side interface of the controller is designed as a convenient Local-Link interface, thereby shielding the internal control logic and mapping rules. The controller automatically allocates storage segment numbers and storage space within the segment according to the data stream information carried by the Local-Link interface, and stores each data in the data stream in a tightly arranged manner, thereby emptying the bubble space in the memory; the present invention is suitable for a large-bit-width data bus. When data needs to be stored on the data bus, the segmented memory can effectively empty the bubble space, so that a frame of data is connected as a whole, which is convenient for the subsequent processing circuit to continuously read the frame of data from the segmented memory without considering the position of each small segment of data in a frame in the storage unit, thereby improving the throughput of the memory; there is no bubble space in the memory, which can improve the utilization rate of the memory.

[0074] Since the present invention empties the bubble space in the memory, the number of times the memory needs to be accessed additionally due to small batches of data is reduced, and each access to the memory is guaranteed to be 100% of the bandwidth, thereby improving the throughput of the memory. Since the present invention empties the bubble space in the memory, there is no memory fragmentation in the memory, and each bit can be used, and the utilization of the memory space is greatly improved. The present invention improves the throughput of storing large-bit-width bus data, ensures that each access to the memory is 100% of the bandwidth, and improves the utilization of the memory storage space. BRIEF DESCRIPTION OF THE DRAWINGS

[0075] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0076] Figure 1 It is a flow chart of a control method for segmented storage of a large bit width data bus provided by an embodiment of the present invention.

[0077] Figure 2 It is a structural block diagram of a control system for large bit width data bus segmented storage provided by an embodiment of the present invention;

[0078] Figure 3 It is a storage structure diagram provided by an embodiment of the present invention.

[0079] Figure 4 It is a segmented memory interface diagram provided by an embodiment of the present invention.

[0080] Figure 5 This is a diagram of a segmented storage controller interface provided by an embodiment of the present invention.

[0081] Figure 6 It is a schematic diagram of a simulation process provided by an embodiment of the present invention.

[0082] Figure 7 It is the data of the simulated write operation provided by the embodiment of the present invention.

[0083] Figure 8 The data of the simulated read operation provided by the embodiment of the present invention is.

[0084] In the figure: 1. Data address calculation module; 2. Cross-row flag calculation module; 3. Byte enable calculation module; 4. Segment enable calculation module; 5. Address calculation module; 6. Data format calculation module. DETAILED DESCRIPTION

[0085] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0086] In view of the problems existing in the prior art, the present invention provides a control method, system, device and medium for large-bit-width data bus segmented storage. The present invention is described in detail below in conjunction with the accompanying drawings.

[0087] like Figure 1 As shown, the control method for large bit width data bus segment storage provided by the embodiment of the present invention includes the following steps:

[0088] S101, calculating the starting address and ending address of each data;

[0089] S102, calculating a cross-row flag;

[0090] S103, calculating the byte enable of the segmented memory;

[0091] S104, calculating the segment enable of the segmented memory;

[0092] S105, calculating the address of the segment memory;

[0093] S106, calculating the data format of the segment memory.

[0094] like Figure 2 As shown, the control system for large bit width data bus segmented storage provided by the embodiment of the present invention includes:

[0095] Data address calculation module 1, used to calculate the starting address and ending address of each data;

[0096] An inter-bank sign calculation module 2, used for calculating the inter-bank sign;

[0097] A byte enable calculation module 3, used for calculating the byte enable of the segmented memory;

[0098] A segment enable calculation module 4, used for calculating the segment enable of the segmented memory;

[0099] An address calculation module 5, used for calculating the address of the segment memory;

[0100] The data format calculation module 6 is used to calculate the data format of the segment memory.

[0101] The technical solution of the present invention is further described below in conjunction with specific embodiments.

[0102] The present invention relates to a control method for large-bit-width data bus segment storage, which is used to manage a piece of memory in segments to empty the bubble space in the memory, improve the memory throughput, and enhance the utilization rate of the memory space. Figure 3 shown.

[0103] Reference Figure 3 , Taking the division of the memory into two segments as an example, the data bus width of the memory is twice the input data width. Each time a write operation is performed on the memory, the storage segment number and the storage space within the segment are automatically allocated according to the write position and the length of the written data, and each data in the data stream is stored in a tightly arranged manner to empty the bubble space in the memory.

[0104] like Figure 3 Example in:

[0105] The effective length of the first data is less than the bit width of a storage segment, so it is stored in the low bit of the 0th row of the 0th segment.

[0106] The effective length of the second data is greater than the remaining length of the 0th segment, resulting in a cross-segment phenomenon. The low bit of the data is stored at the end of the 0th segment, close to the end position of the first data, and the high bit of the data is stored in the low bit of the 0th row of the 0th segment.

[0107] The effective length of the third data is greater than the remaining length of the first segment, and the first segment is the last segment of the 0th row, resulting in a cross-row phenomenon. The low bit of the data is stored at the end of the first segment close to the end position of the second data, and the high bit of the data is stored in the low bit of the 0th segment of the 1st row.

[0108] The fourth data is stored similarly to the second data.

[0109] The effective length of the fifth data is less than the length of the remaining space of the first line of the first paragraph, and the data is stored close to the end position of the fourth data.

[0110] Reference Figure 4 , the interface definition and functions of the segmented memory are as follows:

[0111] (1) Write port:

[0112] wr_cmd_data, the data bus of the segmented memory, has a bit width equal to the product of the number of segments and the data bit width of a single memory segment.

[0113] wr_cmd_addr, the address bus of the segmented memory, has a bit width equal to the product of the number of segments and the bit width of a single storage segment address; starting from the 0th bit, each n-bit wide address is used to index the number of rows in the corresponding segment, where n is the bit width of a single storage segment address.

[0114] wr_cmd_be, the byte mask of the segmented memory, the bit width is the product of the number of segments and the bit width of the byte mask of a single memory segment; starting from the 0th bit, each byte mask with a width of n bits is used to enable the data in the corresponding segment in units of bytes.

[0115] wr_cmd_valid, the write valid signal of the segmented memory, has a bit width equal to the number of segments. Each bit corresponds to a segment number and is used to enable the write function of the corresponding segment.

[0116] wr_cmd_ready, the write-ready signal of the segmented memory, has a bit width equal to the number of segments. Each bit corresponds to a segment number, indicating that the corresponding segment of the memory is not full.

[0117] wr_done, the write completion signal of the segmented memory, has a bit width equal to the number of segments. Each bit corresponds to a segment number, indicating whether the write operation of the corresponding segment is successful.

[0118] (2) Read request port:

[0119] rd_cmd_addr, the read address bus of the segmented memory, the bit width is the product of the number of segments and the bit width of a single memory segment address;

[0120] rd_cmd_valid, the read enable signal of the segmented memory, has a bit width equal to the number of segments. Each bit corresponds to a segment number and is used to enable the read operation of the corresponding segment.

[0121] rd_cmd_ready, the read ready signal of the segmented memory, the bit width is equal to the number of segments, each bit corresponds to the segment number, indicating that the corresponding segment of the memory is not empty.

[0122] (3) Read response port:

[0123] rd_resp_data, the read data bus of the segmented memory, has a bit width equal to the product of the number of segments and the data bit width of a single memory segment.

[0124] rd_resp_valid, the read data valid signal of the segmented memory, the bit width is equal to the number of segments, each bit corresponds to a segment number, and identifies the source segment number of the valid data.

[0125] rd_resp_ready, the data acquisition preparation signal of the reading device, the bit width is equal to the number of segments, each bit corresponds to a segment number, indicating that the reading device can obtain the data output from the corresponding segment.

[0126] Reference Figure 5 , the interface definition and functions of the segmented memory controller are as follows:

[0127] (1) Write port:

[0128] wr_data, Local-Link write data bus, the bit width is equal to the data bit width of a single storage segment.

[0129] wr_addr, Local-Link write address bus, the storage unit size represented by each address is 1 byte.

[0130] wr_lst_b, Local-Link byte is valid, identifies the last valid byte of the last data in a frame of data.

[0131] wr_sop, Local-Link frame start signal, identifies the first data of a frame.

[0132] wr_eop, Local-Link frame end signal, identifies the last data of a frame.

[0133] wr_valid, Local-Link write valid signal, the signal is pulled high to indicate that the write data is valid.

[0134] wr_ready, Local-Link write ready signal, the signal is pulled high to indicate that the RAM is writable.

[0135] (2) Read request port:

[0136] rd_addr, Local-Link read address bus, identifies the first address of the read data frame, and the storage unit size represented by the address is 1 byte.

[0137] rd_len, the length of the data frame read by Local-Link, in bytes.

[0138] rd_en, Local-Link read address is valid, and the signal is pulled high to start the reading process.

[0139] rd_empty, Local-Link read empty flag, the signal is pulled high to indicate that the RAM is read empty.

[0140] (3) Read response port:

[0141] rd_data, Local-Link read data bus, the bit width is equal to the data bit width of a single storage segment.

[0142] rd_be, Local-Link byte valid, identifies the validity of the last byte of data in a frame of data.

[0143] rd_sop, Local-Link frame start signal, identifies the first data of a frame.

[0144] rd_eop, Local-Link frame end signal, identifies the last data of a frame.

[0145] rd_valid, Local-Link read data valid signal, the signal is pulled high to indicate that the data on the read data bus is valid.

[0146] rd_ready, Local-Link read device ready signal. When the signal is pulled high, it means that the read device is ready to receive data on the read data bus.

[0147] The process of initiating a write operation on the Local-Link interface of the segmented memory controller and mapping it to the control of the segmented memory interface is as follows:

[0148] (1) Calculate the starting address and ending address of each data:

[0149] When storing a non-last data in a data stream, the address input by the Local-Link write interface is used as the starting address, and the width of the Local-Link data bus is accumulated in bytes each time as the starting address of the data. The starting address in bytes plus the width of the data bus is used as the ending address; when storing the last data in a data stream, the starting address of the previous data is used as the reference, and the width of the data bus is added in bytes as the starting address, and the starting address plus the number of valid bytes of the last data in a data stream is used as the ending address; when storing a single data frame, the starting address is the address input by the Local-Link write interface, and the starting address plus the number of valid bytes of this data is used as the ending address;

[0150] (2) Calculate the cross-line flag:

[0151] Use logical right shift to divide the starting address in bytes by the data bit width of all storage segments, and the result is the row number of the memory where the starting address is located; use logical right shift to divide the ending address in bytes by the data bit width of all storage segments, and the result is the row number of the memory where the ending address is located; compare the two results, if they are consistent, the data stored this time does not cross rows, otherwise the data that crosses rows will be processed;

[0152] (3) Calculate the byte enable of the segmented memory:

[0153] If the stored data does not cross rows, shift all the sequences with bits set to 1 to the left by the low bit of the starting address to obtain the byte enable from the perspective of the starting address, and shift all the sequences with bits set to 1 to the right by the complement of the low bit of the ending address to obtain the byte enable from the perspective of the ending address. Perform bitwise AND of the byte enable from the perspective of the starting address and the byte enable from the perspective of the ending address to obtain the byte enable used in the segmented memory for this data; if the stored data crosses rows, perform bitwise OR of the byte enable from the perspective of the starting address and the byte enable from the perspective of the ending address to obtain the byte enable used in the segmented memory for this data;

[0154] (4) Calculate the segment enable of the segmented memory:

[0155] Divide the byte enable by storage segment. If all the byte enables of the storage segment are 0, the segment enable of the storage segment is cleared; if the byte enable of the storage segment is not 0, the segment enable of the storage segment is set.

[0156] (5) Calculate the address of the segmented memory:

[0157] If the stored data does not cross rows, take the high bit of the storage row number expressed by the starting address and use it as the row address of each segment of the segmented memory; if the stored data crosses rows, add 1 to the original row address of the storage segment with segment number 0, and the calculation method of the row addresses of the remaining segments remains unchanged;

[0158] (6) Calculate the data format of the segmented memory:

[0159] Copy the data into the number of segments plus 1 and splice them into one data. Take the low bit of the starting address to represent the offset of the starting address in a storage segment. Perform a logical right shift operation on the spliced ​​data according to the offset. Align the 0 bit of one of the data segments in the spliced ​​data with the position of the starting address.

[0160] The process of initiating a read request operation on the Local-Link interface of the segmented memory controller and mapping it to the control of the segmented memory interface is as follows:

[0161] (1) Calculate the read start address of each data:

[0162] When reading the first data in a frame of data stream, the address input by the Local-Link read interface is used as the read start address; when reading data other than the first data in a frame of data stream, the read start address is the address input by the Local-Link read interface plus the bit width of a single storage segment in bytes;

[0163] (2) Calculate the segment enable of the segmented memory:

[0164] The segment enable of the segmented memory is consistent with the value of the read mask;

[0165] (3) Calculate the address of the segmented memory:

[0166] When the bit corresponding to the segment number in the mask is 1, the high bit of the storage row number expressed by the start address is taken and used as the row address of each segment of the segmented memory; when the bit corresponding to the segment number in the mask is 0, the row address of the segment remains unchanged;

[0167] The process of mapping the read response of the segmented memory interface to the Local-Link interface of the segmented memory controller is as follows:

[0168] (1) Calculate the byte enable of the last data of the output data frame:

[0169] The number of bytes remaining after the Local-Link request data amount is aligned with the bit width of the data bus, and converted to the byte enable of the last data of the data frame through logical right shift;

[0170] (2) Calculate output data:

[0171] The memory segment enables the data in the enabled segment to be placed on the output data bus of the Local-Link;

[0172] (3) Mapping of output data valid signal:

[0173] As long as one bit of the segment memory output data valid signal rd_resp_valid is non-zero and the read device ready to receive signal rd_ready is valid, the output data valid signal rd_valid of the Local-Link interface is pulled high;

[0174] (4) Control of output data frame start signal:

[0175] The counter read_cycle_num_cnt is incremented by 1 each time the segment memory outputs a valid data. When the value of the counter read_cycle_num_cnt is 1 and the output data valid signal rd_valid of the Local-Link interface is pulled high, it means that the Local-Link interface is outputting the first data of this frame, and the Local-Link interface output data frame start signal rd_sop is pulled high.

[0176] (5) Control of output data frame end signal:

[0177] The register read_cycle_num stores the data of the read frame length signal rd_len of the Local-Link interface. When the value of the counter read_cycle_num_cnt is equal to the value in the register read_cycle_num, it means that the Local-Link interface is outputting the last data of this frame, and the Local-Link interface outputs the data frame end signal rd_eop high.

[0178] The technical effects of the present invention are described in detail below in conjunction with simulation.

[0179] like Figure 6 As shown, the simulation process of the present invention includes:

[0180] Set the parameters of the segmented memory controller to Local-Link data bus width 128 bits and Local-Link address bus width 13 bits; set the number of segments of the segmented memory to 2.

[0181] The data frame is written to the segmented storage controller through the Local-Link interface, and the segmented storage controller maps the Local-Link data frame into a segmented storage format and stores it in the segmented memory.

[0182] The data frame is read from the segment memory controller through the Local-Link interface, and the data frame read from the segment memory is mapped to Local-Link by the segment memory controller and then output.

[0183] The simulation results of the present invention are as follows: Write data simulation:

[0184] The first frame data of the segmented memory controller is written from the Local-Link interface wr_data to address 0, which is 8 bytes of hexadecimal data 0x0000000012153524; after mapping, it is stored in the lower 64 bits of the 0th segment and the 0th row of the segmented memory through the segmented memory interface wr_cmd_data.

[0185] The second frame data written from the Local-Link interface wr_data to the segmented memory controller at address 8 consists of 4 data, of which the first 3 data are 16 bytes each, and the fourth data is marked as the lower 1 byte by wr_lst_b, and a total of 49 bytes are written; after mapping, it is stored in the segmented memory from address 8 through the segmented memory interface wr_cmd_data without bubbles.

[0186] The third frame data written from the Local-Link interface wr_data to the segmented memory controller at address 8 consists of 2 data, of which the first data is 16 bytes and the second data is marked as the lower 8 bytes by wr_lst_b, for a total of 24 bytes. After mapping, it is stored in the segmented memory from address 57 through the segmented memory interface wr_cmd_data without bubbles.

[0187] The above three write operations write a total of 81 bytes.

[0188] Read data simulation:

[0189] The read start address rd_addr is 0 and the data length rd_len is 81 bytes from the Local-Link read request end. After the read is started, it is mapped and read continuously from address 0 for 6 times. The valid data amount of each of the first 5 times is 16 bytes, and the valid data amount of the 6th time is 1 byte, totaling 81 bytes.

[0190] Comparison of reading and writing results:

[0191] like Figure 7 As shown, the data of this simulation write operation is:

[0192] The first data is the lower 8 bytes, the second, third, and fourth data are all 16 bytes, the fifth data is the lower 1 byte, the sixth data is 16 bytes, and the seventh data is the lower 8 bytes.

[0193] like Figure 8As shown, the data of this simulated read operation is:

[0194] The 1st, 2nd, 3rd, 4th and 5th data are all 16 bytes, and the 6th data is the lower byte.

[0195] through Figure 7 and Figure 8 Data comparison shows that the data frame with bubbles written at the Local-Link end is converted into bubble-free storage in the segmented memory after being mapped by the segmented memory controller, and the data read from the Local-Link end is the data after the bubbles are removed from the segmented memory.

[0196] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When the use is implemented in whole or in part in the form of a computer program product, the computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL) or wireless (e.g., infrared, wireless, microwave, etc.) mode) to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk (SSD)), etc.

[0197] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principle of the present invention should be covered by the protection scope of the present invention.

Claims

1. A control method for large bit width data bus segment storage, characterized in that: The control method for the segmented storage of a large-bit-width data bus is composed of a memory and a controller, and a memory is divided into multiple segments for management. The user-side interface of the controller is designed as a convenient Local-Link interface, thereby shielding the internal control logic and mapping rules. The controller automatically allocates the storage segment number and the storage space within the segment according to the data flow information carried by the Local-Link interface, and stores each data in the data flow in a tightly arranged manner, thereby emptying the bubble space in the memory; The control method for large bit width data bus segment storage comprises the following steps: Step 1, calculate the starting address and ending address of each data; Step 2, calculating the cross-line flag; Step 3, calculating the byte enable of the segmented memory; Step 4, calculating the segment enable of the segmented memory; Step 5, calculating the address of the segmented memory; Step 6, calculating the data format of the segmented memory; The calculation of the starting address and the ending address of each data in step 1 includes: When storing a non-last data in a data stream, the address input by the Local-Link write interface is used as the starting address, and the width of the Local-Link data bus is accumulated in bytes each time as the starting address of the data. The starting address in bytes plus the width of the data bus is used as the ending address; when storing the last data in a data stream, the starting address of the previous data is used as the reference, and the width of the data bus is added in bytes as the starting address, and the starting address plus the number of valid bytes of the last data in a data stream is used as the ending address; when storing a single data frame, the starting address is the address input by the Local-Link write interface, and the starting address plus the number of valid bytes of this data is used as the ending address; The Local-Link write interface is defined as follows: Data bus, the bit width is the same as the bit width of a memory segment; The address bus has a bit width equal to the sum of the address bit width of a segment of the segment memory and the logarithm of the bit width of all segment bytes of the segment memory with base 2; Byte is valid, indicating the last valid byte of the last data in a frame; The start signal indicates the first data of a frame; End signal, indicating the last data of a frame; Valid signal, indicating that all signals transmitted on the bus are valid; Ready signal, indicating that the RAM is not full; The calculation of the cross-row flag in step 2 includes: using a logical right shift to divide the starting address in bytes by the data bit width of all storage segments, and the result is the row number of the memory where the starting address is located; using a logical right shift to divide the ending address in bytes by the data bit width of all storage segments, and the result is the row number of the memory where the ending address is located; comparing the two results, if they are consistent, the data stored this time does not cross rows, otherwise the data of the cross-row part will be processed; The read operation of the controller for large bit width data bus segment storage includes: (1) Calculate the read start address of each data: When reading the first data in a frame of data stream, the address input by the Local-Link read interface is used as the read start address; when reading data other than the first data in a frame of data stream, the read start address is the address input by the Local-Link read interface plus the bit width of a single storage segment in bytes; (2) Calculate the segment enable of the segmented memory: the segment enable of the segmented memory is consistent with the value of the read mask; (3) Calculate the address of the segmented memory: When the bit corresponding to the segment number in the mask is 1, take the high bit of the storage row number expressed by the starting address and use it as the row address of each segment of the segmented memory; when the bit corresponding to the segment number in the mask is 0, the row address of the segment remains unchanged; (4) Calculate the byte enable of the last data in the output data frame: Calculate the number of bytes remaining after alignment with the bit width of the data bus based on the Local-Link request data quantity, and convert it into the byte enable of the last data in the data frame through logical right shift; (5) Calculate output data: The memory segment enables the data in the enabled segment to the output data bus of the Local-Link; The Local-Link read request interface in step (1) is defined as follows: Read address, the starting address of the read memory; Read length, the length of the read memory data, in bytes; Read enable, read address valid, start reading; The memory empty flag indicates that the memory has been read empty; The Local-Link read response interface in step (1) is defined as follows: Read data, the data read out has a bit width equal to the bit width of a storage segment; Read byte enable, read the byte enable of the last data in the data frame; The start signal indicates the first data of the output frame; End signal, indicating the last data of the output frame; Valid signal, indicating that the output data is valid; Ready signal, indicating that the reader is ready to receive data; The read mask in step (2) is the result of performing a modulo 2 operation on the high bit of the read start address that represents the non-circular segment number, and represents the cyclic segment number, and its value range is [0, segment number - 1].

2. The control method for large bit width data bus segment storage according to claim 1, characterized in that: The calculation of the byte enable of the segmented memory in the step 3 includes: if the stored data does not cross rows, shifting the sequence with all bits as 1 to the left by the low bit of the starting address to obtain the byte enable from the perspective of the starting address, and shifting the sequence with all bits as 1 to the right by the complement of the low bit of the ending address to obtain the byte enable from the perspective of the ending address; performing bitwise AND on the byte enable from the perspective of the starting address and the byte enable from the perspective of the ending address to obtain the byte enable used in the segmented memory for the current data; if the stored data crosses rows, performing bitwise OR on the byte enable from the perspective of the starting address and the byte enable from the perspective of the ending address to obtain the byte enable used in the segmented memory for the current data.

3. The control method for large bit width data bus segment storage according to claim 1, characterized in that: The segment enable of the calculation segment memory in step 4 includes: Divide the byte enable by storage segment. If all the byte enables of the storage segment are 0, the segment enable of the storage segment is cleared; if the byte enable of the storage segment is not 0, the segment enable of the storage segment is set. The address of the segment memory calculated in step 5 includes: If the stored data does not cross rows, take the high bit of the storage row number expressed by the starting address and use it as the row address of each segment of the segmented memory; if the stored data crosses rows, add 1 to the original row address of the storage segment with segment number 0, and the calculation method of the row addresses of the remaining segments remains unchanged; The data format of the calculated segmented memory in step six includes: copying the data into the number of segments plus 1 and splicing them into one data, taking the low bit of the starting address to represent the offset of the starting address in a storage segment, performing a logical right shift operation on the spliced ​​data according to the offset, and aligning the 0 bit of one of the data segments in the spliced ​​data with the position of the starting address.

4. A control system for large bit width data bus segmented storage implementing the control method for large bit width data bus segmented storage according to any one of claims 1 to 3, characterized in that: The control system of the large bit width data bus segmented storage includes: A data address calculation module is used to calculate the starting address and the ending address of each data; An inter-bank flag calculation module, used for calculating the inter-bank flag; A byte enable calculation module, used for calculating the byte enable of the segmented memory; A segment enable calculation module, used for calculating the segment enable of the segmented memory; An address calculation module, used for calculating the address of the segment memory; The data format calculation module is used to calculate the data format of the segmented memory.

5. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and when the computer program is executed by the processor, the processor executes the steps of the control method for large-bit-width data bus segmented storage as described in any one of claims 1 to 3.

6. A computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the processor executes the steps of the control method for large-bit-width data bus segmented storage according to any one of claims 1 to 3.

7. An information data processing terminal, characterized in that: The information data processing terminal is used to implement the control system of large bit width data bus segmented storage as claimed in claim 4.

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