Circuit board, circuit board manufacturing method and electronic equipment

Abstract

The embodiments of the present application provide a circuit board, a circuit board manufacturing method and an electronic device. The circuit board is provided with at least one blind hole formed on a second conductive layer and a first dielectric layer, the opening of the blind hole is located on the second conductive layer, a third conductive layer is arranged in the blind hole, and the first conductive layer as the surface layer of the circuit board is connected to the second conductive layer through the third conductive layer, thereby avoiding the problem of increased thickness and poor flatness of the surface copper layer of the circuit board, such as the first conductive layer, in the prior art.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of circuit boards, and in particular to a circuit board, a method for manufacturing a circuit board, and an electronic device. Background Art

[0002] With the continuous development of communication technology, electronic products are gradually transitioning towards the direction of being lighter, thinner and smaller. As the basic component of electronic products, circuit boards are given more functions. In order to achieve the conduction between the surface circuits and the inner circuits of the circuit board, blind holes are usually set on the circuit board.

[0003] In the prior art, when setting a blind hole on a circuit board, a laser drilling method is usually used to first form a blind hole on the surface of the circuit board. The blind hole needs to penetrate the surface copper layer of the circuit board and the dielectric layer between the surface copper layer and the inner copper layer of the circuit board. Then, the blind hole formed above is electroplated and filled, wherein the electroplating material is copper. During the electroplating and filling process, the thickness of the surface copper layer of the circuit board will increase, and the flatness of the surface copper layer will deteriorate. In order to reduce the thickness of the surface copper layer of the circuit board, chemical etching or physical flattening methods are generally used to remove excess copper on the surface copper layer of the circuit board to reduce the thickness of the surface copper layer of the circuit board.

[0004] However, the thickness of the surface copper layer of the above circuit board will still increase to a certain extent, and the problem of poor flatness of the surface copper layer cannot be improved. Summary of the invention

[0005] The embodiments of the present application provide a circuit board, a circuit board manufacturing method and an electronic device, which can avoid the problem of increased thickness and poor flatness of the surface copper layer of the circuit board in the prior art.

[0006] A first aspect of an embodiment of the present application provides a circuit board, which at least includes: a first conductive layer, a second conductive layer, and a first dielectric layer located between the first conductive layer and the second conductive layer, which are stacked; at least one blind hole is formed on the second conductive layer and the first dielectric layer, and the opening of the blind hole is located on the second conductive layer; a third conductive layer is arranged in the blind hole, and the first conductive layer is conductively connected to the second conductive layer through the third conductive layer; wherein the first conductive layer serves as the surface layer of the circuit board.

[0007] The circuit board provided in the embodiment of the present application forms at least one blind hole on the second conductive layer and the first dielectric layer, the opening of the blind hole is located on the second conductive layer, a third conductive layer is arranged in the blind hole, and the first conductive layer as the surface layer of the circuit board is connected to the second conductive layer through the third conductive layer, which can avoid the problem of increased thickness and poor flatness of the surface copper layer of the circuit board in the prior art. In addition, compared with the prior art in which the blind hole is formed on the first conductive layer and the first dielectric layer as the surface layer of the circuit board, and the opening of the blind hole is located on the surface layer of the circuit board, it can avoid the presence of a depression at the opening of the blind hole, which affects the appearance of the first conductive layer, i.e., the surface layer of the circuit board.

[0008] In a possible implementation manner, the method further includes: a second dielectric layer; the second conductive layer is located between the first dielectric layer and the second dielectric layer, and a side of the second dielectric layer close to the second conductive layer is in contact with the opening of the blind hole.

[0009] One side of the second dielectric layer close to the second conductive layer is in contact with the opening of the blind hole. If there is a depression at the opening of the blind hole on the second conductive layer, the depression can be hidden between the second conductive layer and the second dielectric layer. In addition, during the lamination process of the second conductive layer and the second dielectric layer, the second dielectric layer can also fill the depression to a certain extent.

[0010] In a possible implementation, the present invention further includes: a fourth conductive layer, a fifth conductive layer, and a third dielectric layer located between the fourth conductive layer and the fifth conductive layer; the fourth conductive layer is located between the second dielectric layer and the third dielectric layer; at least one blind hole is formed on the fourth conductive layer and the third dielectric layer, and the opening of the blind hole is located on the fourth conductive layer; the third conductive layer is arranged in the blind hole, and the fourth conductive layer is conductively connected to the fifth conductive layer through the third conductive layer.

[0011] By forming at least one blind hole on the fourth conductive layer and the third dielectric layer, the opening of the blind hole is located on the fourth conductive layer, the third conductive layer is arranged in the blind hole, and the fifth conductive layer as the surface layer of the circuit board is connected to the fourth conductive layer through the third conductive layer, the problem of increased thickness and poor flatness of the surface copper layer of the circuit board in the prior art can be avoided. In addition, compared with the prior art in which the blind hole is formed on the fifth conductive layer and the third dielectric layer as the surface layer of the circuit board, and the opening of the blind hole is located on the surface layer of the circuit board, it is possible to avoid the presence of a depression at the opening of the blind hole, which affects the appearance of the fifth conductive layer, i.e., the surface layer of the circuit board.

[0012] In a possible implementation, it further includes: at least one intermediate layer, the at least one intermediate layer is located between the second dielectric layer and the fourth conductive layer; or, the at least one intermediate layer is located between the second dielectric layer and the second conductive layer; the intermediate layer includes a conductive layer and a dielectric layer, and the conductive layer and the dielectric layer in the at least one intermediate layer are alternately stacked.

[0013] In a possible implementation, the third conductive layer is disposed on the inner wall of the blind hole. By disposing the third conductive layer on the inner wall of the blind hole, current conduction and signal transmission can be achieved between the first conductive layer and the second conductive layer through the third conductive layer. Similarly, current conduction and signal transmission can be achieved between the fourth conductive layer and the fifth conductive layer through the third conductive layer. In addition, not completely filling the blind hole can save electroplating costs to a certain extent and improve work efficiency.

[0014] In a possible implementation, the blind holes are filled with the third conductive layer. By filling the blind holes with the third conductive layer, the conduction path between the first conductive layer and the second conductive layer is increased, so that the flow capacity of the via hole is stronger. Similarly, the conduction path between the fourth conductive layer and the fifth conductive layer is increased, so that the flow capacity of the via hole is stronger.

[0015] In a possible implementation, the inner diameter of the blind hole gradually decreases in the direction from the opening of the blind hole to the bottom wall of the blind hole. In this way, the inner diameter of the blind hole near the first conductive layer is relatively small, and when the corresponding pad is arranged on the first conductive layer, the size of the pad can be reduced, thereby increasing the number of pads arranged on the circuit board of the same size and improving the density of the pads.

[0016] In a possible implementation manner, the inner wall of the blind hole is a planar structure.

[0017] In a possible implementation, the inner wall of the blind hole is a stepped structure. By designing the inner wall of the blind hole to be a stepped structure, if the inner diameter of the blind hole near the first conductive layer is kept consistent, the inner diameter of the blind hole with a stepped structure away from the first conductive layer, that is, the inner diameter of the blind hole at the opening is larger than that of the blind hole with a planar structure, thereby improving the flow capacity inside the blind hole to a certain extent. If the inner diameter of the blind hole away from the first conductive layer, that is, the inner diameter of the blind hole at the opening is kept consistent, the inner diameter of the blind hole with a stepped structure near the first conductive layer is smaller than that of the blind hole with a planar structure, and when the corresponding pad is set on the first conductive layer, the size of the pad can be reduced, thereby increasing the number of pads set on a circuit board of the same size and improving the density of the pad.

[0018] A second aspect of an embodiment of the present application provides an electronic device, comprising at least: the circuit board described above.

[0019] The electronic device provided by the embodiment of the present application comprises at least a circuit board, wherein the circuit board is provided with at least one blind hole formed on the second conductive layer and the first dielectric layer, the opening of the blind hole is located on the second conductive layer, a third conductive layer is arranged in the blind hole, and the first conductive layer as the surface layer of the circuit board is connected with the second conductive layer through the third conductive layer, which can avoid the problem of increased thickness and poor flatness of the surface copper layer of the circuit board in the prior art. In addition, compared with the prior art in which blind holes are formed on the first conductive layer and the first dielectric layer as the surface layer of the circuit board, and the opening of the blind hole is located on the surface layer of the circuit board, it is possible to avoid depressions at the opening of the blind hole, which affects the appearance of the first conductive layer, i.e., the surface layer of the circuit board. In addition, by arranging the above-mentioned circuit board in the electronic device, the experience effect of the electronic device can be optimized. At the same time, the stability of signal transmission in the electronic device is also guaranteed, ensuring the normal operation of the electronic device.

[0020] A third aspect of an embodiment of the present application provides a method for manufacturing a circuit board, the method comprising: providing at least a first conductive layer, a first dielectric layer, and a second conductive layer that are stacked, the first dielectric layer being located on the second conductive layer, and the first conductive layer being located on the first dielectric layer; forming blind holes on the first dielectric layer and the second conductive layer, the openings of the blind holes being located on the second conductive layer; arranging a third conductive layer in the blind holes so that the first conductive layer is electrically connected to the second conductive layer through the third conductive layer; wherein the first conductive layer serves as the surface layer of the circuit board.

[0021] The circuit board manufacturing method provided in the embodiment of the present application forms at least one blind hole on the second conductive layer and the first dielectric layer, the opening of the blind hole is located on the second conductive layer, a third conductive layer is arranged in the blind hole, and the first conductive layer as the surface layer of the circuit board is connected to the second conductive layer through the third conductive layer, which can avoid the problem of increased thickness and poor flatness of the surface copper layer of the circuit board in the prior art. In addition, compared with the prior art in which the blind hole is formed on the first conductive layer and the first dielectric layer as the surface layer of the circuit board, and the opening of the blind hole is located on the surface layer of the circuit board, it can avoid the presence of depressions at the opening of the blind hole, which affects the appearance of the first conductive layer, i.e., the surface layer of the circuit board.

[0022] In a possible implementation, after the third conductive layer is provided in the blind hole, the method further includes: providing a second dielectric layer on a side of the second conductive layer facing away from the first dielectric layer; wherein a side of the second dielectric layer close to the second conductive layer is in contact with the opening of the blind hole.

[0023] By contacting the side of the second dielectric layer close to the second conductive layer with the opening of the blind hole, if there is a depression at the opening of the blind hole on the second conductive layer, the depression can be hidden between the second conductive layer and the second dielectric layer, and during the lamination process of the second conductive layer and the second dielectric layer, the second dielectric layer can also fill the depression to a certain extent.

[0024] In a possible implementation, the method further includes: providing a fourth conductive layer, a third dielectric layer, and a fifth conductive layer that are stacked, wherein the third dielectric layer is located on the fifth conductive layer, and the fourth conductive layer is located on the third dielectric layer; forming blind holes on the third dielectric layer and the fourth conductive layer, wherein the openings of the blind holes are located on the fourth conductive layer; and arranging the third conductive layer in the blind holes so that the fifth conductive layer is electrically connected to the fourth conductive layer through the third conductive layer.

[0025] By forming at least one blind hole on the fourth conductive layer and the third dielectric layer, the opening of the blind hole is located on the fourth conductive layer, the third conductive layer is arranged in the blind hole, and the fifth conductive layer as the surface layer of the circuit board is connected to the fourth conductive layer through the third conductive layer, the problem of increased thickness and poor flatness of the surface copper layer of the circuit board in the prior art can be avoided. In addition, compared with the prior art in which the blind hole is formed on the fifth conductive layer and the third dielectric layer as the surface layer of the circuit board, and the opening of the blind hole is located on the surface layer of the circuit board, it is possible to avoid the presence of a depression at the opening of the blind hole, which affects the appearance of the fifth conductive layer, i.e., the surface layer of the circuit board.

[0026] In a possible implementation manner, the second dielectric layer is located between the fourth conductive layer and the second conductive layer; wherein a side of the second dielectric layer close to the fourth conductive layer is in contact with an opening of the blind hole on the fourth conductive layer.

[0027] By contacting the opening of the blind hole with one side of the second dielectric layer close to the fourth conductive layer, if there is a depression at the opening of the blind hole on the fourth conductive layer, the depression can be hidden between the fourth conductive layer and the second dielectric layer, and during the lamination process of the fourth conductive layer and the second dielectric layer, the second dielectric layer can also fill the depression to a certain extent.

[0028] In a possible implementation, the method further includes: providing at least one intermediate layer; arranging the at least one intermediate layer between the second dielectric layer and the fourth conductive layer; or arranging the at least one intermediate layer between the second dielectric layer and the second conductive layer; wherein the intermediate layer includes a conductive layer and a dielectric layer, and the conductive layer and the dielectric layer in the at least one intermediate layer are alternately stacked.

[0029] In a possible implementation, a blind hole is formed on the first dielectric layer and the second conductive layer, and an opening of the blind hole is located on the second conductive layer, including: processing the blind hole from a side of the second conductive layer away from the first dielectric layer toward a side of the first dielectric layer close to the first conductive layer, so that the opening of the blind hole is located on the second conductive layer.

[0030] In a possible implementation, the third conductive layer is provided in the blind hole, comprising: providing the third conductive layer in the blind hole by using a single-sided electroplating process. By using the single-sided electroplating process, it is possible to avoid processing the other side of the circuit board opposite to the blind hole during electroplating, thereby reducing the electroplating cost and improving work efficiency to a certain extent.

[0031] In a possible implementation, the step of providing the third conductive layer in the blind hole by using a single-sided electroplating process includes: providing the third conductive layer on the inner wall of the blind hole of the second conductive layer by using a single-sided electroplating process. By providing the third conductive layer on the inner wall of the blind hole, current conduction and signal transmission can be achieved between the first conductive layer and the second conductive layer through the third conductive layer. Similarly, current conduction and signal transmission can be achieved between the fourth conductive layer and the fifth conductive layer through the third conductive layer.

[0032] In a possible implementation, the third conductive layer is provided in the blind hole by using a single-sided electroplating process, including: the third conductive layer is filled in the blind hole of the second conductive layer by using a single-sided electroplating process. By filling the blind hole with the third conductive layer, the conduction path between the first conductive layer and the second conductive layer is increased, so that the flow capacity of the via hole is stronger. Similarly, the conduction path between the fourth conductive layer and the fifth conductive layer is increased, so that the flow capacity of the via hole is stronger.

[0033] In a possible implementation, a blind hole is formed on the third dielectric layer and the fourth conductive layer, and an opening of the blind hole is located on the fourth conductive layer, including: processing the blind hole from a side of the fourth conductive layer away from the third dielectric layer toward a side of the third dielectric layer close to the fifth conductive layer, so that the opening of the blind hole is located on the fourth conductive layer.

[0034] These and other aspects, implementation forms and advantages of the exemplary embodiments will become apparent from the embodiments described below in conjunction with the accompanying drawings. However, it should be understood that the description and the accompanying drawings are only for illustration and are not intended to be a definition of limitations on the embodiments of the present application, as described in the accompanying claims. Other aspects and advantages of the embodiments of the present application will be described in the following description, and some will be apparent from the description or will be learned through the practice of the embodiments of the present application. In addition, the various aspects and advantages of the embodiments of the present application can be achieved and obtained by the means and combinations specifically indicated in the attached claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0036] Figure 2 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0037] Figure 3 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0038] Figure 4 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0039] Figure 5 A schematic diagram of the structure of a circuit board and a chip connected in accordance with an embodiment of the present application;

[0040] Figure 6 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0041] Figure 7 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0042] Figure 8 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0043] Fig. 9 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0044] Fig.10 A schematic diagram of the structure of a circuit board provided in one embodiment of the present application;

[0045] Fig.11 A schematic diagram of a process flow of a circuit board manufacturing method provided in one embodiment of the present application;

[0046] Fig.12 A schematic diagram of a process flow of a circuit board manufacturing method provided in one embodiment of the present application;

[0047] Fig.13a A schematic diagram of the structure of a first conductive layer, a second conductive layer and a first dielectric layer in a circuit board manufacturing method provided in an embodiment of the present application;

[0048] Fig.13b A schematic diagram of a structure in which blind holes are formed on a first dielectric layer and a second conductive layer in a circuit board manufacturing method provided in an embodiment of the present application;

[0049] Fig.13c A schematic diagram of a structure in which a third conductive layer is provided in a blind hole in a circuit board manufacturing method provided in an embodiment of the present application;

[0050] Fig.14a A schematic diagram of the structure of a first conductive layer, a first dielectric layer and a second conductive layer, a second dielectric layer and a fourth conductive layer, a third dielectric layer and a fifth conductive layer in a circuit board manufacturing method provided in an embodiment of the present application;

[0051] Fig.14b A schematic diagram of a structure in which blind holes are formed on a first dielectric layer and a second conductive layer in a circuit board manufacturing method provided in an embodiment of the present application;

[0052] Fig.14c A schematic diagram of a structure in which a third conductive layer is provided in a blind hole in a circuit board manufacturing method provided in an embodiment of the present application;

[0053] Fig.14d A schematic diagram of a structure for laminating a first board layer, a second dielectric layer, and a second board layer in a circuit board manufacturing method provided in an embodiment of the present application;

[0054] Fig.15a A schematic diagram of the structure of a first conductive layer, a first dielectric layer and a second conductive layer, a second dielectric layer and a fourth conductive layer, a third dielectric layer and a fifth conductive layer in a circuit board manufacturing method provided in an embodiment of the present application;

[0055] Fig.15b A schematic diagram of a structure in which blind holes are formed on a first dielectric layer and a second conductive layer, and blind holes are formed on a third dielectric layer and a fourth conductive layer in a circuit board manufacturing method provided in an embodiment of the present application;

[0056] Fig.15c A schematic diagram of a structure in which a third conductive layer is provided in a blind hole in a circuit board manufacturing method provided in an embodiment of the present application;

[0057] Fig.15d A schematic structural diagram of laminating a first board layer, a second dielectric layer, and a second board layer in a circuit board manufacturing method provided in an embodiment of the present application.

[0058] Description of reference numerals:

[0059] 100-circuit board; 10-first conductive layer; 20-first dielectric layer; 30-second conductive layer; 40-blind hole; 401-opening; 50-third conductive layer; 60-second dielectric layer; 70-fourth conductive layer; 80-third dielectric layer; 90-fifth conductive layer; 1-first board layer; 2-second board layer; 3-middle layer; 31-conductive layer; 32-dielectric layer; 4-shielding hole; 5-connecting hole; 200-chip; 300-solder. DETAILED DESCRIPTION

[0060] The terms used in the implementation method part of this application are only used to explain the specific embodiments of this application, and are not intended to limit this application. The implementation method of the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0061] Circuit boards can miniaturize and visualize circuits, and play an extremely important role in the mass production of fixed circuits and the optimization of electrical appliance layout. Circuit boards can be divided into three types: flexible printed circuits (FPC), printed circuit boards (PCB), and soft and hard combination plates. Among them, flexible circuit boards are made of polyimide or polyester film as a substrate, with high reliability and good flexibility. They have the characteristics of high wiring density, light weight, thin thickness, and good bending. Printed circuit boards are circuit boards made by electronic printing technology. They are important electronic components, support bodies for electronic components, and carriers for electrical connections of electronic components. With the birth and development of flexible circuit boards and printed circuit boards, a new product, soft and hard combination boards, was born. Therefore, soft and hard combination boards are flexible circuit boards and hard circuit boards, which are combined together according to relevant process requirements after lamination and other processes to form circuit boards with the characteristics of flexible circuit boards and printed circuit boards.

[0062] At present, there are two ways to achieve the conduction between the surface circuit and the inner circuit of the circuit board. One is to conduct the circuit by wire bonding, and the other is to set blind holes. Since the method of setting blind holes saves more design area on the circuit board to achieve high density compared with the method of wire bonding, it is increasingly inclined to conduct the two circuit layers by setting blind holes. In the prior art, when setting blind holes on the circuit board, a blind hole is usually formed on the surface of the circuit board by laser drilling. The blind hole needs to penetrate the surface copper layer of the circuit board and the dielectric layer between the surface copper layer and the inner copper layer of the circuit board. Then, the blind hole formed above is electroplated and filled to ensure welding reliability. The electroplating material is copper. During the electroplating and filling process, the thickness of the surface copper layer of the circuit board will increase, and the flatness of the surface copper layer will deteriorate. In order to reduce the thickness of the surface copper layer of the circuit board, chemical etching or physical flattening is generally used to remove excess copper on the surface copper layer of the circuit board to reduce the thickness of the surface copper layer of the circuit board. However, the thickness of the surface copper layer of the above circuit board will still increase to a certain extent, and the problem of poor flatness of the surface copper layer cannot be improved.

[0063] The thickness and flatness of the surface copper layer of the circuit board will affect the accuracy and width of the routing on the circuit board, thereby affecting the performance of the electronic equipment using the circuit board. Taking antenna products as an example, antenna products require thinner outer RF lines and higher line width accuracy to obtain better electrical performance benefits. However, excessive thickness of the surface copper layer will lead to poor line width accuracy, and poor flatness of the surface copper layer will make it impossible to make the line width of the outer RF line smaller.

[0064] Based on this, the embodiment of the present application provides a circuit board and a manufacturing method, wherein at least one blind hole is formed on the second conductive layer and the first dielectric layer, the opening of the blind hole is located on the second conductive layer, a third conductive layer is arranged in the blind hole, and the first conductive layer as the surface layer of the circuit board is connected to the second conductive layer through the third conductive layer, that is, a blind hole is formed from the inner layer to the outer layer (the surface layer of the circuit board), so that when the third conductive layer is arranged, the thickness of the surface plating of the circuit board can be kept constant, thereby avoiding the problem of increased thickness and poor flatness of the surface copper layer of the circuit board in the prior art. In addition, compared with the prior art in which a blind hole is formed on the first conductive layer and the first dielectric layer as the surface layer of the circuit board, and the opening of the blind hole is located on the surface layer of the circuit board, it is possible to avoid the appearance of the first conductive layer, i.e., the surface layer of the circuit board, being affected by a depression at the opening of the blind hole.

[0065] The embodiment of the present application provides a circuit board that can be a flexible circuit board, a printed circuit board, or a combination of hard and soft boards. Moreover, on the basis that the circuit board is a flexible circuit board, a printed circuit board, or a combination of hard and soft boards, the embodiment of the present application provides a circuit board that can be a double-layer circuit board, a three-layer circuit board, a four-layer circuit board, or a circuit board with more layers. Exemplarily, the embodiment of the present application provides a circuit board that can be a double-layer flexible circuit board, a double-layer printed circuit board, a three-layer flexible circuit board, a three-layer printed circuit board, a four-layer flexible circuit board, or a four-layer printed circuit board, etc. The embodiment of the present application does not limit the specific type of the circuit board, nor is it limited to the above examples.

[0066] The specific structure of the circuit board and the method for manufacturing the circuit board are introduced below by taking different embodiments as examples and combining with the accompanying drawings.

[0067] Embodiment 1

[0068] Reference Figure 1As shown, the present application provides a circuit board 100, which may at least include: a first conductive layer 10, a second conductive layer 30, and a first dielectric layer 20 located between the first conductive layer 10 and the second conductive layer 30, wherein the first conductive layer 10 serves as the surface layer of the circuit board 100, and at least one blind hole 40 is formed on the second conductive layer 30 and the first dielectric layer 20, and the opening 401 of the blind hole 40 is located on the second conductive layer 30. A third conductive layer 50 is arranged in the blind hole 40, and the first conductive layer 10 is conductively connected to the second conductive layer 30 through the third conductive layer 50.

[0069] A blind hole 40 is formed on the second conductive layer 30 and the first dielectric layer 20, and the opening 401 of the blind hole 40 is located on the second conductive layer 30, that is, the blind hole 40 is formed from the inner layer to the outer layer (surface layer) of the circuit board 100, so that when the third conductive layer 50 is set, the surface coating thickness can be achieved without increasing, and because the coating flatness or uniformity is poorer than the bottom copper (the original copper layer of the circuit board), it can avoid the problem of poor surface flatness or uniformity of the circuit board when the third conductive layer is set on the surface of the circuit board in the prior art. Therefore, finer and higher precision outer layer circuits can be processed on the circuit board 100 in the embodiment of the present application to obtain higher graphic accuracy. For example, after actual application, it is tested that the circuit board 100 in the embodiment of the present application can process outer layer circuits less than 0.1mm, and the processing error can reach less than ±15um.

[0070] In addition, there will be no depression on the surface of the circuit board 100 in the embodiment of the present application, thereby avoiding affecting the appearance of the first conductive layer 10, i.e., the surface of the circuit board, and facilitating the welding reliability and welding yield of the surface pads when the pads are arranged on the surface. Therefore, the circuit board 100 provided in the embodiment of the present application can not only be applied to the schemes requiring high-density and high-precision graphics, but also can provide great advantages for the design scheme of extremely flat plate holes.

[0071] The third conductive layer 50 is disposed in the blind hole 40, including but not limited to the following two possible implementations:

[0072] One possible implementation is: Figure 1 As shown, the third conductive layer 50 can be disposed on the inner wall of the blind hole 40. By disposing the third conductive layer 50 on the inner wall of the blind hole 40, current conduction and signal transmission can be achieved between the first conductive layer 10 and the second conductive layer 30 through the third conductive layer 50.

[0073] Another possible implementation is: Figure 2As shown, the blind holes 40 may be filled with the third conductive layer 50. By filling the blind holes 40 with the third conductive layer 50, the conduction path between the first conductive layer 10 and the second conductive layer 30 is increased, so that the through-hole current capacity is stronger. Figure 1 The method of not completely filling the blind hole 40 can save electroplating costs to a certain extent and improve work efficiency.

[0074] In addition, as an optional implementation, a conductive paste (not shown) may be disposed in the blind hole 40 to achieve conduction between the first conductive layer 10 and the second conductive layer 30 .

[0075] In the embodiment of the present application, the inner diameter of the blind hole 40 can be gradually reduced in the direction from the opening 401 of the blind hole 40 to the bottom wall of the blind hole 40. In this way, the inner diameter of the blind hole 40 near the first conductive layer 10 is relatively small, and when the corresponding pad is arranged on the first conductive layer 10, the size of the pad can be reduced, thereby increasing the number of pads arranged on the circuit board 100 of the same size and improving the density of the pads.

[0076] In addition, the inner diameter of the blind hole 40 can be flexibly set according to the performance requirements of the circuit board 100 in the specific application scenario, and the embodiment of the present application does not limit this. It should be noted that in the embodiment of the present application, different flow effects and shielding effects can be obtained by adjusting the inner diameter of the blind hole 40. The larger the inner diameter of the blind hole 40, the better the flow effect. The larger the inner diameter of the blind hole 40, the better the signal shielding effect corresponding to the chip set on the circuit board 100. In addition, by setting the inner diameter of the blind hole 40 smaller, when setting the corresponding pad on the first conductive layer 10 corresponding to the blind hole 40, the size of the pad can be reduced, thereby increasing the number of pads set on the circuit board 100 of the same size, and improving the design density of the pad.

[0077] In the embodiment of the present application, the shape of the blind hole 40 includes but is not limited to the following two possible implementations:

[0078] One possible implementation is: Figure 1 or Figure 2 As shown, the inner wall of the blind hole 40 may be a planar structure.

[0079] Another possible implementation is: Figure 3 or Figure 4As shown, the inner wall of the blind hole 40 can be a stepped structure. By designing the inner wall of the blind hole 40 as a stepped structure, when the inner diameter of the blind hole 40 near the first conductive layer 10 is kept constant, the inner diameter of the blind hole 40 with a stepped structure away from the first conductive layer 10, that is, the inner diameter of the blind hole 40 at the opening 401 of the blind hole 40 is larger than that of the blind hole 40 with a planar structure, thereby improving the flow capacity inside the blind hole 40 to a certain extent. If the inner diameter of the blind hole 40 away from the first conductive layer 10, that is, the inner diameter of the opening 401 of the blind hole 40 is kept constant, the inner diameter of the blind hole 40 with a stepped structure near the first conductive layer 10 is smaller than that of the blind hole 40 with a planar structure, when the corresponding pad is set on the first conductive layer 10, the size of the pad can be reduced, and the occupied space on the circuit board 100 can be reduced. On the other hand, the number of pads set on the circuit board 100 of the same size can be increased, and the density of the pads can be increased.

[0080] In addition, it should be noted that the processing of high dielectric thickness blind holes is limited by the thickness-to-diameter ratio capability. When the thickness-to-diameter ratio capability is fixed, the required blind hole diameter, pad size, and outer space occupied are relatively large. However, by designing stepped holes, the maximum processable dielectric thickness capability can be increased. By processing stepped holes from the inside to the outside, the pad size and occupied space of the outer layer of the circuit board 100 are relatively small. Designing the inner wall of the blind hole 40 as a stepped structure can also increase the available thickness of the first dielectric layer 20, thereby reducing design constraints. In addition, in the high dielectric thickness and high-density solder joint design scheme, the inner pad size is small, and blind hole processing in a suitable direction can also be used to achieve the purpose of saving space.

[0081] In the embodiment of the present application, when the inner wall of the blind hole 40 is a stepped structure, the blind hole 40 may be filled with the third conductive layer 50 (see Figure 3 As shown), the third conductive layer 50 may also be disposed only on the inner wall of the blind hole 40 (see Figure 4 shown).

[0082] Based on the above description, in actual application, refer to the attached Figure 5 As shown, when the chip 200 is set on the circuit board 100, the chip 200 is soldered to the circuit board 100 using solder 300 (such as solder paste). Since the flatness and uniformity of the surface layer (first conductive layer 10) of the circuit board 100 are not affected, and no depressions will appear on the surface layer of the circuit board 100 in the embodiment of the present application, it is possible to avoid affecting the appearance of the first conductive layer 10, i.e., the surface layer of the circuit board, and it is helpful to improve the welding reliability and welding yield of the surface pads when the pads are set on the first conductive layer 10.

[0083] As an optional implementation, refer to Figure 6As shown, the circuit board 100 may further include: a second dielectric layer 60, wherein the second conductive layer 30 is located between the first dielectric layer 20 and the second dielectric layer 60, and the side of the second dielectric layer 60 close to the second conductive layer 30 is in contact with the opening 401 of the blind hole 40. In this way, the side of the second dielectric layer 60 close to the second conductive layer 30 is in contact with the opening 401 of the blind hole 40, and if there is a depression at the opening 401 of the blind hole 40 on the second conductive layer 30, the depression can be hidden between the second conductive layer 30 and the second dielectric layer 60, and during the lamination process of the second conductive layer 30 and the second dielectric layer 60, the second dielectric layer 60 can also fill the depression to a certain extent.

[0084] Embodiment 2

[0085] Different from the above-mentioned embodiment 1, referring to the attached Figure 7 or Figure 8 As shown, based on the above-mentioned embodiment 1, the circuit board 100 provided in the present application may further include: a fourth conductive layer 70, a fifth conductive layer 90 and a third dielectric layer 80 located between the fourth conductive layer 70 and the fifth conductive layer 90, wherein the fourth conductive layer 70 is located between the second dielectric layer 60 and the third dielectric layer 80. Figure 7 and Figure 8 The difference is, Figure 7 In the embodiment, the inner wall of the blind hole 40 formed on the first dielectric layer 20 and the second conductive layer 30 is a planar structure. Figure 8 In the embodiment, the inner wall of the blind hole 40 formed on the first dielectric layer 20 and the second conductive layer 30 is a stepped structure.

[0086] In addition, if Fig. 9 As shown, at least one blind hole 40 may be formed on the fourth conductive layer 70 and the third dielectric layer 80 , wherein the opening 401 of the blind hole 40 is located on the fourth conductive layer 70 , the third conductive layer 50 is disposed in the blind hole 40 , and the fourth conductive layer 70 is conductively connected to the fifth conductive layer 90 through the third conductive layer 50 .

[0087] By forming at least one blind hole 40 on the fourth conductive layer 70 and the third dielectric layer 80, the opening 401 of the blind hole 40 is located on the fourth conductive layer 70, and the third conductive layer 50 is arranged in the blind hole 40, the fifth conductive layer 90 as the surface layer of the circuit board 100 is connected to the fourth conductive layer 70 through the third conductive layer 50, which can avoid the problem of increased thickness and poor flatness of the surface copper layer of the circuit board 100 in the prior art. In addition, compared with the prior art in which the blind hole 40 is formed on the fifth conductive layer 90 and the third dielectric layer 80 as the surface layer of the circuit board 100, and the opening 401 of the blind hole 40 is located on the surface layer of the circuit board 100, it can avoid the presence of a depression at the opening 401 of the blind hole 40, which affects the appearance of the fifth conductive layer 90, i.e., the surface layer of the circuit board 100.

[0088] In addition, the circuit board 100 provided in the present application may further include: at least one intermediate layer 3, and at least one intermediate layer 3 is located between the second dielectric layer 60 and the fourth conductive layer 70. Alternatively, at least one intermediate layer 3 is located between the second dielectric layer 60 and the second conductive layer 30. The intermediate layer 3 may include a conductive layer 31 and a dielectric layer 32, and the conductive layer 31 and the dielectric layer 32 in at least one intermediate layer 3 are alternately stacked.

[0089] It should be noted that, in the embodiment of the present application, the conductive layer 31 and the dielectric layer 32 in at least one intermediate layer 3 are alternately stacked, that is, for example, when there are two intermediate layers 3, the conductive layer 31 in one of the two intermediate layers 3 is adjacent to the dielectric layer 32 in the other of the two intermediate layers 3, or the dielectric layer 32 in one of the two intermediate layers 3 is adjacent to the conductive layer 31 in the other of the two intermediate layers 3. Moreover, when at least one intermediate layer 3 is located between the second dielectric layer 60 and the fourth conductive layer 70, the second dielectric layer 60 is adjacent to the conductive layer 31 in at least one intermediate layer 3, and the fourth conductive layer 70 is adjacent to the dielectric layer 32 in at least one intermediate layer 3. When at least one intermediate layer 3 is located between the second dielectric layer 60 and the second conductive layer 30, the second dielectric layer 60 is adjacent to the conductive layer 31 in at least one intermediate layer 3, and the second conductive layer 30 is adjacent to the dielectric layer 32 in at least one intermediate layer 3. For example, Fig.10 As shown, the circuit board 100 includes three intermediate layers 3, and the three intermediate layers 3 are located between the second dielectric layer 60 and the fourth conductive layer 70, wherein the conductive layer 31 and the dielectric layer 32 in the three intermediate layers 3 are alternately stacked in sequence, the second dielectric layer 60 is adjacent to the conductive layer 31, and the fourth conductive layer 70 is adjacent to the dielectric layer 32.

[0090] and Fig. 9 The structure of the circuit board 100 shown is different in that Fig.10 In the embodiment, the blind hole 40 can also be formed on the third dielectric layer 80 and the fifth conductive layer 90, the opening 401 of the blind hole 40 is located on the fifth conductive layer 90, the third conductive layer 50 is arranged in the blind hole 40, and the fourth conductive layer 70 is connected to the fifth conductive layer 90 through the third conductive layer 50.

[0091] in addition, Fig.10 The circuit board 100 shown has a shielding hole 4 , which is penetrated from the top layer to the bottom layer of the circuit board 100 to form a signal shielding through hole, and the middle part of the circuit board 100 may also have a connecting hole 5 .

[0092] It should be noted that in the embodiment of the present application, the material used for the first conductive layer 10, the second conductive layer 30, the fourth conductive layer 70 and the fifth conductive layer 90 can be any one or more of gold, copper, titanium, palladium, tungsten, nickel or vanadium. For example, it can be gold, copper, or a composite material composed of gold and copper.

[0093] In the embodiments of the present application, other technical features are the same as those in Embodiment 1 and can achieve the same or corresponding technical effects, which will not be described one by one here.

[0094] Embodiment 3

[0095] like Fig.11 As shown, the embodiment of the present application provides a method for manufacturing a circuit board 100, and the method for manufacturing the circuit board 100 may include:

[0096] S101 : at least a first conductive layer 10 , a first dielectric layer 20 , and a second conductive layer 30 are provided in a stacked manner, wherein the first dielectric layer 20 is located on the second conductive layer 30 , and the first conductive layer 10 is located on the first dielectric layer 20 .

[0097] like Fig.13a As shown, a first conductive layer 10 , a first dielectric layer 20 , and a second conductive layer 30 are provided in a stacked manner, wherein the first conductive layer 10 serves as a surface layer of the circuit board 100 , and the first dielectric layer 20 is located between the first conductive layer 10 and the second conductive layer 30 .

[0098] S102 : forming a blind hole 40 on the first dielectric layer 20 and the second conductive layer 30 , wherein an opening 401 of the blind hole 40 is located on the second conductive layer 30 .

[0099] like Fig.13b As shown, a blind hole 40 is formed on the first dielectric layer 20 and the second conductive layer 30, and an opening 401 of the blind hole 40 is located on the second conductive layer 30. Specifically, in the embodiment of the present application, the blind hole 40 may be processed from the side of the second conductive layer 30 away from the first dielectric layer 20 toward the side of the first dielectric layer 20 close to the first conductive layer 10, so that the opening 401 of the blind hole 40 is located on the second conductive layer 30.

[0100] As an optional implementation, the blind hole 40 may be formed on the first dielectric layer 20 and the second conductive layer 30 by laser drilling. Alternatively, in some other embodiments, the blind hole 40 may be formed on the first dielectric layer 20 and the second conductive layer 30 by mechanical processing. The specific processing method of the blind hole is not limited to the above examples in the embodiments of the present application.

[0101] It is understandable that, in some embodiments, after forming the blind hole 40 , the blind hole 40 may be metallized, such as plated through hole (PTH), or the blind hole 40 may be blackened to facilitate further processing of the blind hole 40 .

[0102] S103 : a third conductive layer 50 is disposed in the blind hole 40 , so that the first conductive layer 10 is electrically connected to the second conductive layer 30 through the third conductive layer 50 .

[0103] like Fig.13c As shown, a third conductive layer 50 is disposed in the blind hole 40, so that the first conductive layer 10 is connected to the second conductive layer 30 through the third conductive layer 50. Specifically, in the embodiment of the present application, the third conductive layer 50 may be disposed in the blind hole 40 by using a single-sided electroplating process. It should be noted that by using a single-sided electroplating process, it is possible to avoid processing the other side of the circuit board 100 opposite to the blind hole 40 during electroplating, thereby reducing the electroplating cost and improving work efficiency to a certain extent.

[0104] The single-sided electroplating process can be implemented by applying current on one side or by dry film resist plating. For example, only one side of the circuit board 100 can be electroplated by applying current on one side, or one side of the circuit board 100 can be shielded by dry film resist plating to electroplate the other side of the circuit board 100. Of course, the methods for implementing the single-sided electroplating process include but are not limited to the above two possible implementation methods, and the embodiments of the present application are not limited thereto.

[0105] In the embodiment of the present application, the third conductive layer 50 is provided in the blind hole 40 by using a single-sided electroplating process, which may include but is not limited to the following two possible implementation methods:

[0106] One possible implementation is to use a single-sided electroplating process to provide a third conductive layer 50 on the inner wall of the blind hole 40 of the second conductive layer 30. By providing the third conductive layer 50 on the inner wall of the blind hole 40, current conduction and signal transmission can be achieved between the first conductive layer 10 and the second conductive layer 30 through the third conductive layer 50.

[0107] Another possible implementation is to use a single-sided electroplating process to fill the third conductive layer 50 in the blind holes 40 of the second conductive layer 30. By filling the blind holes 40 with the third conductive layer 50, the conduction path between the first conductive layer 10 and the second conductive layer 30 is increased, so that the through-hole current capacity is stronger. The thicker copper layer in the circuit board 100 can enhance the stability of the current transmission of the circuit board 100 and improve the heat dissipation capacity of the circuit board 100.

[0108] As an optional implementation, when the third conductive layer 50 is provided in the blind hole 40, it can be implemented in multiple steps, for example, a layer of metal, such as gold, titanium or palladium, can be firstly sputtered or deposited on the inner wall of the blind hole 40, and then gold or copper is electroplated on the metal formed by sputtering or deposition to form the third conductive layer 50. It should be noted that the thickness of a sputtered or deposited layer of metal is generally at the nm level, and the thickness of a plated layer of metal is generally at the um level.

[0109] Of course, in some other embodiments, the third conductive layer 50 may be formed by coating a conductive paste, wherein the conductive paste may be made of copper, silver, etc. as a main material.

[0110] In a possible implementation, the material used for the third conductive layer 50 may be any one or more of gold, copper, titanium, palladium, tungsten, nickel or vanadium. For example, the third conductive layer 50 may be gold, copper, or a composite material composed of gold and copper.

[0111] By forming at least one blind hole 40 on the second conductive layer 30 and the first dielectric layer 20, the opening 401 of the blind hole 40 is located on the second conductive layer 30, and the third conductive layer 50 is arranged in the blind hole 40, the first conductive layer 10 as the surface layer of the circuit board 100 is connected to the second conductive layer 30 through the third conductive layer 50, which can avoid the problem of increased thickness and poor flatness of the surface copper layer of the circuit board 100 in the prior art. In addition, compared with the prior art in which the blind hole 40 is formed on the first conductive layer 10 and the first dielectric layer 20 as the surface layer of the circuit board 100, and the opening 401 of the blind hole 40 is located on the surface layer of the circuit board 100, it can avoid the presence of a depression at the opening 401 of the blind hole 40, which affects the appearance of the first conductive layer 10, i.e., the surface layer of the circuit board 100.

[0112] In the embodiments of the present application, Fig.12 As shown, after the third conductive layer 50 is provided in the blind hole 40, the method for manufacturing the circuit board 100 may further include:

[0113] S104 : a second dielectric layer 60 is disposed on a surface of the second conductive layer 30 facing away from the first dielectric layer 20 , wherein a side of the second dielectric layer 60 close to the second conductive layer 30 is in contact with the opening 401 of the blind hole 40 .

[0114] By contacting the opening 401 of the blind hole 40 with one side of the second dielectric layer 60 close to the second conductive layer 30, if there is a depression at the opening 401 of the blind hole 40 on the second conductive layer 30, the depression can be hidden between the second conductive layer 30 and the second dielectric layer 60, and during the lamination process of the second conductive layer 30 and the second dielectric layer 60, the second dielectric layer 60 can also fill the depression to a certain extent.

[0115] In addition, it should be noted that the method for manufacturing a circuit board provided in the embodiment of the present application can also solve the problem of difficulty in manufacturing the outer layer graphics of the circuit board in the prior art. In the prior art, in order to reduce the increase in the thickness of the surface copper layer of the circuit board during the electroplating filling of the blind hole, a dry film is generally covered in some areas to avoid being thickened by electroplating. In this way, the thickness between the covered area and the uncovered area is inconsistent, and steps will be formed. If the extra plating layer is flattened, it is easy to cause surface pits, affecting the appearance and even the outer layer circuit production. Alternatively, vacuum lamination is used to overcome the influence of the inconsistent thickness between the covered area and the uncovered area on the production of the outer layer circuit graphics, but during vacuum lamination, due to the presence of steps, it will cause difficulty in filling the outer layer dry film, and it is easy to form gaps, and then form open gaps (acid etching process) or residual copper (alkaline etching process) after etching. When the structural design and manufacturing process of the circuit board provided in the embodiment of the present application are adopted, the coating thickness of the surface layer (e.g., the first conductive layer 10) of the circuit board 100 will not increase, and the uniformity of the conductive layer will not deteriorate. Therefore, the appearance problems such as pits in the outer layer coating caused by steps, as well as the problems of open circuit gaps or residual copper in the outer layer caused by insufficient filling of the outer dry film, can be eliminated.

[0116] Based on the above embodiment, the circuit board may include more layers, so the method for manufacturing the circuit board 100 may further include:

[0117] S101A: Provide a fourth conductive layer 70 , a third dielectric layer 80 , and a fifth conductive layer 90 that are stacked, wherein the third dielectric layer 80 is located on the fifth conductive layer 90 , and the fourth conductive layer 70 is located on the third dielectric layer 80 .

[0118] like Fig.14a and Fig.15a As shown, a first conductive layer 10, a first dielectric layer 20, and a second conductive layer 30 are provided in a stacked manner, wherein the first conductive layer 10 serves as a surface layer of the circuit board 100, and the first dielectric layer 20 is located between the first conductive layer 10 and the second conductive layer 30. A fourth conductive layer 70, a third dielectric layer 80, and a fifth conductive layer 90 are also provided in a stacked manner, wherein the fifth conductive layer 90 serves as another surface layer of the circuit board 100 disposed opposite to the first conductive layer 10, and the third dielectric layer 80 is located between the fourth conductive layer 70 and the fifth conductive layer 90. Fig.14a and Fig.15a In the embodiment, the stacked first conductive layer 10 , the first dielectric layer 20 and the second conductive layer 30 serve as the first board layer 1 , and the stacked fourth conductive layer 70 , the third dielectric layer 80 and the fifth conductive layer 90 serve as the second board layer 2 .

[0119] In addition, if Fig.14bAs shown, a blind hole 40 is formed on the first dielectric layer 20 and the second conductive layer 30, and an opening 401 of the blind hole 40 is located on the second conductive layer 30. On this basis, as an optional implementation, it may also include:

[0120] S102A: a blind hole 40 is formed on the third dielectric layer 80 and the fourth conductive layer 70 , and an opening 401 of the blind hole 40 is located on the fourth conductive layer 70 .

[0121] like Fig.15b As shown, a blind hole 40 is formed on the third dielectric layer 80 and the fourth conductive layer 70, and an opening 401 of the blind hole 40 is located on the fourth conductive layer 70. Specifically, in the embodiment of the present application, the blind hole 40 may be processed from the side of the fourth conductive layer 70 away from the third dielectric layer 80 toward the side of the third dielectric layer 80 close to the fifth conductive layer 90, so that the opening 401 of the blind hole 40 is located on the fourth conductive layer 70.

[0122] As an optional implementation, the blind hole 40 may be formed on the third dielectric layer 80 and the fourth conductive layer 70 by laser drilling. Alternatively, in some other embodiments, the blind hole 40 may be formed on the first dielectric layer 20 and the second conductive layer 30 by mechanical processing. The specific processing method of the blind hole is not limited to the above examples in the embodiments of the present application.

[0123] like Fig.14c As shown, a third conductive layer 50 is disposed in the blind hole 40, so that the first conductive layer 10 is connected to the second conductive layer 30 through the third conductive layer 50. On this basis, as an optional implementation, it can also include:

[0124] S103A: a third conductive layer 50 is disposed in the blind hole 40 , so that the fifth conductive layer 90 is electrically connected to the fourth conductive layer 70 through the third conductive layer 50 .

[0125] like Fig.15c As shown, the third conductive layer 50 is disposed in the blind hole 40, so that the fifth conductive layer 90 is connected to the fourth conductive layer 70 through the third conductive layer 50. Specifically, in the embodiment of the present application, the third conductive layer 50 may be disposed in the blind hole 40 by using a single-sided electroplating process. It should be noted that by using a single-sided electroplating process, it is possible to avoid processing the other side of the circuit board 100 opposite to the blind hole 40 during electroplating, thereby reducing the electroplating cost and improving work efficiency to a certain extent.

[0126] By forming at least one blind hole 40 on the fourth conductive layer 70 and the third dielectric layer 80, the opening 401 of the blind hole 40 is located on the fourth conductive layer 70, and the third conductive layer 50 is arranged in the blind hole 40, the fifth conductive layer 90 as the surface layer of the circuit board 100 is connected to the fourth conductive layer 70 through the third conductive layer 50, which can avoid the problem of increased thickness and poor flatness of the surface copper layer of the circuit board 100 in the prior art. In addition, compared with the prior art in which the blind hole 40 is formed on the fifth conductive layer 90 and the third dielectric layer 80 as the surface layer of the circuit board 100, and the opening 401 of the blind hole 40 is located on the surface layer of the circuit board 100, it can avoid the presence of a depression at the opening 401 of the blind hole 40, which affects the appearance of the fifth conductive layer 90, i.e., the surface layer of the circuit board 100.

[0127] S104: Laminating the first board layer 1 , the second dielectric layer 60 and the second board layer 2 .

[0128] like Fig.14d As shown, the first board layer 1, the second dielectric layer 60 and the second board layer 2 are pressed together so that the second dielectric layer 60 is located between the fourth conductive layer 70 and the second conductive layer 30, wherein the side of the second dielectric layer 60 close to the second conductive layer 30 is in contact with the opening 401 of the blind hole 40 on the second conductive layer 30. Fig.15d As shown, the first board layer 1, the second dielectric layer 60 and the second board layer 2 are pressed together so that the second dielectric layer 60 is located between the fourth conductive layer 70 and the second conductive layer 30, wherein the side of the second dielectric layer 60 close to the second conductive layer 30 is in contact with the opening 401 of the blind hole 40 on the second conductive layer 30, and the side of the second dielectric layer 60 close to the fourth conductive layer 70 is in contact with the opening 401 of the blind hole 40 on the fourth conductive layer 70.

[0129] Similarly, by contacting the opening 401 of the blind hole 40 with one side of the second dielectric layer 60 close to the fourth conductive layer 70, if there is a depression at the opening 401 of the blind hole 40 on the fourth conductive layer 70, the depression can be hidden between the fourth conductive layer 70 and the second dielectric layer 60, and during the lamination process of the fourth conductive layer 70 and the second dielectric layer 60, the second dielectric layer 60 can also fill the depression to a certain extent.

[0130] In a possible implementation, before S104, the circuit board manufacturing method provided in the embodiment of the present application may further include:

[0131] S105: providing at least one intermediate layer 3 .

[0132] The intermediate layer 3 includes a conductive layer 31 and a dielectric layer 32, and the conductive layer 31 and the dielectric layer 32 in at least one intermediate layer 3 are alternately stacked. For example, when there are two intermediate layers 3, the conductive layer 31 in one of the two intermediate layers 3 is adjacent to the dielectric layer 32 in the other of the two intermediate layers 3, or the dielectric layer 32 in one of the two intermediate layers 3 is adjacent to the conductive layer 31 in the other of the two intermediate layers 3.

[0133] S106: disposing at least one intermediate layer 3 between the second dielectric layer 60 and the fourth conductive layer 70. Alternatively, disposing at least one intermediate layer 3 between the second dielectric layer 60 and the second conductive layer 30.

[0134] When at least one intermediate layer 3 is located between the second dielectric layer 60 and the fourth conductive layer 70, the second dielectric layer 60 is adjacent to the conductive layer 31 in at least one intermediate layer 3, and the fourth conductive layer 70 is adjacent to the dielectric layer 32 in at least one intermediate layer 3. When at least one intermediate layer 3 is located between the second dielectric layer 60 and the second conductive layer 30, the second dielectric layer 60 is adjacent to the conductive layer 31 in at least one intermediate layer 3, and the second conductive layer 30 is adjacent to the dielectric layer 32 in at least one intermediate layer 3. For example, Fig.10 As shown, the circuit board 100 includes three intermediate layers 3, and the three intermediate layers 3 are located between the second dielectric layer 60 and the fourth conductive layer 70, wherein the conductive layer 31 and the dielectric layer 32 in the three intermediate layers 3 are alternately stacked in sequence, the second dielectric layer 60 is adjacent to the conductive layer 31, and the fourth conductive layer 70 is adjacent to the dielectric layer 32.

[0135] In addition, it should be noted that in the embodiments of the present application, the inner wall of the blind hole 40 is a planar structure. In some other embodiments, the blind hole 40 can also be made into a stepped hole. For example, when forming the blind hole 40 with a stepped inner wall, a larger hole can be first formed by laser drilling, and then a smaller hole can be formed by laser drilling on the basis of the larger hole, so as to form a blind hole 40 having a stepped inner wall. Figure 3 or Figure 4 Stepped hole shown.

[0136] Embodiment 4

[0137] An embodiment of the present application provides an electronic device, which may include at least any one of the circuit boards 100 in any one of the above embodiments.

[0138] The electronic device at least comprises a circuit board 100, wherein the circuit board 100 is provided with at least one blind hole 40 formed on the second conductive layer 30 and the first dielectric layer 20, wherein the opening 401 of the blind hole 40 is located on the second conductive layer 30, and a third conductive layer 50 is arranged in the blind hole 40, and the first conductive layer 10 as the surface layer of the circuit board 100 is connected with the second conductive layer 30 through the third conductive layer 50, thereby avoiding the problem of increased thickness and poor flatness of the surface copper layer of the circuit board 100 in the prior art. In addition, compared with the prior art in which the blind hole is formed on the first conductive layer and the first dielectric layer as the surface layer of the circuit board, and the opening of the blind hole is located on the surface layer of the circuit board, it is possible to avoid depression at the opening of the blind hole, thereby avoiding affecting the appearance of the first conductive layer, i.e., the surface layer of the circuit board.

[0139] In addition, by providing the circuit board 100 in the electronic device, the experience effect of the electronic device can be optimized. At the same time, the stability of signal transmission in the electronic device is also guaranteed, ensuring the normal operation of the electronic device.

[0140] It should be noted that the electronic device provided in the embodiment of the present application may include but is not limited to mobile phones, tablet computers, laptop computers, ultra-mobile personal computers (UMPCs), handheld computers, walkie-talkies, netbooks, PO step machines, personal digital assistants (PDAs), wearable devices, virtual reality devices, and other mobile or fixed terminals having the above-mentioned circuit board 100.

[0141] In addition, the electronic device provided in the embodiments of the present application may also include but is not limited to semiconductor devices, which can be applied to the field of high power density electronic components, such as metal oxide semiconductor (MOS), insulated gate bipolar transistor (IGBT), power supply chip, etc., so as to achieve a high efficiency, low thermal resistance and high reliability grounding scheme for the device.

[0142] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, or it can be an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0143] In the embodiments of the present application, the devices or elements referred to or implied must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the embodiments of the present application. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0144] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the embodiments of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application have been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit board, characterized in that: At least: A first conductive layer, a second conductive layer and a first dielectric layer located between the first conductive layer and the second conductive layer; At least one blind hole is formed on the second conductive layer and the first dielectric layer, and the opening of the blind hole is located on the second conductive layer; A third conductive layer is disposed in the blind hole, and the first conductive layer is electrically connected to the second conductive layer through the third conductive layer; Wherein, the first conductive layer serves as the surface layer of the circuit board; Also includes: a second dielectric layer; The second conductive layer is located between the first dielectric layer and the second dielectric layer, and a side of the second dielectric layer close to the second conductive layer is in contact with the opening of the blind hole; It also includes: a fourth conductive layer, a fifth conductive layer, and a third dielectric layer located between the fourth conductive layer and the fifth conductive layer; The fourth conductive layer is located between the second dielectric layer and the third dielectric layer; At least one blind hole is formed on the fourth conductive layer and the third dielectric layer, and the opening of the blind hole is located on the fourth conductive layer; The third conductive layer is disposed in the blind hole, and the fourth conductive layer is conductively connected to the fifth conductive layer through the third conductive layer.

2. The circuit board according to claim 1, characterized in that: Also includes: at least one intermediate layer, the at least one intermediate layer being located between the second dielectric layer and the fourth conductive layer; or the at least one intermediate layer being located between the second dielectric layer and the second conductive layer; The intermediate layer includes a conductive layer and a dielectric layer, and the conductive layer and the dielectric layer in the at least one intermediate layer are alternately stacked.

3. The circuit board according to claim 1 or 2, characterized in that: The third conductive layer is arranged on the inner wall of the blind hole.

4. The circuit board according to claim 1 or 2, characterized in that: The blind holes are all filled with the third conductive layer.

5. The circuit board according to claim 1 or 2, characterized in that: Also includes: The shielding hole is penetrated from the top layer to the bottom layer of the circuit board to form a signal shielding through hole.

6. The circuit board according to claim 1 or 2, characterized in that: The third conductive layer includes a first metal layer and a second metal layer, the first metal layer is formed on the inner wall of the blind hole, and the second metal layer is formed on the first metal layer; The thickness of the first metal layer is smaller than that of the second metal layer; the first metal layer and the second metal layer are made of different metals.

7. The circuit board according to claim 1 or 2, characterized in that: The inner diameter of the blind hole gradually decreases in a direction from the opening of the blind hole to the bottom wall of the blind hole.

8. The circuit board according to claim 7, characterized in that: The inner wall of the blind hole is a stepped structure.

9. An electronic device, characterized in that: At least: The circuit board as described in any one of claims 1 to 8 above.

10. A method for manufacturing a circuit board, characterized in that: The method comprises: At least a first conductive layer, a first dielectric layer, and a second conductive layer are provided in a stacked manner, wherein the first dielectric layer is located on the second conductive layer, and the first conductive layer is located on the first dielectric layer; A blind hole is formed on the first dielectric layer and the second conductive layer, and an opening of the blind hole is located on the second conductive layer; A third conductive layer is arranged in the blind hole, so that the first conductive layer is electrically connected to the second conductive layer through the third conductive layer; Wherein, the first conductive layer serves as the surface layer of the circuit board; A second dielectric layer is disposed on a side of the second conductive layer facing away from the first dielectric layer; Wherein, a side of the second dielectric layer close to the second conductive layer is in contact with the opening of the blind hole; Providing a fourth conductive layer, a third dielectric layer and a fifth conductive layer which are stacked, wherein the third dielectric layer is located on the fifth conductive layer, and the fourth conductive layer is located on the third dielectric layer; A blind hole is formed on the third dielectric layer and the fourth conductive layer, and an opening of the blind hole is located on the fourth conductive layer; The third conductive layer is disposed in the blind hole, so that the fifth conductive layer is electrically connected to the fourth conductive layer through the third conductive layer.

11. The method for manufacturing a circuit board according to claim 10, characterized in that: The second dielectric layer is located between the fourth conductive layer and the second conductive layer; wherein a side of the second dielectric layer close to the fourth conductive layer is in contact with the opening of the blind hole on the fourth conductive layer.

12. The method for manufacturing a circuit board according to claim 10 or 11, characterized in that: Also includes: providing at least one intermediate layer; Disposing the at least one intermediate layer between the second dielectric layer and the fourth conductive layer; Alternatively, the at least one intermediate layer is disposed between the second dielectric layer and the second conductive layer; The intermediate layer comprises a conductive layer and a dielectric layer, and the conductive layer and the dielectric layer in the at least one intermediate layer are alternately stacked.

13. The method for manufacturing a circuit board according to claim 10 or 11, characterized in that: A blind hole is formed on the first dielectric layer and the second conductive layer, and an opening of the blind hole is located on the second conductive layer, comprising: A blind hole is processed from a side of the second conductive layer away from the first dielectric layer toward a side of the first dielectric layer close to the first conductive layer, so that an opening of the blind hole is located on the second conductive layer.

14. The method for manufacturing a circuit board according to claim 10 or 11, characterized in that: A third conductive layer is arranged in the blind hole, comprising: A third conductive layer is arranged in the blind hole by adopting a single-side electroplating process.

15. The method for manufacturing a circuit board according to claim 14, characterized in that: The method of providing a third conductive layer in the blind hole by using a single-sided electroplating process comprises: A third conductive layer is disposed on the inner wall of the blind hole of the second conductive layer by adopting a single-sided electroplating process.

16. The method for manufacturing a circuit board according to claim 14, characterized in that: The method of providing a third conductive layer in the blind hole by using a single-sided electroplating process comprises: The blind holes of the second conductive layer are filled with the third conductive layer by using a single-sided electroplating process.

17. The method for manufacturing a circuit board according to claim 10 or 11, characterized in that: A blind hole is formed on the third dielectric layer and the fourth conductive layer, and the opening of the blind hole is located on the fourth conductive layer, comprising: A blind hole is processed from a side of the fourth conductive layer away from the third dielectric layer toward a side of the third dielectric layer close to the fifth conductive layer, so that an opening of the blind hole is located on the fourth conductive layer.

18. The method for manufacturing a circuit board according to claim 10 or 11, characterized in that: Also includes: forming a shielding hole on the circuit board; The shielding hole is formed from the top layer to the bottom layer of the circuit board to form a signal shielding through hole.

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