Memory with Concurrent Fault Detection and Redundancy

Abstract

A memory includes an error detection circuit that identifies a fault feature in a memory cell array within the memory. A redundancy enabling circuit is used to replace the fault feature with a redundant feature. The error detection circuit and the redundancy enabling circuit are concurrently used to perform a read operation on the memory cell array.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Non - Provisional Patent Application No. 17 / 025,133, filed on September 18, 2020, which in turn claims the benefit of Indian Provisional Patent Application No. 201941044243, filed on October 31, 2019. The contents of both are hereby incorporated by reference in their entirety. Technical Field

[0003] This application relates to memories, and more particularly to memories with concurrent fault detection and redundancy. Background Art

[0004] Integrated circuits such as system - on - chip (SoC) typically include thousands of embedded memories. Thus, the embedded memories typically occupy die space of the SoC. As technology continues to shrink transistor sizes, defects tend to be randomly distributed across the die, and thus have a significant impact on the performance of the embedded memories because the embedded memories occupy most of the die space. Therefore, embedded memories typically include redundancy features, such as redundant bitlines, so that memory faults can be repaired. The repair process is continuous and reduces the memory speed. To perform the repair process, the embedded memories are typically checked by an automatic test equipment (ATE) during the manufacture of the integrated circuit to identify any defects and activate the corresponding redundant columns to repair the embedded memories. If an embedded memory fails during use, the customer typically has to return the integrated circuit to the manufacturer. Summary of the Invention

[0005] According to a first aspect of the present disclosure, there is provided a memory, comprising: an array of memory cells; an error detection circuit configured to detect errors in the array of memory cells and identify a fault signature in the array of memory cells containing the error; a redundancy enabling circuit configured to replace the fault signature with a redundancy feature; and an arbiter configured to order output signals from the array of memory cells, output signals from the error detection circuit, and output signals from the redundancy enabling circuit during a concurrent operation mode in which the error detection circuit, the redundancy enabling circuit, and the array of memory cells are all active.

[0006] According to a second aspect of the present disclosure, there is provided a method for a memory, the method comprising: activating an error detection circuit to compare a test vector read from an array of memory cells with a recorded test vector to identify a fault signature in the array of memory cells; and during the activation of the error detection circuit, activating a redundancy enabling circuit to replace the fault signature with a redundancy feature.

[0007] According to a third aspect of the present disclosure, there is provided a memory, the memory comprising: a memory array configured to retrieve test vectors during a concurrent operation mode, and a redundancy enable circuit configured to replace a faulty feature with a replacement feature during the concurrent operation mode.

[0008] These and other advantageous features can be better understood through the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A A conventional memory array and associated error detection circuitry and redundancy enable circuitry are shown.

[0010] Figure 1B Shows for Figure 1A a sequential diagnosis and repair of a memory array of

[0011] Figure 2A An example concurrent memory according to one aspect of the present disclosure is shown, where diagnosis and repair occur concurrently.

[0012] Figure 2B Shows according to one aspect of the present disclosure Figure 2A a concurrent memory timeline in a concurrent memory of

[0013] Figure 3 is a flowchart of an example concurrent operation mode according to one aspect of the present disclosure.

[0014] Figure 4 Some example electronic systems according to one aspect of the present disclosure are shown, each electronic system including a memory having a concurrent operation mode.

[0015] Embodiments of the present disclosure and their advantages can be best understood by reference to the following detailed description. It should be understood that like reference numerals are used to identify like elements shown in one or more of the figures. DETAILED DESCRIPTION

[0016] A concurrent memory is provided where error detection and repair operations can occur concurrently with read and write operations. The resulting concurrent operation is highly advantageous for reducing the time to detect and repair memory faults. In contrast, sequential execution is conventional for functional read and write operations as well as diagnostic and repair operations on the memory. Referring to Figure 1A this can be better understood, Figure 1AA conventional memory array 105 is shown. During normal operation, an output data stream (tdo) can be read from the memory array 105. However, the operation of the memory array 105 may be affected by manufacturing errors. The error detection circuit 115 is used to detect these errors by recording test vectors written to the memory array 105. During subsequent read operations, the error detection circuit 115 compares the output vectors retrieved from the memory array 105 with the recorded test vectors to identify any faulty bit cells in the memory array 105.

[0017] If the error detection circuit 115 detects an error, the redundancy enable circuit 110 is used to replace the faulty bit cells in the memory array 105 with redundant replacement bit cells. For example, the bit cells in the memory array 105 are typically arranged in rows and columns. To provide a redundancy feature, the memory array 105 may also include replacement bit cells for one or more redundant columns or rows. If a column of bit cells in the memory array 105 fails to operate properly due to a manufacturing error detected by the error detection circuit 115, the faulty column can be replaced with a redundant column by the redundancy enable circuit 110. Alternatively, the redundancy enable circuit 110 can replace the row of faulty bit cells with a redundant row.

[0018] The error detection circuit 115 provides a report of any errors found by messaging on the output signal through the output data stream. Similarly, the redundancy enable circuit 110 reports the confirmation of the replacement of the faulty column (or row) by messaging on the output signal through the output data stream. Given this common usage of the output data stream, an external tool (e.g., ATE) typically controls the diagnostic operations of the error detection circuit 115 and the repair operations of the redundancy enable circuit 110 sequentially. Error detection requires writing and reading test vectors to and from the memory array 105. Reading the test vectors from the memory array 105 can drive the retrieved test vectors onto the output data stream. Since this read operation uses the output data stream, it occurs before the error detection circuit 115 is activated to prevent contention in the output data stream. The conventional writing and reading of test vectors before the operation of the error detection circuit 115 are represented herein as the functional operation mode. Thus, the functional operation mode occurs before the diagnostic operation mode of the error detection circuit 115. Similarly, the diagnostic operation mode occurs before the repair operation mode of the redundancy enable circuit 110.

[0019] The timeline of this sequential operation is shown in Figure 1BIt is shown in . The functional operation mode starts with a setup operation at time t0. At time t1, a write operation occurs, in which a test vector is written to the memory array 105. The error detection circuit 115 also records the test vector during this write operation. For example, the error detection circuit 115 includes a sufficient number of memory elements (e.g., latches) to store the test vector being written to the memory array 105. The write operation is followed by a read operation at time t2, in which the test vector is read (retrieved) from the memory array 105.

[0020] At time t3, the diagnostic operation mode starts with a setup at time t3. At time t4, the error detection operation of the error detection circuit 115 occurs until time t5. Such an error detection operation involves comparing the recorded test vector recorded by the error detection circuit 115 during the write operation with the retrieved test vector read from the memory array 105 during the read operation. If the read operation test vector is different from the recorded test vector, the error detection circuit 115 detects an error. The diagnostic operation also includes an error isolation operation that starts at time t5 and ends at time t6. Through the error isolation operation, the error detection circuit 115 identifies the fault feature (e.g., a faulty column) in the memory array 105 that produced the detected error. The error detection circuit 115 transmits the identity of the fault feature to an external test tool through the output data stream.

[0021] The repair operation mode starts with a setup operation at time t6, and the setup operation ends at time t7. The redundancy enabling operation starts at time t7 and continues until time t8. During the redundancy enabling operation, the redundancy enabling circuit 110 enables redundancy features such as redundant columns to replace the fault feature identified in the previous error isolation operation. The repair operation mode ends with a write / read operation that is performed from time t8 to time t9, and the write / read operation can be used to confirm the successful operation of the enabled redundancy feature.

[0022] To significantly reduce the time required to complete the diagnostic operation mode and the repair operation mode, a concurrent memory is disclosed in which error detection, error isolation, and redundancy enabling operations are performed concurrently with the reading of the error vector. Advantageously, this concurrent memory does not require modification to the redundancy enabling circuit 110. Similarly, no modification to the error detection circuit 115 is required. Since these circuits are known, their structures will not be discussed in detail herein. However, what is different is the logic in the concurrent memory and the sequencer that enables the concurrent memory operation. Figure 2AAn example memory 200 with a concurrent operation mode is shown. The memory 200 responds to two mode signals: a mode 1 signal and a mode 0 signal. If both mode signals are asserted, the concurrent operation mode is activated, as will be discussed further herein. However, the memory 200 is also backward compatible with sequential functional operation mode, diagnostic operation mode, and repair operation mode, as discussed with respect to the memory array 105, depending on the state of the mode signals. The following table summarizes the mode control resulting from the mode signals:

[0023]

[0024] The memory 200 includes an array 105 of bit cells or memory cells, an error detection circuit 115, and a redundancy enable circuit 110, as discussed with respect to Figure 1A During a functional mode in which both mode signals are logic 0, the NAND gate 215 receiving the two mode signals asserts the memory enable signal 216. The asserted memory enable signal 216 passes through the OR gate 230 to activate the memory array 105 for functional mode operation. For example, the memory array 105 may be powered off or in a low power mode before being activated by the memory enable signal 216. In response to the assertion of the memory enable signal 216, the memory array 105 is fully powered. As defined herein, a signal is considered asserted when it is logic true, regardless of whether the logic true state is represented by an active high or active low convention. In an active high convention, a signal is asserted by being charged to the supply voltage. In an active low convention, a signal is asserted by being discharged to ground. During the functional mode, write operations to the memory array 105 and subsequent read operations from the memory array 105 both occur, as discussed with respect to Figure 1A The binary zero value of the mode 0 signal controls the multiplexer 255 to select a test vector retrieved from the memory array 105. Similarly, the binary zero of the mode 1 signal controls the multiplexer 260 to select an output signal from the multiplexer 255.

[0025] In the functional mode, the concurrent mode enable signal 221 from the AND gate 220 processing the two mode signals will be de-asserted. The de-asserted concurrent mode enable signal 221 from the NAND gate 215 controls the multiplexer 265 to select an output signal from the multiplexer 260. During the functional mode, the test vector retrieved from the memory array 105 will thus flow through the multiplexers 255, 260, and 265 to form an output data stream (tdo) to any system controlling the memory 200. This control system may be integrated into an integrated circuit having the memory 200.

[0026] The concurrent mode enable signal 221 drives OR gate 235, OR gate 225, and OR gate 230. OR gate 235 also receives the mode 0 signal. The output signal of OR gate 235 controls whether the error detection circuit 115 is activated. Since both the concurrent mode enable signal 221 and the mode 0 signal to OR gate 235 are de-asserted during the functional mode, the error detection circuit 115 is not activated. Similarly, OR gate 225 receives the mode 1 signal and the concurrent mode enable signal 221. The output signal of OR gate 225 controls whether the redundancy enable circuit 110 is activated. Since the output signal from OR gate 225 is de-asserted during the functional mode due to the de-assertion of both the mode 1 signal and the concurrent mode enable signal 221, the redundancy enable circuit 110 is not activated during the functional mode.

[0027] Although the error detection circuit 115 is not activated during the functional operation mode, its state changes in the diagnostic operation mode. During the diagnostic operation mode, the mode 0 signal has a logic 1 value. The asserted mode 0 signal propagates through OR gate 235 to activate the error detection circuit 115. During the functional operation mode, the error detection circuit 115 records the test vectors written to the memory array 105. When activated in the diagnostic operation mode, the error detection circuit 115 is configured to compare the test vectors it recorded with the corresponding retrieved test vectors read from the memory array 105 to detect any errors. Similarly, the error detection circuit 115 is also configured to identify the features (e.g., faulty columns) in the memory array 105 that cause errors during the diagnostic operation mode. The assertion of the mode 0 signal causes multiplexer 255 to select the output signal from the error detection circuit 115. Multiplexers 260 and 265 continue to operate as discussed for the functional operation mode during the diagnostic operation mode because the mode 1 signal has a logic 0 value in both operation modes. The error detection circuit 115 can thus transmit the identity of the faulty features to an external controller (not shown) through multiplexers 255, 260, and 265. Since both the concurrent mode enable signal 221 and the mode 1 signal are de-asserted during the diagnostic operation mode, the output signal of OR gate 225 will be de-asserted, causing the redundancy enable circuit 110 to be not activated during the diagnostic operation mode. The memory enable signal 216 is asserted during the diagnostic operation mode, enabling the memory array 105 to be active.

[0028] When the mode 1 signal is logic 1 and the mode 0 signal is logic 0, the repair operation mode is active. The asserted value of the mode 1 signal propagates through the OR gate 225 to activate the redundant enable circuit 110. Similarly, the memory enable signal 216 is asserted during the repair operation mode, enabling the memory array 105 to be active. Activating the redundant enable circuit 110 during the repair operation mode causes the redundant enable circuit 110 to replace the faulty feature (if any) identified during the diagnostic operation mode. For example, the redundant enable circuit 110 may replace a faulty column (not shown) with a redundant column 210. In an alternative embodiment, a faulty row may be replaced by a redundant row (not shown). The redundant enable circuit 110 conveys an acknowledgement of the activation of the redundant feature by transmitting an output signal to an external controller. To this end, the asserted mode 1 signal controls the multiplexer 260 to select the output signal from the redundant enable circuit 110. Subsequently, the de-asserted concurrent mode enable signal 221 controls the multiplexer 265 to select the output signal of the redundant enable circuit 110, which is routed through the multiplexer 265 to drive the output data stream accordingly. The AND gate 220 de-asserts the concurrent mode enable signal 221 during the repair operation mode. Since both the concurrent mode enable signal 221 and the mode 0 signal are de-asserted during the repair operation mode, the output signal of the OR gate 235 will be de-asserted to keep the error detection circuit 115 inoperative during the repair operation mode.

[0029] In the concurrent operation mode, both the mode 1 signal and the mode 0 signal are asserted to a logic 1 value. The AND gate 220 thus asserts the concurrent mode enable signal 221 during the concurrent operation mode. The asserted concurrent mode enable signal 221 is received by the OR gates 225, 230, and 235. The output signal of each of the OR gates 225, 230, and 235 may each be represented as an activation signal. For example, the activation signal from the OR gate 225 activates the operation of the redundant enable circuit 110. Similarly, the activation signal from the OR gate 230 activates the operation of the memory array 105. Finally, the activation signal from the OR gate 235 activates the operation of the error detection circuit 115. Accordingly, the redundant enable circuit 110, the memory array 105, and the error detection circuit 115 will all be concurrently activated in the concurrent operation mode. A timeline of an example concurrent operation mode is shown in Figure 2Bis shown. The write operation starts at time t1 and ends at time t2. During this write operation, one or more test vectors are written to the memory array 105. The error detection circuit 115 also records the test vectors during this write operation. The read operation starts at time t2 and ends at time t3 to read the test vectors from the memory array 105. Concurrent with the read operation is the error detection operation, during which the error detection circuit 115 compares the recorded test vectors with the retrieved test vectors read from the memory array 105. If the comparison indicates a difference, the error or fault in the memory that caused the difference is isolated in an error isolation operation performed by the error detection circuit 115 that occurs concurrently with the read operation. Finally, the redundancy enable circuit 110 replaces the faulty feature with a redundant feature in a redundancy enable operation that also occurs concurrently with the read operation from time t2 to time t3. From time t3 to time t4, a final read / write operation is performed to confirm the success of the repair. Thus, the concurrent operations are advantageously completed at time t4, while the Figure 1B conventional sequential operations discussed can extend to time t9. At this point, it will be understood that Figure 1B and Figure 2B have substantially the same time scale.

[0030] During the concurrent operation mode, the test vectors read from the memory array 105 during the read operation will pass through the output data stream. However, this read operation occurs concurrently with the error detection and the identification of the faulty features in the memory array 105 performed by the error detection circuit 115 that also uses the output data stream. Similarly, the read operation occurs concurrently with the repair operation mode, in which the redundancy enable circuit 110 uses the output data stream to confirm that the faulty features have been replaced. To prevent conflicts between the output signals from the memory array 105 and the output signals from the error detection circuit 115 and the redundancy enable circuit 110, all of these output signals are received by the sequencer 250, which sorts them during the concurrent operation mode to prevent conflicts in the output data stream. In response to the assertion of the concurrent mode enable signal 221, the resulting output signals from the sequencer 250 are selected by the multiplexer 265.

[0031] A flowchart of an example concurrent operation mode is in Figure 3Shown in. The method includes operation 300: activating an error detection circuit to compare a test vector read from a memory cell array with a recorded test vector to identify a fault signature in the memory cell array. Activating the error detection circuit 115 in the concurrent memory 200 by the concurrent mode enable signal 221 is an example of operation 300. Additionally, the method includes operation 305, which occurs during the activation of the error detection circuit and includes activating a redundancy enable circuit to replace the fault signature with a redundancy signature. Activating the redundancy enable circuit 110 in the concurrent memory 200 by the concurrent mode enable signal 221 is an example of operation 305.

[0032] Memories having the advantageous concurrent operation mode disclosed herein can be incorporated into a variety of electronic systems. For example, as Figure 4 shown, the cellular phone 400, laptop computer 405, and tablet PC 410 can all include a concurrent mode memory according to the present disclosure. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers can also be configured with a memory constructed according to the present disclosure.

[0033] It should be understood that many modifications, substitutions, and variations can be made to the materials, devices, configurations, and methods of use of the devices of the present disclosure without departing from the scope of the present disclosure. In view of this, the scope of the present disclosure should not be limited to the scope of the specific embodiments shown and described herein as they are only some examples thereof, but rather, the scope of the present disclosure should be commensurate in full with the scope of the appended claims and their functional equivalents.

Claims

1. A memory, comprising: A memory cell array; An error detection circuit configured to detect an error in the memory cell array and identify a fault signature in the memory cell array that includes the error, wherein the error detection circuit is configured to be active in response to an assertion of a first mode signal and inactive in response to a de-assertion of the first mode signal; A redundancy enable circuit configured to replace the fault signature with a redundancy signature, wherein the redundancy enable circuit is configured to be active in response to an assertion of a second mode signal and inactive in response to a de-assertion of the second mode signal; And A first logic gate configured to process the first mode signal and the second mode signal to generate a concurrent mode signal, wherein the memory cell array, the redundancy enable circuit, and the error detection circuit are each further configured to be active simultaneously in response to an assertion of the concurrent mode signal.

2. The memory according to claim 1, wherein an output signal from the memory cell array is a retrieved test vector for error detection, and wherein the error detection circuit is further configured to compare the retrieved test vector with a recorded test vector to detect the error.

3. The memory according to claim 1, wherein an output signal from the error detection circuit includes an identification of the fault signature.

4. The memory according to claim 1, wherein an output signal from the redundancy enable circuit includes a confirmation of the replacement of the fault signature with the redundancy signature.

5. The memory according to claim 1, wherein the redundancy signature includes a redundant column for the memory cell array.

6. The memory according to claim 1, further comprising: An arbiter configured to order an output signal from the memory cell array, an output signal from the error detection circuit, and an output signal from the redundancy enable circuit during a concurrent operation mode in which the concurrent mode signal is asserted.

7. The memory according to claim 1, wherein the first logic gate is an AND gate.

8. The memory according to claim 6, further comprising a second logic gate configured to process the first mode signal and the second mode signal to generate a memory enable signal, wherein the memory cell array is configured to be active in response to an assertion of the memory enable signal.

9. The memory according to claim 8, wherein the second logic gate is a NAND gate.

10. The memory according to claim 8, further comprising: A first multiplexer configured to select between the output signal from the memory cell array and the output signal from the error detection circuit in response to the first mode signal.

11. The memory according to claim 10, further comprising: A second multiplexer configured to select between the output signal from the redundancy enabling circuit and the output signal from the first multiplexer in response to the second mode signal.

12. The memory of claim 11, further comprising: A third multiplexer configured to select between the output signal from the second multiplexer and the output signal from the sequencer in response to the concurrent mode signal.

13. The memory of claim 8, further comprising: A third logic gate configured to process the concurrent mode signal and the second mode signal together to provide an activation signal to the redundancy enabling circuit.

14. The memory of claim 13, further comprising: A fourth logic gate configured to process the memory enable signal and the concurrent mode signal together to provide an activation signal to the memory cell array.

15. The memory of claim 14, further comprising: A fifth logic gate configured to process the concurrent mode signal and the first mode signal together to provide an activation signal to the error detection circuit.

16. The memory of claim 15, wherein the third logic gate, the fourth logic gate, and the fifth logic gate each comprise an OR gate.

17. A method for a concurrent operation mode of a memory, comprising: Asserting a concurrent mode signal to start a concurrent operation mode in response to a simultaneous assertion of a first mode signal and a second mode signal; During the concurrent operation mode, activating an error detection circuit to compare a test vector read from a memory cell array with a recorded test vector to identify a fault signature in the memory cell array, and simultaneously activating a redundancy enabling circuit to replace the fault signature with a redundancy signature; Asserting the first mode signal while de-asserting the second mode signal to start a diagnostic operation mode; And During the diagnostic operation mode, activating the error detection circuit when the redundancy enabling circuit is in an inactive state.

18. The method of claim 17, further comprising: Asserting the second mode signal while de-asserting the first mode signal to start a repair operation mode; And During the repair operation mode, activating the redundancy enabling circuit when the error detection circuit is in an inactive state.

19. The method of claim 17, further comprising: During the activation of the error detection circuit and the redundancy enabling circuit, sorting a first output signal from the memory cell array, a second output signal identifying the fault signature, and a third output signal confirming the replacement of the fault signature with the redundancy signature.

20. A concurrent memory, comprising: A memory array; An error detection circuit configured to identify a fault signature in response to an assertion of a first mode signal; And A redundancy enabling circuit configured to replace the fault signature with a replacement signature in response to an assertion of a second mode signal, Wherein, in response to the simultaneous assertion of the first mode signal and the second mode signal, the error detection circuit identifies the fault feature and the redundancy enabling circuit replaces the fault feature concurrently.

21. The concurrent memory according to claim 20, wherein the fault feature is a column of bit cells in the memory array.

22. The concurrent memory according to claim 20, further comprising: A sequencer configured to sequence output signals from the memory array, output signals from the error detection circuit, and output signals from the redundancy enabling circuit.

23. The concurrent memory according to claim 20, wherein the concurrent memory is included in a cellular phone.

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