A thermally tuned semiconductor chip and a method for preparing the same

Abstract

An embodiment of the present invention discloses a thermally tunable semiconductor chip and a preparation method thereof. Among them, the thermally tunable semiconductor chip includes: a substrate, and a sacrificial layer and a functional layer stacked on the substrate in sequence; the functional layer is used to transfer heat to the thermal tuning electrode of the thermally tunable semiconductor chip; wherein, a suspension region is formed in the substrate and the sacrificial layer, and the suspension region is a cavity structure that penetrates the sacrificial layer and terminates inside the substrate, so that the functional layer located above the cavity structure is isolated from the remaining part of the substrate below the cavity structure through the suspension region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a thermally tunable semiconductor chip and a preparation method thereof. Background Art

[0002] With the rapid development of the Internet, people's demand for network bandwidth is increasing. Monolithic integrated chips with comprehensive functions, powerful performance, and low power consumption are attracting more and more attention. For example, monolithic integrated tunable lasers are attracting attention as the core chips for future 5G networks and intelligent optical networks. As the transmission rate of coherent transmission networks is getting higher and higher, the system's requirement for the linewidth of lasers is also getting higher. Currently, a typical coherent transmission system requires the linewidth of a tunable laser chip to be below 300KHz. Traditional tunable laser chips are based on electro-injection tuning. Although the tuning speed is very fast, due to the existence of current shot noise and other parasitic noises, it is difficult to reduce the chip linewidth. Generally, the linewidth of such chips is generally above several MHz, which cannot meet the requirements of the coherent transmission system for the chip linewidth. To solve the above problems, thermally tunable chips based on the thermal effect have attracted the attention of device manufacturers. Since in the thermal effect, the high-frequency noise component is very small, the chip linewidth can be greatly improved.

[0003] However, for thermally tunable chips based on the thermal effect, since there is a certain distance between the functional layer and the thermal tuning electrode, and there is a physical connection between the chip functional layer and the substrate, the thermal power is very easy to dissipate through the substrate, and the thermal tuning efficiency is quite low. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a thermally tunable semiconductor chip and a preparation method thereof to solve at least one problem in the background art.

[0005] To achieve the above object, the technical solution of the present invention is realized as follows:

[0006] An embodiment of the present invention provides a thermally tunable semiconductor chip, including: a substrate, and a sacrificial layer and a functional layer sequentially stacked on the substrate; the functional layer is used to transfer heat to the thermal tuning electrode of the thermally tunable semiconductor chip; wherein,

[0007] A suspension area is formed in the substrate and the sacrificial layer, and the suspension area is a cavity structure that penetrates the sacrificial layer and terminates inside the substrate, so that the functional layer above the cavity structure is isolated from the remaining part of the substrate below the cavity structure through the suspension area.

[0008] In the above solution, the lower surface of the sacrificial layer contacts the upper surface of the substrate.

[0009] In the above solution, it further includes:

[0010] A support layer stacked on the substrate and located between the sacrificial layer and the functional layer;

[0011] The suspended area specifically extends from below the upper surface of the support layer, penetrates through the sacrificial layer, and terminates inside the substrate.

[0012] In the above solution, the suspended area includes a first part located in the substrate, a second part located in the sacrificial layer, and a third part located in the support layer, and the depth of the first part is greater than the sum of the depths of the second part and the third part.

[0013] In the above solution, the thickness of the support layer is greater than the thickness of the sacrificial layer; the depth of the third part of the suspended area located in the support layer is greater than the depth of the second part of the suspended area located in the sacrificial layer.

[0014] In the above solution, the material of the support layer is the same as the material of the substrate.

[0015] In the above solution, the materials of the support layer and the substrate are both InP.

[0016] In the above solution, the functional layer includes a first sub-functional layer, and the lower surface of the first sub-functional layer contacts the upper surface of the support layer and is used as an etching stop layer in the process of etching the support layer to form the suspended area.

[0017] In the above solution, it further includes:

[0018] At least two openings communicating with the suspended area, and the suspended area is formed by an etching process performed through at least two of the openings;

[0019] Between any two of the at least two openings, there are unremoved partial support layers and unremoved partial sacrificial layers.

[0020] In the above solution, the material of the sacrificial layer includes at least one of the following: InGaAs, InGaAsP, AlGaInAs.

[0021] Another aspect of the embodiments of the present invention provides a method for manufacturing a thermally tunable semiconductor chip, and the method includes:

[0022] Providing a substrate, and sequentially forming a sacrificial layer and a functional layer on the substrate; the functional layer is used to transfer heat to the thermal tuning electrode of the thermally tunable semiconductor chip;

[0023] Forming a through hole, the through hole penetrating through the functional layer and exposing a part of the sacrificial layer;

[0024] Etch the sacrificial layer and the substrate to form a suspended area; the suspended area is a cavity structure that penetrates the sacrificial layer and terminates inside the substrate, so that the functional layer above the cavity structure is isolated from the remaining part of the substrate below the cavity structure through the suspended area.

[0025] In the above solution, forming the sacrificial layer on the substrate specifically includes: directly forming the sacrificial layer on the substrate so that the lower surface of the sacrificial layer contacts the upper surface of the substrate.

[0026] In the above solution, sequentially forming a sacrificial layer and a functional layer on the substrate specifically includes: forming the sacrificial layer on the substrate, forming a support layer on the sacrificial layer, and forming the functional layer on the support layer;

[0027] The through hole also penetrates the support layer;

[0028] Forming the suspended area specifically includes: etching the sacrificial layer, the support layer and the substrate; the suspended area specifically extends from below the upper surface of the support layer, penetrates the sacrificial layer, and terminates inside the substrate.

[0029] In the above solution, after forming the through hole, the method further includes:

[0030] Form a mask layer that at least covers the side wall of the through hole;

[0031] Form an opening at the bottom end of the mask layer, and the opening exposes a part of the sacrificial layer.

[0032] In the above solution, forming the suspended area specifically includes:

[0033] Use a first etching process to etch the sacrificial layer to expose a part of the upper surface of the substrate and a part of the lower surface of the support layer;

[0034] Use a second etching process to etch the substrate and the support layer to form the suspended area.

[0035] In the above solution, the suspended area includes a first part located in the substrate, a second part located in the sacrificial layer, and a third part located in the support layer, and the depth of the first part is greater than the sum of the depths of the second part and the third part.

[0036] In the above solution, the sacrificial layer has a first thickness, the support layer has a second thickness, and the second thickness is greater than the first thickness;

[0037] Forming the suspension region specifically includes: etching the support layer to a depth greater than the first thickness, so that the formed suspension region has a greater depth in the third part located within the support layer than in the second part located within the sacrificial layer.

[0038] In the above solution, the material of the support layer is the same as that of the substrate.

[0039] In the above solution, the materials of both the support layer and the substrate are InP.

[0040] In the above solution, forming the support layer on the sacrificial layer and forming the functional layer on the support layer specifically includes: after forming the support layer, forming a first sub-functional layer of the functional layer on the support layer, and the lower surface of the first sub-functional layer contacts the upper surface of the support layer;

[0041] Forming the suspension region includes: using the first sub-functional layer as an etching stop layer when etching the support layer.

[0042] In the above solution, forming the through holes includes forming at least two through holes;

[0043] In the step of etching the sacrificial layer, the support layer, and the substrate, the portions of the support layer and the sacrificial layer between any two of at least two through holes are not completely removed.

[0044] In the above solution, the material of the sacrificial layer includes at least one of the following: InGaAs, InGaAsP, AlGaInAs.

[0045] The thermally tunable semiconductor chip and its manufacturing method provided by the embodiments of the present invention, wherein the thermally tunable semiconductor chip includes: a substrate, and a sacrificial layer and a functional layer stacked on the substrate in sequence; the functional layer is used to transfer heat to the thermal tuning electrode of the thermally tunable semiconductor chip; a suspension region is formed in the substrate and the sacrificial layer, and the suspension region is a cavity structure that penetrates the sacrificial layer and terminates inside the substrate, so that the functional layer above the cavity structure is isolated from the remaining part of the substrate below the cavity structure through the suspension region. Thus, the suspension region has a relatively large depth, which not only includes a partial depth greater than the thickness of the sacrificial layer obtained by penetrating the sacrificial layer, but also includes the depth of the part located in the substrate. Therefore, the functional layer located on the suspension region can be suspended on the substrate and has a relatively large air gap with the substrate, thereby having good heat insulation, effectively reducing the occurrence of heat dissipation through the substrate, and thus conducting most of the heat to the thermal tuning electrode, improving the thermal tuning efficiency of the chip.

[0046] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A top view of a thermally tuned semiconductor chip provided for an embodiment of the present invention and cross-sectional views along two dashed line positions in the top view;

[0048] Figure 2 A top view of a thermally tuned semiconductor chip provided for another embodiment of the present invention and cross-sectional views along two dashed line positions in the top view;

[0049] Figure 3 A schematic flow chart of a method for manufacturing a thermally tuned semiconductor chip provided for an embodiment of the present invention;

[0050] Figures 4a to 4d A schematic cross-sectional view of the structure during the manufacturing process of a thermally tuned semiconductor chip provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0051] Exemplary embodiments disclosed of the present invention will be described in more detail hereinafter with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention disclosed can be fully conveyed to those skilled in the art.

[0052] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without one or more of these details. In other instances, some well-known technical features are not described to avoid obscuring the present invention; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0053] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0054] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below may be denoted as a second element, component, region, layer or section without departing from the teachings of the present invention. And when discussing a second element, component, region, layer or section, it does not imply that a first element, component, region, layer or section necessarily exists in the present invention.

[0055] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "on" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientation) and the spatial descriptors used herein are interpreted accordingly.

[0056] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0057] To thoroughly understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution of the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other embodiments.

[0058] Due to the thermal tuning chip based on the thermal effect, there is a certain distance between the functional layer and the thermal tuning electrode, and the time required for heat conduction to the thermal tuning electrode is relatively long; and there is a physical connection between the functional layer and the substrate, resulting in easy dissipation of thermal power through the substrate. To solve the above technical problems, as a feasible solution: a ternary material layer, such as an InGaAs layer, is pre-grown between the substrate and the functional layer, and then this layer is removed by lateral etching, so that the chip functional layer is suspended above the substrate. However, since it is difficult to grow the ternary material InGaAs that is lattice-matched with the substrate, especially it is difficult to grow a relatively thick InGaAs material, and usually only a few hundred nanometers can be grown. In addition, in the related art, a lower limit layer is also provided between the ternary material layer and the substrate. When the ternary material layer is laterally etched, the lower limit layer will prevent the etching reaction from proceeding downward (i.e., in the direction towards the substrate). Therefore, the suspension gap formed between the substrate and the functional layer by lateral etching of the ternary material layer is very small. And a thicker InGaAs material will cause a significant reduction in the quality of the chip material, especially affecting the quality of the quantum well structure in the active region.

[0059] Therefore, the further improvement of the chip thermal tuning efficiency and the tuning response speed is restricted. When the chip thermal power is certain, the thermal power is very easy to be dissipated through the substrate, and only a small amount of heat is conducted to the thermal tuning electrode, resulting in the technical problem of low chip thermal tuning efficiency.

[0060] Therefore, it is urgent to solve the problem of being unable to obtain a larger suspension gap between the substrate and the functional layer.

[0061] Based on this, the embodiments of the present invention first provide a thermal tuning semiconductor chip.

[0062] The thermally tunable semiconductor chip includes: a substrate, and a sacrificial layer and a functional layer sequentially stacked on the substrate; the functional layer is used to transfer heat to the thermal tuning electrode of the thermally tunable semiconductor chip; wherein, a suspension region is formed in the substrate and the sacrificial layer, and the suspension region is a cavity structure that penetrates the sacrificial layer and terminates inside the substrate, so that the functional layer located above the cavity structure is isolated from the remaining part of the substrate below the cavity structure through the suspension region. Thus, the suspension region has a relatively large depth, and this depth not only includes a partial depth greater than the thickness of the sacrificial layer obtained by penetrating the sacrificial layer, but also includes a partial depth located in the substrate. Therefore, the functional layer located on the suspension region can be suspended on the substrate and has a relatively large air gap with the substrate, thereby having good heat insulation, effectively reducing the occurrence of heat dissipation through the substrate, and thus conducting most of the heat to the thermal tuning electrode, improving the thermal tuning efficiency of the chip.

[0063] Next, reference will be made to Figure 1 to describe and explain the thermally tunable semiconductor chip provided by the embodiment of the present invention in more detail.

[0064] Figure 1 The top view of the thermally tunable semiconductor chip provided by an embodiment of the present invention and the cross-sectional views along two dashed line positions in the top view are shown. As shown in the figure, the thermally tunable semiconductor chip includes: a substrate 101, and a sacrificial layer 102, a support layer 103, and a functional layer 105 sequentially stacked on the substrate 101; wherein, a suspension region 109 is formed in the substrate 101, the sacrificial layer 102, and the support layer 103.

[0065] Here, the substrate 101 is a semiconductor substrate, and its material may specifically include InP. The thickness of the substrate 1, for example, is greater than 150 μm.

[0066] It can be understood that the substrate includes a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction perpendicular to the top surface and the bottom surface of the substrate is defined as the Z direction. The Z direction is also the stacking direction of depositing each layer structure on the substrate subsequently, or the height direction of the chip. The plane where the top surface and the bottom surface of the substrate are located, or strictly speaking, the central plane in the thickness direction of the substrate, is determined as the substrate plane; the direction parallel to the substrate plane is the direction along the substrate plane; the Z direction is the direction perpendicular to the substrate plane. Two mutually perpendicular X directions and Y directions are defined in the direction of the substrate plane.

[0067] At least one of the sacrificial layer 102, the support layer 103, and the functional layer 105 can be formed on the substrate 101 by deposition or evaporation.

[0068] The material of the sacrificial layer 102 includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs. The material of the sacrificial layer 102 is different from the material of the substrate 101. As a specific embodiment, the material of the sacrificial layer 102 is InGaAs; the materials of the substrate 101 and the support layer 103 are both InP. The thickness range of the sacrificial layer 102 is 100 nm to 400 nm.

[0069] In a specific embodiment, the lower surface of the sacrificial layer 102 contacts the upper surface of the substrate 101. In other words, there is no other material layer between the sacrificial layer 102 and the substrate 101. Thus, in this embodiment, by omitting the lower confinement layer in the related art, the suspension region extends into the interior of the substrate, thereby increasing the overall depth of the suspension region and improving the thermal insulation of the device.

[0070] In the embodiment where the thermally tunable semiconductor chip further includes the support layer 103, the support layer 103 is stacked on the substrate 101 and is located between the sacrificial layer 102 and the functional layer 105. The material of the support layer 103 may include InP. The material of the support layer 103 may be the same as the material of the substrate 101; the material of the support layer 103 is different from the material of the sacrificial layer 102. The thickness of the support layer 103 is, for example, greater than the thickness of the sacrificial layer 102; the thickness range of the support layer 103 is, for example, 450 nm to 550 nm.

[0071] In this embodiment, the suspension region 109 is specifically a cavity structure that extends from below the upper surface of the support layer 103, penetrates through the sacrificial layer 102, and terminates inside the substrate 101, so that the functional layer 105 above the cavity structure is isolated from the remaining part of the substrate 101 below the cavity structure through the suspension region 109.

[0072] The depth of the suspension region 109 can be between 10 - 15 μm.

[0073] In a specific embodiment, the suspension region 109 includes a first part inside the substrate 101, a second part inside the sacrificial layer 102, and a third part inside the support layer 103, and the depth of the first part is greater than the sum of the depths of the second part and the third part.

[0074] In a specific embodiment, the depth of the third part of the suspension region 109 located within the support layer 103 is greater than the depth of the second part of the suspension region 109 located within the sacrificial layer 102. Thus, the proportion of the first part in the suspension region 109 is the largest; and specifically, the depth of the first part > the depth of the third part > the depth of the second part.

[0075] Please continue to refer to Figure 1 , the cross-section of the suspension region 109 in the direction perpendicular to the substrate plane is hexagonal. The distance between the side walls of the suspension region 109 in the direction parallel to the substrate plane increases from the support layer 103 to the sacrificial layer 102. In an embodiment where the depth of the first part is greater than the sum of the depths of the second part and the third part, the distance between the side walls of the suspension region 109 in the direction parallel to the substrate plane is maximized within the substrate 101 and decreases downward from the maximum position.

[0076] In an embodiment of the present invention, the thickness of the suspension region is much greater than the thickness of the sacrificial layer, so that there is a large gap between the upper and lower surfaces of the suspension region in the direction perpendicular to the chip surface (i.e., perpendicular to the substrate).

[0077] The functional layer 105 is used to transfer heat to the thermal tuning electrode (not shown in the figure) of the thermal tuning semiconductor chip.

[0078] The functional layer 105 may include a first sub-functional layer 1051, the lower surface of the first sub-functional layer 1051 is in contact with the upper surface of the support layer 103, and is used as an etch stop layer in the process of etching the support layer 103 to form the suspension region 109.

[0079] The material of the first sub-functional layer 1051 includes at least one of the following: InGaAs, InGaAsP, AlGaInAs; in other words, the bottom layer structure in the functional layer 105 in contact with the upper surface of the support layer 103 is a material layer of InGaAs, InGaAsP, and / or AlGaInAs. The material of the first sub-functional layer 1051 may be the same as the material of the sacrificial layer 102. The material of the first sub-functional layer 1051 is different from the material of the support layer 103; and, as an etch stop layer for etching the support layer 103, there should be a large etch selectivity between the first sub-functional layer 1051 and the support layer 103 in the etching process.

[0080] The thickness of the first sub-functional layer 1051 is less than the thickness of the support layer 103. In a plane parallel to the substrate 101, the area of the first sub-functional layer 1051 may be greater than or equal to the area of the support layer 103, so that the first sub-functional layer 1051 completely covers the support layer 103.

[0081] In a specific embodiment, the first sub-functional layer 1051 is a quantum well layer.

[0082] The specific structure of the functional layer 105 depends on the actual scenario and may be one of the following: a laser layer structure, a detector layer structure, a modulator layer structure, or a passive waveguide layer structure. As a specific implementation, the functional layer 105 may include a lower waveguide layer (made of, for example, InGaAsP), a waveguide core layer (made of, for example, InGaAsP), and an upper waveguide layer (made of, for example, InGaAsP) from bottom to top along the substrate 101; the functional layer 105 may further include a cladding layer (made of, for example, InP) located on the upper waveguide layer. It may also include an electrode contact layer (made of, for example, InGaAs).

[0083] In an embodiment where the functional layer 105 includes the first sub-functional layer 1051, the lower waveguide layer is located on the first sub-functional layer 1051. The lower waveguide layer may only be located on a part of the first sub-functional layer 1051; in other words, in a part of the region, the functional layer 105 only includes the first sub-functional layer 1051, and in another part of the region, it includes the first sub-functional layer 1051 and other sub-functional layers located on the first sub-functional layer 1051.

[0084] The thermally tunable semiconductor chip may further include a through hole 107 communicating with the suspension region 109. The through hole 107, for example, penetrates through the functional layer 105 and the support layer 103; in an embodiment where the functional layer 105 includes the first sub-functional layer 1051, it also penetrates through the first sub-functional layer 1051.

[0085] A mask layer 106 may also be covered on the side wall of the through hole 107. The mask layer 106 is used to protect the functional layer 105 and the support layer 103 within the mask layer 106 during the etching process for forming the suspension region. The bottom end of the mask layer 106 has an opening 108; the opening 108 penetrates through the mask layer 106 and communicates the through hole 107 and the suspension region 109. The mask layer 106 may also be covered on the functional layer 105, and no specific limitation is made here.

[0086] It should be understood that the opening 108 is located within the through hole 107. Figure 1The case where the opening size of the opening 108 is smaller than the opening size of the through hole 107 is shown; of course, the opening size of the opening 108 can also be equal to the opening size of the through hole 107, or more specifically equal to the opening size of the through hole 107 minus the thickness of the two side walls of the mask layer 106.

[0087] The opening shapes of the through hole 107 and the opening 108 can be circular, square, diamond-shaped or other shapes, which can be designed according to the actual situation and will not be specifically limited here.

[0088] The number of the through holes / the openings corresponding to one suspension area can be more than two. Figure 1 In the corresponding embodiment, the number of the through holes 107 / the openings 108 corresponding to one suspension area 109 is specifically two; and, the two through holes 107 / the openings 108 can be symmetrically arranged on the suspension area 109, and specifically can be symmetrically arranged left and right along the central axis of the suspension area 109.

[0089] Between any two of more than two through holes 107 / the openings 108, there can be a part of the support layer 103 that has not been removed, and there can also be a part of the sacrificial layer 102 that has not been removed; in other words, at least a first part and a second part that expose the functional layer 105 (specifically the first sub-functional layer 1051) are included at the top of the suspension area 109, and there can also be a part of the sacrificial layer 102 and a part of the support layer 103 located between the first part and the second part in a plane parallel to the substrate 101. The thermally tunable semiconductor chip can have a first part of the sacrificial layer 102 and a first part of the support layer 103 on one side of the suspension area 109, a second part of the sacrificial layer 102 and a second part of the support layer 103 on the other side of the suspension area 109, and a third part of the sacrificial layer 102 and a third part of the support layer 103 in the suspension area 109; it should be understood that the sacrificial layer 102 and the support layer 103 of the above three parts are connected through an area not shown in the figure. Thus, the mechanical structure strength of the entire suspension area 109 is increased.

[0090] Therefore, as an optional embodiment of the present application, the thermally tunable semiconductor chip can further include: at least two openings communicating with the suspension area, and the suspension area is formed by an etching process performed through at least two openings; there is a part of the support layer that has not been removed and a part of the sacrificial layer that has not been removed between any two of the at least two openings.

[0091] The cross-section of the part of the support layer that has not been removed and the part of the sacrificial layer that has not been removed in a direction perpendicular to the substrate is an inverted trapezoid.

[0092] The substrate 101, the sacrificial layer 102, and the support layer 103 are disposed along the circumferential direction of the suspension region 109, and form the side wall and the bottom wall of the suspension region 109, so that the functional layer 105 is suspended on the substrate 101. Since there is a large air isolation gap between the functional layer 105 and the substrate 101, the heat dissipated from the substrate 101 can be reduced, thereby improving the thermal tuning efficiency of the thermal tuning semiconductor chip.

[0093] Next, please refer to Figure 2 . Figure 2 The top view of the thermal tuning semiconductor chip provided by another embodiment of the present invention and the cross-sectional views along two dotted line positions in the top view.

[0094] Different from Figure 1 the corresponding embodiment, in this embodiment, the case where the thermal tuning semiconductor chip includes multiple suspension regions 109 is specifically introduced. Correspondingly, the thermal tuning semiconductor chip includes multiple groups of through holes (such as 107, 107' in the figure) and openings (such as 108, 108' in the figure); since the openings correspond to the through holes one by one, hereinafter, only the through holes will be described. The multiple groups of through holes communicating with the multiple suspension regions 109 (such as between 107 and 107' in the figure) can be arranged at equal intervals or unequal intervals, depending on the actual situation. The multiple suspension regions 109 can be arranged in an array, so that the multiple groups of through holes / multiple groups of openings can also be arranged in an array.

[0095] As Figure 2 shown in the top view, two through holes in the same row communicate with the corresponding suspension region of that row, and two through holes in another row communicate with the corresponding suspension region of that row. The sacrificial layer 102, the support layer 103, and the functional layer 105 are continuous in the direction of lateral extension (X direction) of each layer between the through holes in adjacent rows. The sacrificial layer 102, the support layer 103, and the functional layer 105 are continuous in the direction of longitudinal extension (Y direction) of each layer between the through holes in the same row, ensuring that only the positions of the substrate 101, the sacrificial layer 102, and the support layer 103 corresponding to the suspension region 109 on the thermal tuning semiconductor chip are hollowed out, while the substrate 101, the sacrificial layer 102, and the support layer 103 in the circumferential direction of the suspension region 109 are continuous in the direction of extension of the substrate plane. After the suspension region 109 is formed by etching, the suspension region 109 is continuous in the direction of extension on the surface of the thermal tuning semiconductor chip and is limited to the region near the through holes and the openings; the structural layers (mask layer 106, functional layer 105, the remaining part of the support layer 103, the sacrificial layer 102, and the substrate 101) that are not etched in the region are connected to the structures outside the region, so as to ensure that the functional layers 105 can be connected together and then suspended on the substrate 101.

[0096] In some embodiments, the suspended regions corresponding to the through-holes located in different rows may also be connected. Thus, the overall connected suspended region formed can be understood as including multiple sub-suspended regions. In embodiments where the suspended region includes multiple (more than two) sub-suspended regions, an unremoved portion of the support layer may be included between two adjacent sub-suspended regions; in addition, an unremoved portion of the sacrificial layer may also be included. In other words, in the arrangement direction (Y direction) of the multiple sub-suspended regions, the top end of the suspended region at least includes a first part and a third part that expose the functional layer (specifically, the first sub-functional layer), and on a plane parallel to the substrate, an unremoved portion of the support layer and an unremoved portion of the sacrificial layer may also be included between the first part and the third part. Among them, the unremoved portion of the support layer and the unremoved portion of the sacrificial layer located between the first part and the third part may be referred to as a "cantilever", and the cantilever is similar to the unremoved portion of the support layer and the unremoved portion of the sacrificial layer located between two through-holes in the X direction, and can also play a role in enhancing mechanical strength. Thus, the width of the suspended region in the first direction (X direction) parallel to the substrate plane is less than the width in the second direction (Y direction) parallel to the substrate plane, and the second direction is perpendicular to the first direction.

[0097] Embodiments of the present invention also provide a method for manufacturing a thermally tunable semiconductor chip; specifically, please refer to the attached Figure 3 . As shown in the figure, the method includes the following steps:

[0098] Step 301: Provide a substrate, and sequentially form a sacrificial layer and a functional layer on the substrate; the functional layer is used to transfer heat to the thermal tuning electrode of the thermally tunable semiconductor chip.

[0099] Step 302: Form through-holes, and the through-holes penetrate the functional layer and expose a part of the sacrificial layer.

[0100] Step 303: Etch the sacrificial layer and the substrate to form a suspended region; the suspended region is a cavity structure that penetrates the sacrificial layer and terminates inside the substrate, so that the functional layer above the cavity structure is isolated from the remaining part of the substrate below the cavity structure through the suspended region.

[0101] Next, with reference to Figures 4a to 4d the schematic cross-sectional view of the structure in the manufacturing process of the thermally tunable semiconductor chip, the thermally tunable semiconductor chip and its manufacturing method provided by the embodiments of the present invention will be further described in detail.

[0102] First, please refer to Figure 4a . Provide a substrate 101, and sequentially form a sacrificial layer 102 and a functional layer 105 on the substrate.

[0103] In a specific embodiment, forming the sacrificial layer 102 on the substrate 101 specifically includes: directly forming the sacrificial layer 102 on the substrate 101 so that the lower surface of the sacrificial layer 102 contacts the upper surface of the substrate 101. In other words, no other material layer is included between the sacrificial layer 102 and the substrate 101. Thus, in this embodiment, by omitting the lower limit layer in the related art, the subsequent process of etching the substrate using the second etching process is easier to implement, and the formed suspended region extends into the substrate, increasing the overall depth of the suspended region and improving the heat insulation of the device.

[0104] In a specific embodiment, forming the sacrificial layer 102 and the functional layer 105 on the substrate 101 in sequence specifically includes: forming the sacrificial layer 102 on the substrate 101, forming the support layer 103 on the sacrificial layer 102, and forming the functional layer 105 on the support layer 103. In other words, the sacrificial layer 102, the support layer 103, and the functional layer 105 are formed on the substrate 101 in sequence.

[0105] In a specific embodiment, forming the support layer 103 on the sacrificial layer 102 and forming the functional layer 105 on the support layer 103 specifically includes: after forming the support layer 103, forming the first sub-functional layer 1051 of the functional layer 105 on the support layer 103, with the lower surface of the first sub-functional layer 1051 contacting the upper surface of the support layer 103; forming the functional layer 105 on the first sub-functional layer 1051; thus, in the subsequent step of forming the suspended region, when etching the support layer 103, the first sub-functional layer 1051 is used as an etching stop layer.

[0106] Next, taking a thermally tunable semiconductor chip as a passive waveguide as an example for explanation. In this embodiment, first, a sacrificial layer 102 is formed on a substrate 101. The material of the sacrificial layer 102 is, for example, InGaAsP, and the thickness is, for example, 0.02 μm ± 0.05 μm; the material of the support layer 103 is, for example, InP, and the thickness is, for example, 1 μm ± 0.05 μm; the material of the first sub-functional layer 1051 is, for example, InGaAs, and the thickness is, for example, 0.2 μm ± 0.05 μm; the functional layer 105 further includes, for example, a lower waveguide layer, a waveguide core layer, a waveguide core layer, a cladding layer, and an electrode contact layer located on the first sub-functional layer 1051; the material of the lower waveguide layer is, for example, InGaAsP, and the thickness is, for example, 0.1 μm ± 0.05 μm; the material of the waveguide core layer is, for example, InGaAsP, and the thickness is, for example, 0.2 μm ± 0.05 μm; the material of the waveguide core layer is, for example, InGaAsP, and the thickness is, for example, 0.1 μm ± 0.05 μm; the material of the cladding layer is, for example, InP, and the thickness is, for example, 1.5 μm ± 0.05 μm; and the material of the electrode contact layer is, for example, InGaAs, and the thickness is, for example, 0.2 μm ± 0.05 μm.

[0107] The above layers can be formed on the substrate 101 by deposition or evaporation. After the epitaxy of the above layers is completed, the fabrication of the suspension region 109 can be carried out.

[0108] To form the suspension region 109, a patterned first mask layer 110 can be formed on the above layers. The first mask layer 110 defines the positions for subsequently forming through-holes 107. The patterning of the first mask layer 110 can be achieved by photolithography.

[0109] Next, please refer to Figure 4b . Form through-holes 107 that penetrate the functional layer 105 and expose a part of the sacrificial layer 102.

[0110] In a specific embodiment, through-holes 107 that penetrate the functional layer 105 and the support layer 103 are formed. The through-holes 107 expose a part of the sacrificial layer 102; that is, the through-holes 107 also penetrate the support layer 103.

[0111] In specific preparation, etching holes (i.e., through holes 107) extending along the direction close to the substrate 101 are formed on the left and right sides of the thermal tuning semiconductor chip. Among them, the etching holes penetrate through the mask 106, the functional layer 105, and the support layer 103 in sequence along the direction close to the substrate 101. The through hole 107 may also pass through part of the sacrificial layer 102; that is, the through hole 107 may penetrate into the sacrificial layer 102 (this situation is not shown in the figure). Thus, the corresponding etching hole pattern is defined on the surface of the thermal tuning semiconductor chip by lithography, and etching is performed on the left and right sides of the thermal tuning semiconductor chip based on the defined etching hole pattern, such as reactive ion (RIE) etching, so as to form etching holes extending along the direction close to the substrate on the left and right sides of the thermal tuning semiconductor chip. Among them, the opening of the etching hole may be square, circular, or other shapes.

[0112] Next, please refer to Figure 4c . The sacrificial layer 102 is etched to form a part of the suspended area, that is, the second part.

[0113] Specifically, after the through hole 107 penetrating through the functional layer 105 and the support layer 103 is formed in Figure 4b , the method further includes: forming a mask layer 106, and the mask layer 106 at least covers the side wall of the through hole 107. In addition, the mask layer 106 may also cover the top surface of the thermal tuning semiconductor chip, such as covering the functional layer 105.

[0114] Next, an opening 108 is formed at the bottom end of the mask layer 106, and the opening 108 exposes part of the sacrificial layer 102.

[0115] It should be understood that the opening 108 is located within the through hole 107. Figure 4c shows the situation where the opening size of the opening 108 is smaller than the opening size of the through hole 107; of course, the opening size of the opening 108 may also be equal to the opening size of the through hole 107, or more specifically equal to the opening size of the through hole 107 minus the thickness of the two side walls of the mask layer 106.

[0116] In a specific preparation process, etching holes (i.e., opening 108) extending in the direction close to the substrate are formed on the left and right sides of the thermally tunable semiconductor chip, and the etching holes penetrate the mask in the direction close to the substrate. In this embodiment, the first mask layer 110 is removed using an HF acid etching solution, and the mask layer 106 (also referred to as the second mask layer) is regrown. The corresponding etching hole pattern is defined on the surface of the thermally tunable semiconductor chip by photolithography, and RIE etching is performed on the left and right sides of the thermally tunable semiconductor chip based on the defined etching hole pattern, so as to form etching holes extending in the direction close to the substrate on the left and right sides of the thermally tunable semiconductor chip. Among them, the opening of the etching hole can be square, circular, or other shapes.

[0117] Next, the sacrificial layer 102 is etched using a first etching process, exposing a part of the upper surface of the substrate 101 and a part of the lower surface of the support layer 103.

[0118] Here, the first etching process can be a wet etching process. The sacrificial layer 102 can be etched using a first etching solution. In an actual application scenario, the composition of the sacrificial layer 102 includes InGaAs material. Part of the sacrificial layer 102 is removed using the first etching solution, and the first etching solution is injected into the thermally tunable semiconductor chip through the opening 108. The first etching solution selectively etches the InGaAs material in the sacrificial layer 102 laterally, so that part of the sacrificial layer 102 is removed. Among them, the first etching solution can be a sulfuric acid-based etching solution, that is, the etching solution used in the first etching process can include a sulfuric acid-based solution; the sulfuric acid-based etching solution selectively etches the InGaAs material and has no etching effect on the InP material. Therefore, in an embodiment where the substrate 101 and the support layer 103 are made of InP, the substrate 101 and the support layer 103 can remain in a non-etched state.

[0119] The opening size of the sacrificial layer 102 formed after etching is larger than the opening size of the through hole 107.

[0120] In a specific embodiment, forming the through hole includes forming at least two through holes; the corrosion regions corresponding to two adjacent through holes 107 are not connected, that is, there is still the sacrificial layer 102 that has not been removed between two adjacent through holes 107.

[0121] Next, please refer to Figure 4d . Further etch the support layer 103 and the substrate 101 to finally form the suspended region 109.

[0122] Specifically, after etching the sacrificial layer using the first etching process, the second etching process is used to etch the substrate to form the suspension region. In an embodiment including the support layer, the method further includes etching the support layer using the second etching process; in other words, forming the suspension region specifically includes: etching the sacrificial layer, the support layer, and the substrate; thus, the formed suspension region specifically extends from below the upper surface of the support layer, penetrates through the sacrificial layer, and terminates inside the substrate.

[0123] Here, the second etching process can be a wet etching process. The support layer 103 and the substrate 1 may be etched using a second etching solution. In an actual application scenario, the second etching solution is injected into the thermally tunable semiconductor chip through the left and right etching holes and the channels connecting the etching holes. The second etching solution selectively etches the InP material in the substrate and the support layer, removing part of the substrate and the support layer, thereby forming a suspension region. Among them, the second etching solution can be a hydrochloric acid-based etching solution, that is, the etching solution used in the second etching process may include a hydrochloric acid-based solution; since the hydrochloric acid-based solution cannot etch the InGaAsP material, this step of etching will stop below the first sub-functional layer, protecting the original layers of the thermally tunable semiconductor chip from being affected by etching. At the same time, the thickness of the substrate layer is much larger than the thickness of other layers, so by controlling the etching time, the structural stability of the thermally tunable semiconductor chip can be ensured.

[0124] In actual applications, the etching of the InP material by the second etching solution used has the characteristic of being able to etch at a fixed etching angle.

[0125] Thus, the formed suspension region 109 is a cavity structure that extends from below the upper surface of the support layer 103, penetrates through the sacrificial layer 102, and terminates inside the substrate 101, so that the functional layer 105 above the cavity structure is isolated from the remaining part of the substrate 101 below the cavity structure through the suspension region 109.

[0126] In a specific embodiment, forming the sacrificial layer, the support layer, and the functional layer specifically includes: forming a sacrificial layer with a first thickness, and forming a support layer with a second thickness on the sacrificial layer. In this way, the sacrificial layer has a first thickness and the support layer has a second thickness; the second thickness is greater than the first thickness; correspondingly, forming the suspension region specifically includes: the etching depth of the support layer is greater than the first thickness, so that the depth of the third part of the formed suspension region located in the support layer is greater than the depth of the second part located in the sacrificial layer.

[0127] In this embodiment, first, part of the sacrificial layer 102 is etched to pre-define the pattern of the suspended region 109. Then, a second etchant is injected according to the pre-defined pattern of the suspended region 109, and then part of the substrate 101 and the support layer 103 are etched to form a complete suspended region 109. At the same time, since a corrosion channel is formed after part of the sacrificial layer 102 is removed, the contact area between the second etchant and the substrate 101 and the support layer 103 is increased, the etching rate is improved, and the manufacturing time is shortened.

[0128] In this embodiment, by removing part of the sacrificial layer 102, the substrate 101, and the support layer 103 to form the suspended region 109, a relatively thick thermal isolation layer can be formed, and its thickness can be determined by the first sub-functional layer 1051 and the etching time, which is much larger than the thickness fabricated by the currently common methods. Therefore, through the above method, a relatively thick thermal isolation layer can be obtained, and at the same time, it is not affected by the relatively thick InGaAs layer on the growth quality of the thermally tunable semiconductor chip.

[0129] In this embodiment, the depth of the suspended region 109 determines the thermal isolation effect of the thermally tunable semiconductor chip. A relatively deep suspended region 109 can improve the thermal isolation effect of the thermally tunable semiconductor chip, improve the thermal tuning efficiency and the thermal tuning response speed of the thermally tunable semiconductor chip, and effectively solve the problem of low thermal tuning efficiency of the currently thermally tunable semiconductor chips.

[0130] In a specific application, first, corrosion holes are defined on the surface of the thermally tunable semiconductor chip. The corrosion holes are square with a size of 5μm * 10μm. Then, an inductively coupled plasma (ICP) etcher is used to etch the corrosion hole material, and the etching depth is between 3.00μm and 3.02μm. Next, a sulfuric acid-based solution (such as sulfuric acid: hydrogen peroxide: water = 5:1:1) is used for etching; then, a hydrochloric acid-based solution (such as HCl: H3PO4 = 3:1) is used for re-etching to remove part of the support layer and the substrate to form a suspended region. Finally, the remaining processes of the thermally tunable semiconductor chip can be carried out according to the normal steps, which will not be elaborated here.

[0131] It can be understood that in the embodiment where forming the through holes includes forming at least two through holes, there may be an unremoved sacrificial layer 102 between two adjacent through holes 107. Furthermore, in the step of etching the support layer, there may also be an unremoved support layer between two adjacent through holes 107; in other words, in the step of etching the sacrificial layer, the support layer, and the substrate, the parts of the support layer and the sacrificial layer located between any two of the at least two through holes are not completely removed.

[0132] In this embodiment, since the thermal tuning efficiency of the material is basically not affected by the material bandgap, in chip design, materials with a higher material bandgap can be used as the passive waveguide region for wavelength tuning, further reducing the absorption loss of the passive waveguide region material, reducing the chip threshold, and reducing the laser linewidth. At the same time, the waveguide layer and the substrate are thermally isolated by air, and when the chip thermal power is constant, both the thermal tuning efficiency and the tuning response speed are greatly improved.

[0133] It should be noted that the thermal tuning semiconductor chip embodiment provided by the present invention and the thermal tuning semiconductor chip preparation method embodiment belong to the same concept; among the technical features in the technical solutions recorded in each embodiment, they can be arbitrarily combined without conflict. However, it should be further noted that for the thermal tuning semiconductor chip provided by the embodiments of the present invention, the combination of its technical features can already solve the technical problems to be solved by the present invention; therefore, the thermal tuning semiconductor chip provided by the embodiments of the present invention can be independent of the thermal tuning semiconductor chip preparation method provided by the embodiments of the present invention, and any thermal tuning semiconductor chip prepared by a preparation method that can form the structure of the thermal tuning semiconductor chip provided by the embodiments of the present invention is within the protection scope of the present invention.

[0134] The above is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A thermally tuned semiconductor chip, characterized in that: The invention comprises: a substrate, and a sacrificial layer, a supporting layer and a functional layer sequentially stacked on the substrate; the functional layer is used to transfer heat to the thermal tuning electrode of the thermal tuning semiconductor chip; wherein, A suspension region is formed in the substrate and the sacrificial layer. The suspension region is a cavity structure extending from below the upper surface of the supporting layer, through the sacrificial layer, and terminating inside the substrate, so that the functional layer above the cavity structure and the remaining part of the substrate below the cavity structure are isolated by the suspension region; the suspension region includes a first portion located in the substrate, a second portion located in the sacrificial layer, and a third portion located in the supporting layer, and the depth of the first portion is greater than the sum of the depths of the second portion and the third portion.

2. The thermal tuning semiconductor chip according to claim 1, wherein: A lower surface of the sacrificial layer contacts an upper surface of the substrate.

3. The thermal tuning semiconductor chip according to claim 1, wherein: The thickness of the supporting layer is greater than the thickness of the sacrificial layer; the depth of the third portion of the suspension region located in the supporting layer is greater than the depth of the second portion of the suspension region located in the sacrificial layer.

4. The thermal tuning semiconductor chip according to claim 1, wherein: The material of the support layer is the same as that of the substrate.

5. The thermal tuning semiconductor chip according to claim 4, characterized in that The materials of the support layer and the substrate are both InP.

6. The thermal tuning semiconductor chip according to claim 1, wherein: The functional layer includes a first sub-functional layer, the lower surface of which contacts the upper surface of the support layer and is used as an etching stopper layer in a process of etching the support layer to form the suspension region.

7. The thermal tuning semiconductor chip according to claim 1, wherein: Also includes: at least two openings communicating with the suspension region, the suspension region being formed by an etching process performed through the at least two openings; A portion of the support layer and a portion of the sacrificial layer that have not been removed are located between any two of the at least two openings.

8. The thermal tuning semiconductor chip according to claim 1, wherein: The material of the sacrificial layer includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs.

9. A method for preparing a thermally tuned semiconductor chip, characterized in that: The method comprises: Providing a substrate, and sequentially forming a sacrificial layer, a supporting layer, and a functional layer on the substrate; the functional layer is used to transfer heat to the thermal tuning electrode of the thermal tuning semiconductor chip; forming a through hole, wherein the through hole penetrates the functional layer and the support layer and exposes a portion of the sacrificial layer; The sacrificial layer, the supporting layer and the substrate are etched to form a suspension area; the suspension area is a cavity structure extending from below the upper surface of the supporting layer, through the sacrificial layer, and terminating inside the substrate, so that the functional layer above the cavity structure and the remaining part of the substrate below the cavity structure are isolated by the suspension area; the suspension area includes a first part located in the substrate, a second part located in the sacrificial layer and a third part located in the supporting layer, and the depth of the first part is greater than the sum of the depths of the second part and the third part.

10. The method for preparing a thermally tuned semiconductor chip according to claim 9, wherein: Forming the sacrificial layer on the substrate specifically includes: directly forming the sacrificial layer on the substrate so that the lower surface of the sacrificial layer contacts the upper surface of the substrate.

11. The method for preparing a thermally tuned semiconductor chip according to claim 9, wherein: After forming the through hole, the method further includes: forming a mask layer, wherein the mask layer at least covers the sidewall of the through hole; An opening is formed at the bottom of the mask layer, wherein the opening exposes a portion of the sacrificial layer.

12. The method for preparing a thermally tuned semiconductor chip according to claim 9, wherein: Forming the suspension region specifically includes: Etching the sacrificial layer using a first etching process to expose a portion of the upper surface of the substrate and a portion of the lower surface of the support layer; The substrate and the support layer are etched using a second etching process to form the suspension region.

13. The method for preparing a thermally tuned semiconductor chip according to claim 9, wherein: The sacrificial layer has a first thickness, and the supporting layer has a second thickness, wherein the second thickness is greater than the first thickness; Forming the suspension region specifically includes: etching the support layer to a depth greater than the first thickness, so that the depth of the formed suspension region in the third portion located in the support layer is greater than the depth of the second portion located in the sacrificial layer.

14. The method for preparing a thermally tuned semiconductor chip according to claim 9, wherein: The material of the support layer is the same as that of the substrate.

15. The method for preparing a thermally tuned semiconductor chip according to claim 14, wherein: The materials of the support layer and the substrate are both InP.

16. The method for preparing a thermally tuned semiconductor chip according to claim 9, wherein: forming a support layer on the sacrificial layer, and forming the functional layer on the support layer, specifically comprising: after forming the support layer, forming a first sub-functional layer of the functional layer on the support layer, wherein the lower surface of the first sub-functional layer contacts the upper surface of the support layer; Forming the suspension region includes: using the first sub-functional layer as an etching stop layer when etching the support layer.

17. The method for preparing a thermally tuned semiconductor chip according to claim 9, wherein: The forming of the through holes includes forming at least two through holes; In the step of etching the sacrificial layer, the supporting layer and the substrate, portions of the supporting layer and the sacrificial layer located between any two of the at least two through holes are not completely removed.

18. The method for preparing a thermally tuned semiconductor chip according to claim 9, wherein: The material of the sacrificial layer includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs.

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