Background memory scan block selection

Abstract

The present disclosure relates to background memory scan block selection. Memory subsystems of the present disclosure select a memory block having a highest page fill ratio for a memory scan. In one embodiment, the memory subsystem identifies a plurality of block stripes on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The subsystem determines a fill ratio for each of the plurality of block stripes. The subsystem selects a block stripe having a highest fill ratio among the block stripes. The subsystem identifies a memory block of the LU from the selected block stripe. The subsystem performs a memory scan operation on the memory block of the memory device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory subsystems, and more specifically, to block selection for background memory scanning. BACKGROUND

[0002] A memory subsystem can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can use a memory subsystem to store data at and retrieve data from the memory devices. SUMMARY

[0003] In one aspect, the present disclosure designs a system comprising: a plurality of memory devices; and a processing device operatively coupled with the plurality of memory devices to perform operations comprising: identifying a plurality of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), wherein the LU is one of a plurality of LUs of a memory device; determining a fill ratio for each of the plurality of block stripes; selecting a block stripe with a highest fill ratio among the plurality of block stripes; identifying a memory block of the LU from the selected block stripe; and performing a memory scan operation on the memory block of the memory device.

[0004] In another aspect, the present disclosure designs a method comprising: identifying a memory address range storing fill threshold index (FTI) metadata for a plurality of block stripes located on a logical unit (LU), the LU identified by a logical unit number (LUN); determining a memory address corresponding to a highest FTI within the memory address range; determining a block stripe based on the memory address; identifying a memory block of the LU from the block stripe; and performing a memory scan operation on the memory block of the memory device.

[0005] In a further aspect, the present disclosure relates to a non-transitory machine-readable storage medium including instructions that, when accessed by a processing device, cause the processing device to perform one or more operations comprising: identifying a plurality of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), wherein the LU is one of a plurality of LUs of a memory device; determining a fill ratio for each of the plurality of block stripes; selecting a block stripe with a highest fill ratio among the plurality of block stripes; identifying a memory block of the LU from the selected block stripe; and performing a memory scan operation on the memory block of the memory device. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description, taken in conjunction with the accompanying drawings, in which like reference numerals refer to like elements throughout. The drawings, however, are not intended to limit the present disclosure to the specific embodiments presented but are intended to be illustrative only.

[0007] Figure 1A An example computing system including a memory subsystem is shown in accordance with some embodiments.

[0008] Figure 1A An example memory subsystem controller is shown in accordance with one embodiment.

[0009] Figure 2 is a block diagram showing a set of blocks (block stripe) allocated across IC logical units (LUNs) in accordance with an embodiment.

[0010] Figure 3 is a block diagram showing an example of a data structure configured to support zone-based mapping in accordance with an embodiment.

[0011] Figure 4 is a block diagram showing an example of a coupled NAND page threshold table in accordance with an embodiment.

[0012] Figure 5 is an example of block stripe fill threshold index (FTI) metadata in accordance with an embodiment.

[0013] Figure 6 is a flow diagram of an example method of selecting memory blocks for a memory scan in accordance with an embodiment.

[0014] Figure 7 is a flow diagram of an example method of selecting memory blocks for a memory scan in accordance with an embodiment.

[0015] Figure 8 is a block diagram of an example computer system in which embodiments of the present disclosure can operate. DETAILED DESCRIPTION

[0016] Aspects of the present disclosure relate to selecting blocks for a memory scan on a non-volatile memory device of a memory subsystem that supports partitioned namespaces. The memory subsystem can be a storage device, a memory module, or a combination of a storage device and a memory module. Example storage devices and memory modules are described below in connection with Figure 1A An example storage device and memory module are described. Generally, a host system can use a memory subsystem including one or more components such as a storage device that stores data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0017] Memory subsystems can include high-density non-volatile memory devices in which the retention of data is required when no power is supplied to the memory devices. One example of a non-volatile memory device is a NAND memory device. The following description is made in connection with NAND memory devices, but the description is applicable to other types of non-volatile memory devices as well. Figure 1A Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies (or logical units (LUs)) identified by a logical unit number (LUN). Each LU can be composed of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells (“cells”). The cells are electronic circuits that store information. Depending on the cell type, the cells can store one or more bits of binary information and have various logical states related to the number of bits being stored. The logical states can be represented by binary values such as “0” and “1” or combinations of such values.

[0018] A memory device can include a plurality of memory cells arranged in a two-dimensional grid. The memory cells are etched onto a silicon wafer in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address for a memory cell. In the following, a block refers to a unit of a memory device for storing data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell. One or more blocks can be grouped together to form a plane of a memory device in order to allow concurrent operations on each plane. A memory device can include circuitry to perform concurrent memory page accesses of two or more memory planes. For example, a memory device can include a respective access line driver circuit and power circuit for each plane of the memory device to facilitate concurrent access to pages of two or more memory planes that include different page types.

[0019] The cells (or simply “media”) of a memory device can be organized in a hierarchical manner from LUs (upper layer) to planes, to blocks, to pages (lower layer). A block set (also referred to as a block stripe) can be a set of blocks arranged across planes of different LUs such that the blocks are grouped together for the purpose of data storage. Writes to a block set allow more host data to be written and read concurrently in parallel across multiple LUs.

[0020] For some types of non-volatile memory devices (e.g., NAND devices), background scans are a component of proper NAND flash operations. Scans can refer to a check of programmed bits in a NAND device. Background scan operations serve to maintain stability and performance of a NAND device by monitoring bit error rates of programmed data in the NAND device throughout the life of the NAND device. Background scans can rely on scans of fully and partially programmed blocks on the NAND device. In a non-volatile memory device (or solid state device (SSD)), a block stripe can span all physical logical units (LUs) and be filled sequentially and in a predictable physical order using a logical to physical (L2P) mapping scheme to map logical host block addresses (LBAs) to physical NAND addresses. Due to this L2P mapping in traditional SSDs, there is a minimum number of partially filled blocks and block stripes in each LU. Due to these system design considerations, a write specific capacity SSD will have a representative sample of blocks available on each LU in the device to perform the required background scans.

[0021] In a zone namespace (ZNS) SSD, there is no L2P mapping in the traditional sense and each host zone can map to a block stripe within a flash translation layer (FTL) when the first host writes to the zone. Zones can be referred to as data groups and can be referred to as a range in LBA space. A “data group” can contain one or more blocks within a block set, or can contain one or more block sets that span multiple LUs. The LBAs of a zone (e.g., logical address space associated with a data group) can be sequentially ordered within LBA space and mapped to sequentially ordered physical addresses within a physical address space. Writes within a zone are performed sequentially from the beginning of the zone by a zone write pointer and data within a zone cannot be arbitrarily overwritten. The only way to overwrite a zone that has already been written to is to reset the zone write pointer, effectively deleting all data in the zone and starting writes from the beginning of the zone again. A ZNS SSD can report a zone active limit (ZAL) that indicates to the host the maximum amount of time a zone can remain open. The zone active limit defines the amount of time a host can leave a partially filled zone. However, even though the zone can appear to the host to have completed reporting, the corresponding NAND blocks can not be fully programmed, adding complexity to NAND background scan operations. Furthermore, zone sizes in ZNS can be much smaller than block stripes in a typical SSD, resulting in a larger number of block stripes in a ZNS SSD.

[0022] The memory sub-system of the present disclosure addresses the above and other deficiencies by selecting a candidate memory block having a highest page fill ratio for a memory scan. In one embodiment, the memory sub-system identifies a plurality of block stripes on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs of a memory device. The sub-system determines a fill ratio for each of the plurality of block stripes. The sub-system selects a block stripe having a highest fill ratio among the block stripes. The sub-system identifies a memory block of the LU from the selected block stripe. The sub-system performs a memory scan operation on the memory block of the memory device.

[0023] Aspects of the above-referenced methods and systems are described in detail below with reference to the following example embodiments, by way of illustration and not by limitation.

[0024] Figure 1A An example computing system 100 including a memory sub-system 110 according to some embodiments of the present disclosure is shown. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination thereof.

[0025] The memory sub-system 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device including a memory and a processing device.

[0027] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to a plurality of memory sub-systems 110 of different types. Figure 1AAn example of a host system 120 coupled to a memory sub-system 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0028] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, memory controllers (e.g., NVDIMM controllers), and storage protocol controllers (e.g., PCIe controllers, SATA controllers). The host system 120 uses the memory sub-system 110, e.g., to write data to and read data from the memory sub-system 110.

[0029] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for communicating control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1A The memory sub-system 110 is shown as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory devices 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0031] Some examples of non-volatile memory devices (e.g., memory devices 130) include negative-and (NAND)-type flash memory and in-place write memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grided data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform in-place write operations, in which a non-volatile memory cell can be programmed without prior erasure of the non-volatile memory cell. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), can store one bit per cell. Other types of memory cells, such as a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), and a penta-level cell (PLC), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination of these. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device that are used to store data. In the case of some types of memory, such as NAND, pages can be grouped to form blocks.

[0033] Although non-volatile memory components are described, such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND), the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or negative-or (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0034] The memory sub-system controller 115 (or, for simplicity, the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory sub-system controller 115 can include a processing device including one or more processors (e.g., the processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0036] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the local memory 119 is shown as being internal to the memory sub-system controller 115, in some embodiments, the local memory 119 can be external to the memory sub-system controller 115. Figure 1A The example memory sub-system 110 in FIG. 1 has been shown to include the memory sub-system controller 115, but in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0037] In general, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with memory devices 130. Memory sub-system controller 115 can further include host interface circuitry to communicate with host system 120 over a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions to access memory devices 130, as well as convert responses associated with memory devices 130 into information for host system 120.

[0038] Memory sub-system 110 can also include additional circuitry or components not shown. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row and column decoders) that can receive addresses from memory sub-system controller 115 and decode the addresses to access memory devices 130.

[0039] Memory sub-system 110 includes a block selection component 113 that can select a block candidate with the highest page fill percentage / ratio for a scan of memory in a partitioned namespace SSD. In some embodiments, memory sub-system controller 115 includes at least a portion of block selection component 113. In some embodiments, block selection component 113 is part of host system 110, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of block selection component 113 and is configured to perform the functionality described herein. Additional details regarding the operation of block selection component 113 are described below.

[0040] Reference is made to Figure 1BIn one embodiment, the memory sub-system controller 115 can include a memory scan manager 116 and a direct memory access (DMA) engine 129. The DMA engine 129 can be a hardware-based component of the memory sub-system configured to execute DMA commands and transfer direct memory from a source memory region to a destination memory region. The memory scan manager 116 can include a read level calibration (RLC) scan module 121, a data retention scan module 122, and a background scan module 125. The memory scan manager 116 can send a request with a LUN to the block selection component 113 to request a block in a LU identified by the LUN. The memory scan manager 116 can then perform various memory scans on the block identified with the LUN, including a read level calibration scan, a data retention scan, or a background scan (for error bits).

[0041] A read level calibration scan can be a memory scan that determines read level thresholds (voltage level thresholds for read operations) of a memory device. The read level thresholds can be used for successive read level calibrations that adjust one or more read level thresholds used to read pages from the memory device. A read level calibration operation can be performed to keep each threshold centered so that the memory component can achieve the best possible overall bit error rate (BER). The calibration is referred to as successive because the algorithm is sampled continuously at discrete intervals.

[0042] A data retention scan refers to scanning a plurality of blocks / LUNs at power-up to monitor data retention after a potentially long / extended period of time that the non-volatile memory device was powered off. To avoid using potentially corrupted data, the controller 115 can perform a data retention scan on the non-volatile memory device at power-up to assess the condition of the data.

[0043] A background scan can monitor the bit error rate for programmed data in a NAND device throughout the life of the NAND device. The background scan can rely on scanning fully and partially programmed blocks on the NAND device.

[0044] The local memory 119 can include a mapping data structure 126, coupled NAND page threshold tables 127, and filled threshold index (FTI) metadata 128. The mapping data structure 126 can include, as Figure 3Various mappings of the block set are further described. The coupled NAND page threshold table 127 can include a mapping of FTI to coupled NAND page threshold. The FTI metadata 128 can include metadata storing the FTI value for each block stripe grouped by LUN in the memory sub-system 110. The FTI value is an index value (natural number) indicating a fill ratio of the block stripe. The fill ratio is associated with a ratio or percentage of pages in the block stripe having valid data. The coupled NAND page threshold for the FTI value is the minimum number of pages that are fully coupled in the block stripe to associate the block stripe with the corresponding FTI value.

[0045] A page is fully coupled if the page can be read without causing read disturb due to neighboring pages not being programmed. That is, if a page is programmed without a subsequent page being programmed, it is unreliable to determine a bit error rate. Read disturb refers to reading from a memory cell that can cause some neighboring memory cells in the same memory block to change over time. In one embodiment, only fully coupled pages are used to record a count of fill ratio due to read disturb errors. To reduce complexity, the coupled NAND page threshold table 127 is used to map from a write cursor of the block set to a fully coupled page.

[0046] The block selection component 113 can receive a request identifying a block candidate within a logical unit (LU) identified by a LUN value, the request containing the LUN value. The block selection component 113 can query the FTI metadata 128 for a block stripe of the LUN, where the block stripe is associated with the highest FTI value. The component 113 then maps the block stripe to a block within the LUN based on the mapping data structure 126. The block selection component 113 can then return an identifier of the block, in another embodiment, the block selection component 113 can also determine a last programmed page of the block that can be tracked by the local memory 119, and return an identifier of the last programmed page of the block.

[0047] Figure 2 is a block diagram illustrating a block set (block stripe) allocated across logical units according to an embodiment. Referring to Figure 2Referring to one or more memory devices 130, 140, the physical address space of LUs identified by LUNs (e.g., LUN 0 and LUN 1) within the memory devices 130, 140 can be organized in a hierarchical manner by plane, block, and page. Thus, for example, each LU of LUN 0 and LUN 1 can include plane A and plane B, and each of plane A and plane B can include block A and block B. A block set (or block stripe) can be defined as a group of blocks of a plane arrangement spanning multiple dies of a memory device. As shown, block set 144 is arranged to include block A of plane A of LUN 0, block A of plane B of a LU identified by LUN 1, and so on, e.g., also including block A of plane C of a LU identified by LUN 1, and if present and online, continuing to another LUN.

[0048] Figure 3 is a block diagram showing an instance of a data structure configured to support zone-based mapping according to an embodiment. Controller 115 can store some of the mapping data structures 126 in volatile local memory 119 and / or non-volatile memory devices 130-140 (not shown) of Figure 1A . Controller 115 can also use the data structures of Figure 3 to support media layout (e.g., mapping of zones to be located within a physical address space). In Figure 3 , zone mapping data structure 201 is configured to provide media layout information for zones in a namespace such as LBA space for ZNS operations. Zone mapping data structure 201 can have a plurality of entries. Each zone mapping entry in zone mapping data structure 201 identifies information about a zone, e.g., a start LBA 211 of the zone, a block set identifier 213 of the zone, a zone cursor value 215 of the zone, a status 217 of the zone, and so on. Zone mapping data structure 201 contains information about zones and can be used to identify the physical location of a zone, e.g., which block stripe / LUN in a physical address space the zone is located.

[0049] Host system 120 starts writing data in a zone at the LBA of zone start LBA 211. Host system 120 can sequentially write data in the zone in LBA space. After a certain amount of data has been written into the zone, the current start LBA for writing subsequent data is identified by zone cursor value 215. Each write command for the zone moves zone cursor value 215 to the new start LBA for the next write command for the zone. Status 217 can have a value indicating that the zone is empty, full, implicitly open, explicitly open, closed, and so on to track the progress of writing to the zone.

[0050] Referring to Figure 3The block set mapping data structure 123 stores data for aspects of the dynamic media layout of the control zone. The block set mapping data structure 123, which can be a table in one embodiment, can have a plurality of entries. Each block set entry in the block set data structure 123 identifies a number / count 271 of LUs (e.g., LUN 0, LUN 1, etc.) in which data for a zone is stored. For each LU used for the zone, the block set entry of the block set mapping data structure 123 has a LUN identifier 273, a block identifier 275, etc. The memory sub-system can use the block set mapping data structure 123 to identify blocks corresponding to a block stripe within a given LU.

[0051] The LUN identifier 273 identifies a particular LU (e.g., LUN 0, LUN 1, etc.) in the media of the memory sub-system 110 in which data for a zone can be stored. The block identifier 275 identifies a particular memory block (e.g., NAND flash memory or other media) within the LU identified using the LUN identifier 273 in which data for the zone can be stored. In one embodiment, the block set mapping data structure 123 is a plane index mapping table indexed by block set ID (e.g., block stripe ID). The block set mapping data structure 123 can map a block set ID to a physical block (e.g., a physical block address or identifier) within each die / LUN of a memory device.

[0052] For example, the memory sub-system 110 receives a plurality of write command streams. In embodiments, each respective stream of the plurality of streams is used to write data in a logical address space sequentially in one embodiment; and in another embodiment, streams of the plurality of streams are configured to write data in a logical address space pseudo-sequentially or randomly in one embodiment. Each write stream contains a set of commands that write a set of data together as a group, fine-tune, rewrite. In the group, data can be written sequentially, randomly, or pseudo-sequentially in logical space. Preferably, data in the group is written to an erase block set, where memory cells in the erase block set store data for the stream, but not data from other streams. The erase block set can be erased to remove data for the stream without erasing data for other streams.

[0053] For example, each of the write streams is permitted to write sequentially at LBAs in a zone in a namespace allocated in the media of the memory devices 130, 140 of the memory sub-system 110, but is prohibited from writing data out of order in the LBA (or logical address) space. Because a zone has a zone activity limit (ZAL) that indicates to a host a maximum amount of time a zone can remain open, a zone can close before data is written to the zone, e.g., resulting in a partially filled zone. That is, even if a zone is indicated as complete / closed, some memory blocks are still empty / inactive.

[0054] The block for background scan purposes can be the NAND block with the highest page fill ratio. Another consideration for memory scan is that for bit error rate detection via scan, the fill pages of a block should be considered fully coupled so as to be considered readable. Depending on the type of NAND, a page is fully coupled if the memory controller can read the page without causing read disturb due to subsequent pages not being programmed. Thus, a predetermined coupled NAND page threshold table can be used to determine the fill ratio of a block stripe.

[0055] Figure 4 is a block diagram showing an example of a coupled NAND page threshold table according to an embodiment. Table 400 can be a coupled NAND page threshold table for a type of NAND device. Table 400 can be used by controller 115 to generate a fill threshold index (FTI) value that indicates the fill ratio of a block stripe. The FTI value indicates the fill ratio of a block stripe. The coupled NAND page threshold column indicates the minimum threshold for a fill page to be fully coupled for the corresponding FTI value.

[0056] Figure 5 is an example of block stripe fill threshold index (FTI) metadata according to an embodiment. In this example, metadata 128 indicates that LUN 0 contains block stripe 0, 1, 2, 3, etc.; LUN 1 contains block stripe i, i+1, i+2, i+3, etc.; and LUN n contains block stripe j, j+1, j+2, j+3, etc. In one embodiment, metadata 128 can contain name / value pairs. In another embodiment, metadata 128 contains a contiguous array of FTI values, where the FTI values have a predetermined mapping to block stripes based on the location of the FTI value in the metadata. In one embodiment, FTI metadata 128 is an array indexed by block set ID (e.g., block stripe ID). Note that the contiguous array of FTI values can facilitate block selection as further described below.

[0057] In one embodiment, the FTI value for a block stripe in metadata 128 can be initialized to 0. Here, the FTI value can be an index value (e.g., 0, 1, 2, 3, 4, etc.) that maps to a coupled NAND page threshold. In one embodiment, when a page is written (programmed) to a block stripe associated with a zone, the memory controller updates the entry in metadata 128. Specifically, when a write request is made to program a block stripe (in this case, block stripe n), the current FTI value for block stripe n can be retrieved from metadata 128. The current FTI value can be used to look up the next FTI value, and the coupled NAND page threshold for the next FTI value (e.g., next coupled NAND page threshold). The next coupled NAND page threshold can then be compared to the page number of the current page being programmed, and if the page number matches or exceeds the next coupled NAND page threshold, the FTI value for the block stripe is updated to the next FTI value, e.g., 0 -> 1.

[0058] For example, referring to Figure 1A , 4 -5, a given block stripe n has an FTI value of 0. Upon writing to a zone via a cursor value, the zone can map to a page value and a block stripe value, e.g., page 187 of block stripe n. Controller 115 can retrieve the FTI value of 0 from metadata 128 corresponding to block stripe n. Following the FTI value of 0, controller 115 looks up the next FTI value of 1 from table 400. Controller 115 retrieves the next coupled NAND page threshold from table 400, e.g., 187. Controller 115 compares the current page being programmed to the next coupled NAND page threshold, e.g., the current page of 187 is greater than or equal to the next coupled NAND page threshold of 187. In response to determining that the page number of the current page being programmed is greater than or equal to the next coupled NAND page threshold, controller 115 updates the FTI value in metadata 128 for block stripe n to the next FTI value, e.g., 1.

[0059] In one embodiment, to identify a block stripe in a LU identified by a LUN that has the highest page fill, block selection module 113 can iterate through metadata 128 for a particular LUN to identify a block stripe with the highest FTI value as the block stripe with the highest page fill. After identifying the block stripe, block selection module 113 can query block set mapping data structure 123 to determine a block candidate based on the block stripe and the LUN.

[0060] In one embodiment, the metadata 128 is grouped by the LUN identified LU such that each LUN corresponds to a contiguous segment of metadata 128. For example, the scan manager 116 can request the block selection component 113 to return the identifiers for the block candidates to perform a memory scan for LUN 0. In one embodiment, the block selection component 113 can identify a block stripe (or block set) from the block set mapping data structure 123 for the block set associated with LUN 0. The block selection component 113 can then traverse or scan the metadata 128 for the block stripe associated with LUN 0 to retrieve the FTI values for the block stripe. The block selection component 113 compares the FTI values to determine the block stripe with the highest FTI value. The BSM converts the block stripe to blocks and obtains the identifiers for the blocks based on the block set mapping data structure 123. In one embodiment, the block selection component 113 can retrieve the last programmed page for the blocks, which can be tracked by the local memory 119. The block selection component 113 returns the block identifiers and / or last programmed pages to the scan manager 116.

[0061] In another example, the block selection component 113 can send a request to perform a highest FTI value search in the metadata 128 to a DMA engine, such as the DMA engine 129. In one embodiment, the metadata 128 includes an array of FTI values indexed by block stripe # and grouped by LUN. With the metadata 128 in an array, the metadata 128 can be loaded onto memory and the DMA engine 129 can expedite the search of the block stripe (without blocking the controller for processing other tasks) to iterate from the memory entry corresponding to the LU (e.g., LUN 0) of the metadata 128 to the identified memory address with the highest FTI value by using a min / max / compare function. Figure 1B

[0062] In one embodiment, the block selection component 113 identifies the block stripe using the identified memory address. For example, the block selection component 113 can calculate an offset value for the identified memory address from a starting address within the memory address range and use the offset value to calculate the block stripe #. For example, if the starting address 0x00 corresponds to block stripe (BS) 0, and the BS increments by 0x04, then the memory address 0x04 (offset = 0x04) corresponds to BS 1, the memory address 0x08 (offset = 0x08) corresponds to BS 2, and so on. When the identified memory address maps to a block stripe #, the DMA engine can notify the block selection component 113 of the block stripe #. The block selection component 113 then converts the block stripe # to a block # based on the block set mapping data structure 123 and obtains the identifier for the block as described above.

[0063] Figure 6 ​is an example method 660 for selecting a memory block for a memory scan in a zoned namespace SSD according to some embodiments of the present disclosure. The method 660 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 660 is performed by the block selection component 113 of FIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, it is to be understood that the illustrated embodiments are meant as examples only and that the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. Figure 1B

[0064] At operation 661, the processing logic identifies those block stripes that are located on a logical unit (LU) identified by a logical unit number (LUN), where the LU is one of a plurality of LUs within the memory device. The block stripes can be retrieved from the block set mapping data structure 123, as the block set mapping data structure 123 contains mappings for all block stripes in the LU. At operation 663, the processing logic determines a fill ratio for each of the plurality of block stripes. At operation 665, the processing logic selects a block stripe having a highest fill ratio among the plurality of block stripes. At operation 667, the processing logic identifies a memory block of the LU from the selected block stripe. The memory block candidate can be identified by retrieving a first block entry associated with the LUN for the block stripe from the block set mapping data structure 123. At operation 669, the processing logic performs a memory scan operation on the memory block of the memory device.

[0065] In one embodiment, determining the fill ratio of the block stripe includes determining fill threshold index (FTI) metadata of the block stripe. In one embodiment, the FTI metadata of the block stripe corresponds to the plurality of block stripes of the same LU being incrementally indexed.

[0066] In one embodiment, determining the fill threshold index (FTI) metadata of the block stripe includes determining the fill threshold index (FTI) metadata of the block stripe via a direct memory access (DMA) engine. In one embodiment, the processing logic further updates the FTI metadata of the block stripe in response to a page write to the block stripe by: determining a number of pages for the page write; determining an FTI value based on the number of pages using a coupled NAND page threshold table; and updating the FTI metadata according to the FTI value.

[0067] ​In one embodiment, the memory device is a non-volatile memory device having a zoned namespace. In one embodiment, the memory scan includes at least one of a read level calibration memory scan, a data retention memory scan, or a background memory scan for detecting bit errors.

[0068] Figure 7 is an example method 700 of selecting a memory block for a memory scan in a zoned namespace SSD, according to some embodiments of the present disclosure. The method 700 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 700 is performed by a block selection component 113 of Figure 1B The method 700 is performed by the block selection component 113. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, it is to be understood that the processes shown can be performed in other orders, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0069] At operation 701, the processing logic identifies a memory address range storing fill threshold index (FTI) metadata for a plurality of block stripes located on a logical unit (LU), the LU identified by a logical unit number (LUN). At operation 703, the processing logic determines a memory address corresponding to a highest FTI within the memory address range. At operation 705, the processing logic determines a block stripe based on the memory address. At operation 707, the processing logic identifies a memory block of the LU from the block stripe. At operation 709, the processing logic performs a memory scan operation on the memory block of the memory device.

[0070] In one embodiment, determining the block stripe based on the memory address includes determining an offset value from a starting location in the memory address range based on the memory address, and determining the block stripe based on the offset value. In one embodiment, the FTI metadata of the block stripe corresponds to a plurality of block stripes of the same LU are incrementally indexed.

[0071] In one embodiment, determining, within the range of memory addresses, the memory address corresponding to the highest FTI comprises determining, within the range of memory addresses, the memory address corresponding to the highest FTI via a direct memory access (DMA) engine. In one embodiment, the processing logic is further to update the FTI metadata for the block stripe in response to a page write to the block stripe by: determining a number of pages for the page write; determining an FTI value based on the number of pages using a coupled NAND page threshold table; and updating the FTI metadata according to the FTI value.

[0072] In one embodiment, the memory device is a non-volatile memory device having a zoned namespace. In one embodiment, the memory scan comprises at least one of: a read level calibration memory scan, a data retention memory scan, or a background memory scan to detect bit errors.

[0073] Figure 8 An example machine is shown in FIG. 6, in which an instance of the machine can execute instructions for causing the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 600 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used in performing operations of a controller (e.g., executing an operating system to perform operations corresponding to the block selection component 113 of FIG. 1). Figure 1A Figure 1A Figure 1A Figure 1B In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environments, as a peer machine in peer-to-peer (or distributed) network environments, or as a server or a client machine in a cloud computing infrastructure or environment.

[0074] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0075] ​​​The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or RDRAM), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0076] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 communicating via network 620.

[0077] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more instruction sets 626 or software embodying any one or more of the methods or functions described herein are stored. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1A The memory subsystem 110.

[0078] In one embodiment, instruction 626 includes implementing a component corresponding to a block selection component (e.g., Figure 1B The block selection component 113) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0079] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self- consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0080] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0081] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0082] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0083] The disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, etc.

[0084] In the foregoing specification, embodiments of the disclosure have been described with reference to specific examples embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system for memory operations, comprising: a plurality of memory devices; and a processing device, operatively coupled with the plurality of memory devices, to perform operations comprising: identifying a plurality of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), wherein the LU is one of a plurality of LUs of a memory device; determining a fill ratio of fully coupled pages for each of the plurality of block stripes; selecting, among the plurality of block stripes, a block stripe having a highest fill ratio of fully coupled pages; identifying, from the selected block stripe, a memory block of the LU; and performing a memory scan operation on the memory block of the memory device.

2. The system of claim 1, wherein determining the fill ratio of fully coupled pages for a block stripe comprises determining an FTI value for the block stripe from fill threshold index (FTI) metadata, the FTI metadata comprising FTI values for the plurality of block stripes located on the LU.

3. The system of claim 2, wherein the FTI metadata is incrementally indexed for each of the plurality of block stripes located on the LU.

4. The system of claim 3, wherein determining the FTI value for the block stripe comprises determining the FTI value for the block stripe via a direct memory access (DMA) engine.

5. The system of claim 3, further comprising updating the FTI value for the block stripe in the FTI metadata by: determining a number of pages for a page write; determining a respective FTI value based on the number of pages using a coupled NAND page threshold table; and updating the FTI value for the block stripe in the FTI metadata according to the respective FTI value determined using the coupled NAND page threshold table.

6. The system of claim 1, wherein the memory device is a non-volatile memory device having a zoned namespace.

7. The system of claim 1, wherein the memory scan comprises at least one of: a read level calibration memory scan, a data retention memory scan, or a background memory scan, wherein the background memory scan detects bit errors in the memory block.

8. A method for memory operations, comprising: identifying a memory address range storing fill threshold index (FTI) metadata, the FTI metadata comprising FTI values indicating a fill ratio of fully coupled pages for each of a plurality of block stripes located on a logical unit (LU) of a memory device, the LU identified by a logical unit number (LUN); determining, within the memory address range, a memory address corresponding to a highest FTI value; determining a block stripe based on the memory address; identifying, from the block stripe, a memory block of the LU; and performing a memory scan operation on the memory block of the memory device.

9. The method of claim 8, wherein determining a block stripe based on the memory address comprises: determining an offset value from a starting location in the memory address range based on the memory address; and determining the block stripe based on the offset value. ​ ​ ​ 10. The method of claim 9, wherein the FTI metadata is incrementally indexed for each of the plurality of block stripes of the same LU.

11. The method of claim 10, wherein determining a memory address corresponding to the highest FTI value within the memory address range comprises determining the memory address corresponding to the highest FTI value within the memory address range via a direct memory access (DMA) engine.

12. The method of claim 10, further comprising updating the FTI metadata for the block stripe by: determining a number of pages for a page write; determining a respective FTI value based on the number of pages using a coupled NAND page threshold table; and updating the FTI value for the block stripe in the FTI metadata according to the respective FTI value determined using the coupled NAND page threshold table.

13. The method of claim 8, wherein the memory device is a non-volatile memory device having a zoned namespace.

14. The method of claim 8, wherein the memory scan comprises at least one of a read level calibration memory scan, a data retention memory scan, or a background memory scan, wherein the background memory scan detects bit errors in the memory block.

15. A non-transitory machine-readable storage medium including instructions that, when accessed by a processing device, cause the processing device to perform one or more operations comprising: identifying a plurality of block stripes located on a logical unit (LU) identified by a logical unit number (LUN), wherein the LU is one of a plurality of LUs of a memory device; determining a fill ratio of fully coupled pages for each of the plurality of block stripes; selecting, among the plurality of block stripes, a block stripe having a highest fill ratio of fully coupled pages; identifying, from the selected block stripe, a memory block of the LU; and performing a memory scan operation on the memory block of the memory device.

16. The non-transitory machine-readable storage medium of claim 15, wherein determining the fill ratio of fully coupled pages for a block stripe comprises determining an FTI value for the block stripe from fill threshold index (FTI) metadata comprising FTI values for the plurality of block stripes located on the LU.

17. The non-transitory machine-readable storage medium of claim 16, wherein the FTI metadata is incrementally indexed for each of the plurality of block stripes located on the LU.

18. The non-transitory machine-readable storage medium of claim 17, wherein determining the FTI value for the block stripe comprises determining the FTI value for the block stripe via a direct memory access (DMA) engine.

19. The non-transitory machine-readable storage medium of claim 17, further including instructions that, when accessed by a processing device, cause the processing device to perform one or more operations comprising: updating the FTI value for the block stripe in the FTI metadata by: determining a number of pages for a page write; determining a respective FTI value based on the number of pages using a coupled NAND page threshold table; and updating the FTI value for the block stripe in the FTI metadata according to the respective FTI value determined using the coupled NAND page threshold table. determining a number of pages for a page write; determining a respective FTI value based on the number of pages using a coupled NAND page threshold table; and updating the FTI value for the block stripe in the FTI metadata according to the respective FTI value determined using the coupled NAND page threshold table.

20. The non-transitory machine-readable storage medium of claim 15, wherein the memory device is a non-volatile memory device having a zoned namespace.

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