A verification method for the relationship between GaAs LED chip voltage and TCL film layer

Abstract

The present invention relates to a method for verifying the relationship between the voltage of a gallium arsenide (GaAs) LED chip and a TCL film layer, belonging to the field of semiconductor processing technology, and comprising the following steps: (1) chip preparation: preparing an LED chip on which an epitaxial layer, a TCL film layer, and an electrode are sequentially grown on a gallium arsenide substrate; (2) test point production: using a photoresist or an electrode photoresist to produce a mask pattern, the mask pattern being located on the entire chip surface, using an etching liquid to etch away the TCL film layer in other areas, and performing debonding to produce test points; (3) ohmic contact testing: using a test machine to measure an I-V curve between two adjacent test points, and judging whether the ITO and epitaxial layer are in good contact by whether the curve is a straight line, and obtaining corresponding relationship information after verification, so as to obtain the quality of a tube core produced simultaneously or in the same batch as the verification tube core, and facilitate adjustment of a process or method, thereby avoiding large losses and improving product yield.

Description

Technical Field

[0001] The present invention relates to a process method for verifying the relationship between the voltage of a gallium arsenide LED chip and a TCL film layer, and belongs to the technical field of semiconductor processing. Background Art

[0002] A light-emitting diode (LED) is an electroluminescent semiconductor device consisting of a PN junction formed by a P electrode and an N electrode. It is typically made from compounds containing gallium (Ga), arsenic (As), phosphorus (P), and nitrogen (N). LEDs, known as the fourth-generation lighting source, are widely used due to their numerous advantages, including compact size, environmental friendliness, long life, energy efficiency, and high stability. Currently, my country is gradually becoming a global LED industry base, and overseas emerging markets are creating greater opportunities for domestic LED companies. The rapid growth of these markets will continue to benefit domestic LED manufacturers. Gallium arsenide (GaAs), a black solid, is stable in air below 600°C and is resistant to corrosion by non-oxidizing acids. GaAs is a very important semiconductor material, belonging to the III-V group of compound semiconductors. With a band gap of 1.4 electron volts, semiconductor devices made with GaAs offer numerous advantages, including high frequency, high and low-temperature resistance, low noise, and strong radiation resistance. Gallium arsenide is one of the semiconductor materials that has many advantages.

[0003] The GaAs-based LED die structure typically consists of a substrate, epitaxial layer, transparent conductive layer (TCL), and electrode layer, resulting in a complex manufacturing process. When using GaAs substrates to fabricate LED die electrodes, the complexity of the entire process, the tedious steps involved, and the uncontrollable nature of human operations inevitably lead to abnormal wafer parameters, surface irregularities, and regional contamination. Wafer parameter anomalies are particularly common, and most of these anomalies are caused by conductivity abnormalities in the TCL layer. Therefore, timely determination of the TCL film's quality after fabrication is crucial for minimizing die losses. During the GaAs-based LED die structure manufacturing process, TCL corrosion is avoided, and the TCL film is integral to the entire light-emitting area, making it difficult to test the proper contact between the film and the epitaxial layer, or the quality of the TCL film itself.

[0004] Chinese patent document CN103713251 A (201410002151.0) proposes a method for verifying the relationship between high voltage and ITO film on white LED chips. The specific steps are as follows: 1) Select an abnormally high Vf1 chip during testing and soak it in ammonium fluoride etchant for 20-60 seconds to remove the silicon dioxide from the passivation layer. 2) The chip, with the silicon dioxide removed, undergoes yellow light P-SiO2 photolithography. After yellow light photolithography, it is soaked in ITO etchant for 100-150 seconds to remove the remaining ITO film. After photoresist removal, ITO vapor deposition is performed again. 3) After vapor deposition, yellow light ITO photolithography is performed, followed by another immersion in ITO etchant for 100-200 seconds to expose the N electrode and the aisle. 4) After photoresist removal, ITO fusion is performed, and finally, spot testing is completed. This invention can efficiently verify the relationship between the high VF1 and the quality of the evaporated ITO film layer, so that the impact of the ITO film quality on the electrical VF1 can be determined intuitively, and an early warning can be given to the ITO evaporation process of the production line, which is beneficial to improving product quality. However, this invention method must complete the entire tube core structure before testing, so the cycle will inevitably be longer, and it takes a long time from ITO to the finished product. Moreover, in this invention method, the ITO film layer that is subsequently verified is remade for the second time. If there is a large difference in the quality of the ITO film layer made for the first time and the film layer made for the second time, then this method is likely to get the opposite result, which will mislead our judgment. In other words, there is a problem that the ITO film layer made for the second time cannot represent the quality of the film layer made for the first time.

[0005] In view of this, it is necessary to study a process method that can timely determine the quality and conductive properties of the ITO film layer. Summary of the Invention

[0006] In response to the problem of abnormal photoelectric parameters caused by abnormal TCL film layer in the existing GaAs-based LED tube core production, the present invention has invented a process method that can determine the quality of the TCL film layer by testing the contact between the TCL film layer and the epitaxial layer.

[0007] The technical solutions of the present invention are as follows:

[0008] A method for verifying the relationship between the voltage of a GaAs LED chip and a TCL film layer comprises the following steps:

[0009] (1) Wafer preparation: Prepare the LED wafer with epitaxial layer, TCL film layer and electrode grown on the GaAs substrate in sequence;

[0010] (2) Test point production: Use photoresist or electrode photoresist to make a mask pattern. The mask pattern is located on the entire wafer surface. Use etching liquid to etch away the TCL film layer in other areas and remove the glue to make the test point.

[0011] (3) Ohmic contact test: Use a test machine to measure the IV curve between two adjacent test points.

[0012] Preferably, according to the present invention, the epitaxial layer described in step (1) is a film layer grown on a gallium arsenide substrate, and the epitaxial layers from the gallium arsenide substrate upward are: an N-type gallium arsenide ohmic contact layer, an N-type gallium arsenide confinement layer, a quantum well active layer, a P-type confinement layer, a P-type gallium arsenide ohmic contact layer, and a P-type gallium phosphide window layer.

[0013] According to the preferred embodiment of the present invention, the TCL film layer described in step (1) is further preferably an ITO film layer, and the metal electrode is made of one of the commonly used metals Cr, Ti, Al, Pt, Au, Ni, Ge, and Ag.

[0014] According to the preferred embodiment of the present invention, in step (2), the mask pattern and the electrode are staggered and distributed, and the manufacturing process does not need to consider the protection of the electrode. The same photoresist can be used, and only a glue with opposite properties needs to be used. In this way, a circular TCL pattern is obtained, and the photoresist of other parts is developed and removed. Alternatively, a separate photoresist can be used to obtain the desired pattern. Photolithography is a conventional process.

[0015] According to the preferred embodiment of the present invention, in step (2), the diameter of the test point is preferably between 50-100 μm, that is, the distance at the widest point of the test point is within this range. If the test point is circular, the diameter is 50-100 μm. If the test point is square, the side length is 50-100 μm. If the test point is rectangular, both the length and width are within this range. The same applies to ellipse, and the same applies to irregular shapes.

[0016] Further preferably, in step (2), the diameter of the test point is 80 μm, and the test point is a regular-shaped figure, specifically an axisymmetric or centrosymmetric figure.

[0017] In step (2), the pattern openings of the mask pattern are located in the entire light-emitting area, and two adjacent test points can be selected for testing.

[0018] According to a preferred embodiment of the present invention, in step (2), the etching liquid is an acidic etching liquid, more preferably hydrochloric acid, wherein the mass fraction of hydrochloric acid is 36-38% and the density is 1.10 g / ml-1.25 g / ml; the photoresist is a conventional photoresist. Etching the TCL pattern can be performed in a conventional manner.

[0019] In step (3), the test machine used is a common optoelectronic parameter test machine, model IPT6000.

[0020] Preferably, according to the present invention, in step (3), after the test, the quality of the ohmic contact is judged according to the slope of the IV curve. If it is a straight line, it is determined that the contact between the ITO and the epitaxial layer is intact.

[0021] This application is a testing method for the contact between the entire tube core structure and the TCL film layer of the finished tube core (or the tube core that has completed the TCL film layer). After verification, the corresponding relationship information can be obtained to obtain the quality of the tube core produced at the same time or in the same batch as the verified tube core, which is convenient for adjusting the process or method to avoid large losses and improve product yield.

[0022] The beneficial effects of the present invention are:

[0023] 1. The present invention makes test points by opening holes in the TCL film layer, and directly performs penetration tests on adjacent test points and tests the conductive performance between the TCL film layer and the epitaxial layer. This can characterize the TCL film layer itself and verify whether ohmic contact is formed between the TCL film layer and the epitaxial layer, thereby achieving the purpose of verifying the quality of the TCL film layer.

[0024] 2. In the present invention, the selection of the test point size is extremely important. If the test point size is too small, the needle mark of the test needle used will be large, and the test will be inaccurate. If the test point size is too large, it will affect the characterization of the conductive performance between the TCL film layer and the epitaxial layer. In addition, the selection of the distance between two adjacent test points has little effect on the IV curve test results, and only affects the size of the IV curve slope, without affecting the linear relationship.

[0025] 3. The testing method of the present invention has simple operation steps and easy-to-understand principles. The IV curve of the test can completely correspond to the final die wafer photoelectric parameter VF1 (forward voltage). It is suitable for characterizing the contact performance between all LED wafer film layers and can avoid huge losses caused by parameter abnormalities in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 , which is a longitudinal schematic diagram of the tube core structure completed in step (1);

[0027] Figure 2 , which is a plan view of the tube core structure completed in step (1);

[0028] Figure 3 , is a planar diagram of the test point after step (2) is completed;

[0029] Figure 4, is the normal curve after the test in step (3), indicating that the conductivity of the TCL film is normal; the horizontal axis is marked with a voltage from -1v to 1v, and the vertical axis is the current value, in mA;

[0030] Figure 5 , is the abnormal curve after the test in step (3), which characterizes the abnormal conductivity of the TCL film layer; the horizontal axis is marked with the voltage from -1v to 1v, and the vertical axis is the current value, in mA;

[0031] Among them: 001 is the gallium arsenide substrate; 002 is the epitaxial layer; 003 is the TCL film layer; 004 is the metal electrode; 005 is the TCL pattern after etching (test point); 006 is the P-type gallium phosphide window layer on the upper surface of the epitaxial layer exposed after etching the TCL film layer. DETAILED DESCRIPTION

[0032] The present invention will be further described below with reference to embodiments and accompanying drawings, but is not limited thereto.

[0033] Example 1:

[0034] A method for verifying the relationship between the voltage of a GaAs LED chip and a TCL film layer comprises the following steps:

[0035] (1) Wafer preparation: An LED wafer with an epitaxial layer, a TCL film layer, and electrodes grown on a GaAs substrate is prepared for use. The TCL film layer is an ITO film layer, and the metal electrode is made of one of the commonly used metals Cr, Ti, Al, Pt, Au, Ni, Ge, and Ag. The epitaxial layer is a film layer grown on the GaAs substrate. From the GaAs substrate upward, the epitaxial layers are: N-type GaAs ohmic contact layer, N-type GaAs confinement layer, quantum well active layer, P-type confinement layer, P-type GaAs ohmic contact layer, and P-type GaP window layer.

[0036] (2) Test point production: Use photoresist to make a mask pattern, which is located on the entire chip surface. Use etching liquid to etch away the TCL film layer in other areas, and then remove the glue to make test points; the test points are circular with a diameter of 80μm.

[0037] The mask pattern and the electrodes can be staggered, and electrode protection is not a concern during the manufacturing process. The same photomask can be used, simply using a resist with opposite properties. This will produce a circular TCL pattern, while the remaining resist is removed by development. Alternatively, separate photomasks can be used to achieve the desired pattern. Lithography is a conventional process.

[0038] The etching solution is an acidic etching solution, more preferably hydrochloric acid, wherein the mass fraction of hydrochloric acid is 36-38% and the density is 1.10g / ml-1.25g / ml; the photoresist is a conventional photoresist, and etching the TCL pattern can be a conventional operation.

[0039] (3) Ohmic contact test: Use a test machine to measure the IV curve between two adjacent test points. The test machine used is a common optoelectronic parameter test machine, model IPT6000. After the test, the quality of the ohmic contact is judged based on the slope of the IV curve. If it is a straight line, it is determined that the contact between the ITO and the epitaxial layer is intact.

[0040] Example 2:

[0041] A method for verifying the relationship between the voltage of a gallium arsenide LED chip and a TCL film layer, wherein the steps are as described in Example 1, except that, in step (2), a mask pattern is produced using a photomask of an electrode.

[0042] Example 3:

[0043] A method for verifying the relationship between the voltage of a GaAs LED chip and a TCL film layer, wherein the steps are as described in Example 1, except that in step (2), the diameter of the test point is 50 μm.

[0044] Example 4:

[0045] A method for verifying the relationship between the voltage of a GaAs LED chip and a TCL film layer, wherein the steps are as described in Example 1, except that in step (2), the diameter of the test point is 100 μm.

[0046] Example 5:

[0047] A method for verifying the relationship between the voltage of a GaAs LED chip and a TCL film layer, wherein the steps are as described in Example 1, except that in step (2), the test point is a square with a side length of 80 μm.

[0048] Example 6:

[0049] A method for verifying the relationship between the voltage of a GaAs LED chip and a TCL film layer, wherein the steps are as described in Example 1, except that in step (2), the test point is a rectangle with a long side length of 80 μm.

Claims

1. A method for verifying the relationship between GaAs LED chip voltage and TCL film layer, characterized in that: The steps are as follows: (1) Wafer preparation: Prepare the LED wafer with epitaxial layer, TCL film layer and electrode grown on the GaAs substrate in sequence; The TCL film layer is an ITO film layer, and the electrode is made of one of the metals Cr, Ti, Al, Pt, Au, Ni, Ge, and Ag; (2) Test point production: Use photoresist or electrode photoresist to produce a mask pattern. The mask pattern is located on the entire wafer surface. Use etching liquid to etch away the TCL film layer in other areas and remove the glue to produce test points. The mask pattern and the electrode are staggered. The diameter of the test point line is between 50-100μm. (3) Ohmic contact test: Use a test machine to measure the IV curve between two adjacent test points; After the test, the quality of the ohmic contact is judged based on the slope of the IV curve. If it is a straight line, it is determined that the contact between the ITO and the epitaxial layer is intact.

2. The method for verifying the relationship between the GaAs LED chip voltage and the TCL film layer according to claim 1, characterized in that: The epitaxial layer described in step (1) is a film layer grown on a gallium arsenide substrate, and the epitaxial layers from the gallium arsenide substrate upward are: an N-type gallium arsenide ohmic contact layer, an N-type gallium arsenide confinement layer, a quantum well active layer, a P-type confinement layer, a P-type gallium arsenide ohmic contact layer, and a P-type gallium phosphide window layer.

3. The method for verifying the relationship between GaAs LED chip voltage and TCL film layer according to claim 1, characterized in that: In step (2), the diameter of the test point is 80 μm, and the test point is a regular shape.

4. The method for verifying the relationship between GaAs LED chip voltage and TCL film layer according to claim 1, characterized in that: In step (2), the etching liquid is an acidic etching liquid, which is hydrochloric acid, and the mass fraction of the hydrochloric acid is 36-38%, and the density is 1.10g / ml-1.25g / ml.

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