Cmos imaging sensor and related manufacturing method

Abstract

A CMOS imaging sensor and related manufacturing method are described. A CMOS image sensor pixel has integrated within its in-pixel circuitry a saddle gate source follower transistor. The saddle gate source follower transistor structure can include a channel region having a three-dimensional geometry defined by a trench on axial sides thereof. A gate oxide layer is formed over the top and axial sides of the channel region, and a saddle gate structure is formed on the gate oxide layer. Thus, the saddle gate structure includes a seat portion extending over the top of the channel region, and first and second guard portions extending over the first and second axial sides of the channel region, such that the first and second guard portions are buried below the upper surface of the semiconductor substrate (e.g., in the trench formed in the side isolation region).

Description

[0001] Cross-references

[0002] This application claims the benefit of priority to U.S. non-provisional patent application No. 17 / 527,065, filed on November 15, 2021, entitled “SADDLE-GATE SOURCE FOLLOWER FORIMAGING PIXELS,” which is a non-provisional application of and claims the benefit of priority to U.S. provisional patent application No. 63 / 127,494, filed on December 18, 2020, entitled “3-DIMENSIONAL FIN-SHAPED TRANSISTOR DESIGNS AND APPLICATIONS IN SEMICONDUCTOR IMAGE SENSORS,” and the above two applications are hereby incorporated by reference in their entirety. Technical Field

[0003] This document relates to complementary metal oxide semiconductor (CMOS) image sensors. More particularly, embodiments relate to a saddle gate source follower transistor block for integration with in-pixel circuitry of a CMOS image sensor (CIS) pixel. Background Art

[0004] Many modern electronic applications include integrated digital cameras and / or other imaging systems based on complementary metal oxide semiconductor (CMOS) image sensor (CIS) technology. A CIS can typically include an array of pixels, where each pixel includes a single photosensor (e.g., a photodiode), or an array of multiple photosensors. Each pixel can also include supporting hardware, such as a source follower transistor for converting the optical response of the photosensor into a corresponding electrical signal for use by other components. The performance of a pixel is related to its size. For example, increasing the size of the photodiode area in a pixel can increase the full well capacitance (FWC) of the photodiode, which often supports higher dynamic range, higher contrast, and / or other image performance improvements. Similarly, increasing the active area of ​​the source follower transistor can improve the noise performance of the pixel, such as by increasing its signal-to-noise ratio (SNR).

[0005] For any given pixel size, the optical sensor(s) and source-follower transistors must share a common footprint. Consequently, an increase in either dimension forces a decrease in the other, so pixel design typically represents a trade-off between image performance (related to the size and, consequently, the optical sensor's FWC) and noise performance (related to the active area of ​​the source-follower transistors). As pixel size continues to decrease, maintaining acceptable noise performance (i.e., a high SNR) while optimizing the FWC becomes increasingly difficult. SUMMARY

[0006] Embodiments provide circuits, devices, and methods for implementing a saddle gate source follower transistor integrated with a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) pixel. For example, a CIS can include an array of a large number of imaging pixels (e.g., millions of imaging pixels). Each imaging pixel can include one or more photosensors for converting incident illumination to accumulated photocharge, and in-pixel circuitry for reading out and converting the accumulated photocharge to a pixel output signal. Each in-pixel circuit includes a source follower block in a readout chain, and embodiments of the source follower block described herein are implemented with a saddle gate source follower transistor structure. The saddle gate source follower transistor structure can include a channel region having a three-dimensional geometry defined by a trench on axial sides thereof. A gate oxide layer is formed over a top and axial sides of the channel region, and a saddle gate structure is formed on the gate oxide layer. Thus, the saddle gate structure includes a seat extending over the top of the channel region, and first and second shields extending over the first and second axial sides of the channel region, such that the first and second shields are buried below an upper surface of the semiconductor substrate.

[0007] According to a set of embodiments, a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) is provided. The CIS includes an imaging pixel having: a semiconductor substrate; a photosensor block including at least one photosensor configured to accumulate photocharge in response to exposure to illumination and transfer the accumulated photocharge to a floating diffusion region for readout; and in-pixel circuitry coupled with the floating diffusion region to convert the accumulated photocharge to a pixel output signal. The in-pixel circuitry includes: a saddle gate source follower transistor block having: a channel region having a three-dimensional geometry including: an upper portion having an axial length dimension and a planar width dimension, a first axial side portion defined by a first side trench to have an axial length dimension and a first shield depth dimension, and a second axial side portion defined by a second side trench to have an axial length dimension and a second shield depth dimension, the channel region being implanted with a channel doping; a gate oxide layer formed over at least the upper portion, the first axial side portion, and the second axial side portion of the channel region; and a saddle gate structure formed on the gate oxide layer to have a seat extending over the upper portion of the channel region, a first shield extending over the first axial side portion of the channel region, and a second shield extending over the second axial side portion of the channel region, such that the first shield and the second shield are buried below an upper surface of the semiconductor substrate.

[0008] Some such embodiments also include: filling a first side isolation region formed into a first isolation trench etched to a first isolation trench depth in the semiconductor substrate deeper than the first trench depth along at least the axial length; and filling a second side isolation region formed into a second isolation trench etched to a second isolation trench depth in the semiconductor substrate deeper than the second trench depth along at least the axial length, wherein the first side trench is etched into the first isolation trench electrical isolation material and the second side trench is etched into the second isolation trench electrical isolation material. Some such embodiments also include a source region and a drain region implanted into the semiconductor substrate, the source region located at a first axial end of the channel region and the drain region located at a second axial end of the channel region opposite the first axial end and separated therefrom by a distance corresponding to the axial length.

[0009] According to another set of embodiments, a method for fabricating a horse-shoe gate source follower transistor block is provided. The method includes: forming a channel region of the horse-shoe gate source follower transistor block by: etching a first side trench to a first trench depth along an axial length of a semiconductor substrate; etching a second side trench to a second trench depth along the axial length of the semiconductor substrate, the second side trench substantially parallel to the first side trench and separated therefrom by a horizontal distance, such that a three-dimensional geometry of the channel region includes an upper portion, a first axial side portion, and a second axial side portion defined according to the axial length, the horizontal distance, the first trench depth, and the second trench depth; and implanting a channel dopant into the semiconductor substrate according to the three-dimensional geometry of the channel region; forming a gate oxide layer over the semiconductor substrate at least over the upper portion, the first axial side portion, and the second axial side portion of the channel region; and forming a horse-shoe gate structure over the gate oxide layer to have: a seat portion extending over the upper portion of the channel region to have a planar width dimension corresponding to the horizontal distance, a first shield portion extending over the first axial side portion of the channel region to have a first shield depth dimension corresponding to the first trench depth, and a second shield portion extending over the second axial side portion of the channel region to have a second shield depth dimension corresponding to the second trench depth.

[0010] Some such embodiments further comprise forming side isolation regions by: etching a first isolation trench along at least the axial length to a first isolation trench depth deeper than the first trench depth; etching a second isolation trench along at least the axial length to a second isolation trench depth deeper than the second trench depth; and filling the first isolation trench and the second isolation trench with an electrically isolating material; wherein the first side trench is etched into the electrically isolating material of the first isolation trench and the second side trench is etched into the electrically isolating material of the second isolation trench. Some such embodiments further comprise implanting a source region and a drain region into the semiconductor substrate, the source region being located at a first axial end of the channel region and the drain region being located at a second axial end of the channel region opposite the first axial end and separated from the first axial end by a distance corresponding to the axial length.

[0011] The following figures, description, and claims provide a more detailed description of the above and other aspects of the transistor with a hybrid structure, its implementation, and features of the disclosed technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated herein and constitute a part thereof, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the invention.

[0013] Figure 1 Shown is a simplified block diagram of a portion of an illustrative digital imaging system as context for the various embodiments described herein.

[0014] Figure 2A and 2B A side cross-sectional view and a perspective view are respectively shown of a conventional source follower block implemented as a planar source follower transistor, which is typical of a conventional CIS pixel design.

[0015] Figures 3A-3D Shown is a simplified view of an illustrative novel saddle-gate source follower transistor in accordance with various embodiments described herein.

[0016] Figure 4 Shown is a simplified physical layout of an illustrative CIS pixel having integrated saddle-gate source-follower transistors with a 2×2 photosensor arrangement in accordance with various embodiments.

[0017] Figure 5 Shown is a simplified physical layout of another illustrative CIS pixel having integrated saddle-gate source-follower transistors with a 2×4 photosensor arrangement in accordance with various embodiments.

[0018] Figure 6 A simplified circuit schematic diagram of a CIS pixel is shown according to various embodiments described herein.

[0019] Figure 7 An illustrative integrated circuit portion fabrication process for fabricating a saddle gate source follower transistor on a semiconductor substrate of an integrated circuit is shown in accordance with various embodiments.

[0020] Figures 8A-8D Illustrative diagrams of the saddle gate source follower transistor in fabrication at various stages of the fabrication process along Figure 7

[0021] In the drawings, like parts and / or features can have the same reference label. Also, various parts of similar type can be distinguished by following the reference label by a second label, e.g., 1stand 2ndlabels, that denotes the different instance of the parts. If only the first reference label is used in the specification, the description is applicable to any one of the similar parts having the same first reference label irrespective of the second reference label. DETAILED DESCRIPTION

[0022] In the following description, numerous specific details are provided, such as examples of specific types of components, techniques, etc., in order to provide a thorough understanding of the present application. However, it will be recognized by one skilled in the art that the present application can be practiced without one or more of the specific details. In other instances, well-known features and techniques have not been described in order to not obscure the related description.

[0023] Many modern electronic applications include integrated digital cameras and / or other imaging systems based on complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) technology. A CIS can generally include an array of pixels, each pixel including a single photosensor (e.g., photodiode), or a group of multiple photosensors. Each imaging pixel can include a photosensitive element that generates photocharge in response to light, and in-pixel circuitry for processing the generated photocharge to produce an electrical pixel output signal and for controlling operation of each imaging pixel. The in-pixel circuitry of a CIS imaging pixel typically includes a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) for performing sensing and control functions.

[0024] Figure 1 A simplified block diagram is shown as part of an illustrative digital imaging system 100 in the context of various embodiments described herein. The digital imaging system 100 can be constructed around complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) technology. Such a CIS system can generally include one or more arrays of pixels 105, such as a large number of pixels 105 arranged in rows and columns. Each pixel 105 can include a photosensor block 110, which can include a single photodiode 115 (e.g., or any suitable photosensor such as a photogate, phototransistor, etc.), or a group of multiple photodiodes 115 (e.g., a group of four photodiodes). ​

[0025] Pixel 105 also includes additional components (in-pixel circuitry) to facilitate optical sensing using photosensor block 110. As shown, embodiments can include a gain block 120, a reset block 130, a source follower block 140, and a select block 150. Each can be implemented using at least one corresponding transistor. Gain block 120 can control the gain of pixel 105, such as by implementing double conversion gain (DCG). Reset block 130 can selectively reset pixel 105 components. Source follower block 140 (implemented herein using a saddle gate source follower device) can support conversion of output from photosensor block 110 into an electrical signal indicative of optical information detected by photosensor block 110. Select block 150 can support selection of pixel 105 signals from among an array of pixels 105, for example as part of a row select operation. Pixel 105 can be coupled with a readout bus 160, such as a column select bus.

[0026] As technology advances, there has been a drive in many application contexts to reduce the size of such pixels 105. Indeed, many digital imaging applications are seeking to increase the number and density of pixels 105 on their image sensor chips (i.e., a reduction in the drive 105 pixel size) while also requiring designs to continue to meet or exceed a number of performance parameters, such as those related to image contrast, dynamic range, frame capture rate, signal-to-noise ratio (SNR), power consumption, and the like. However, it has proven that certain performance parameters of pixels 105 tend to be adversely affected by reducing the size of components within pixel 105. For example, reducing the size of photodiode 115 in photosensor block 110 can reduce its full well capacity (FWC), which can tend to result in lower dynamic range, lower contrast, and / or other image performance degradation. Similarly, reducing the active area of source follower block 140 can degrade the noise performance of pixel 105, such as by reducing its signal-to-noise ratio (SNR). For example, reducing the active area of source follower block 140 tends to increase its low frequency noise (sometimes referred to as 1 / f noise) and / or burst noise (also referred to as random telegraph signal (RTS) noise, impulse noise, bistable noise, and the like). Some conventional pixel 105 designs seek to maximize component sizes within the limited footprint of pixel 105, but the footprint of each pixel 105 is shared by all of its components; increasing the size of one component (e.g., photosensor block 110) tends to require reducing the size of another (e.g., source follower block 140). Thus, conventional pixel 105 designs are often forced to compromise between image performance (related to the size of the photosensor and corresponding FWC) and noise performance (related to the active area of the source follower transistor).

[0027] As pixel 105 size continues to decrease, even achieving an acceptable compromise between image performance and noise performance becomes increasingly difficult. To add context, Figure 2A and 2B A side cross-sectional view and a perspective view are respectively shown of a conventional source follower block 140 implemented as a planar source follower transistor 200, which is typical of a conventional CIS pixel design. As shown, the planar source follower transistor 200 includes a drain region 210, a source region 215, and a gate region 220, all of which are implemented on a substrate 205. For example, the substrate 205 is a p-doped silicon wafer, each of the drain region 210 and the source region 215 is an n-doped region of the substrate 205, and the gate region 220 is a polysilicon structure deposited (e.g., by deposition) on the substrate 205. Applying a gate voltage to the gate region 220 can cause a current channel to form and current to flow between the drain region 210 and the source region 215 in the direction of arrow 225. The length (L) of the current channel is Figure 2A The active area width (W) of the planar source follower transistor 200 is shown as dimension 230. Figure 2B is shown as size 235. Figure 2B As shown, active areas may be defined (eg, isolated from adjacent devices) using isolation regions 240 , such as shallow trench isolation (STI) regions.

[0028] Achieving a specific performance level for a CIS pixel may involve implementing the source follower block 140 to produce at least a threshold level of transconductance (g_m) within a threshold acceptable noise level. The amount of transconductance may functionally correspond to performance characteristics such as frame rate, power consumption, and certain types of noise. In general, the transconductance of a generalized source follower transistor in the saturation region may be calculated as:

[0029]

[0030] Where W is the width of the source follower transistor (e.g., Figure 2B 235), C_ox is the oxide capacitance, and v_sat is the saturation voltage. It can be seen that the transconductance of a source follower transistor tends to be proportional to its width, so that a reduction in width tends to produce a corresponding reduction in transconductance related performance.

[0031] Additionally, the voltage noise at the gate of the source follower transistor (S_vg) can be calculated as:

[0032]

[0033] where M is an empirical parameter and β is a frequency dependent parameter. The voltage signal at the source follower transistor gate is often proportional to the gate capacitance, described by C ox * W * L, where L is the current channel length (e.g., the dimension 230 in conventional designs Figure 2A From the gate voltage noise and the gate voltage signal, it can be shown that the SNR of the source follower transistor is functionally related to C ox3* W2* L2. Thus, it can be seen that the SNR of the source follower transistor is often proportional to its width and length, such that a reduction in the size of the source follower transistor often results in a corresponding reduction in noise performance. Notably, in conventional designs, this noise performance is often further reduced at the edges of the device, such as in the isolation region 240. For example, current flowing in the current channel can be trapped in the STI region and can generate additional noise.

[0034] Many modern digital imaging applications have pushed pixel size down to the scale of approximately 1.12 microns. Even at such small scales, some conventional designs based on planar source follower transistors 200 have achieved sufficient transconductance (gm) at acceptable noise levels to provide high CIS performance. However, as pixel size continues to decrease, it becomes extremely difficult, impractical, or even impossible to maintain desirable levels of transconductance (gm) and SNR.

[0035] As noted above, in conventional planar source follower transistors 200, the gate region 220 is disposed on top of the substrate 205. Application of a gate voltage to the gate region 220 can cause a current channel to form just below the surface of the substrate 205 between the drain region 210 and the source region 215 (just below the gate region 220). Thus, the length and width of the formed current channel are related to the length and width of the gate region 220; the physical layout width of the current channel is approximately the effective active width of the current channel. For example, reducing the length or width of the gate region 220 will often reduce the length or width of the current channel, thereby affecting the performance of the source follower.

[0036] Embodiments described herein provide a novel source follower block 140 implemented using a saddle gate source follower transistor. Generally, embodiments of the saddle gate source follower transistor described herein include separate source and drain regions implanted into a semiconductor substrate, and a channel region extending in an axial direction between the source and drain regions. A saddle gate structure is integrated with the substrate in such a way that the saddle gate structure includes a seat deposited over the channel region, and a shield buried in the substrate (e.g., into a previously formed isolation region) to wrap around axial sides of the channel region. A gate oxide layer is sandwiched between the saddle gate structure and the channel region, such that the gate oxide layer also wraps around a top of the channel region and the axial sides of the channel region. Application of a gate voltage to a terminal patterned on the saddle gate structure creates an electric field that causes a current channel to form in the channel region. The effective channel width of the saddle gate source follower transistor (resulting from the three-dimensional saddle gate structure) is significantly larger than its two-dimensional physical layout width. Thus, the saddle gate source follower transistor can provide better performance (e.g., an increase in transconductance-related and / or noise-related performance) compared to a conventional planar source follower transistor having the same physical layout dimensions.

[0037] Figures 3A-3D A simplified view of an illustrative novel saddle gate source follower transistor 300 is shown, in accordance with various embodiments described herein. The saddle gate source follower transistor 300 can be an implementation of the source follower block 140 of Figure 1 FIG. 1. Figure 3A A simplified perspective view (labeled 300a) is shown, shown as cut through a gate region of the saddle gate source follower transistor 300. For greater clarity, Figure 3A A reference coordinate system is shown, in which the “z” direction extends along a length of the device (referred to herein as an “axial” direction), the “x” direction extends along a width of the device, and the “y” direction represents a vertical dimension (i.e., a dimension laid out perpendicular to the zx plane). Figure 3B A cross-sectional view (labeled 300b) is shown, corresponding to a widthwise cut through the gate of the saddle gate source follower transistor 300 in the x-y plane, in accordance with the illustrated axis prescription shown in Figure 3A FIG. 2. Figure 3C A cross-sectional view (labeled 300c) is shown, corresponding to a lengthwise cut along the saddle gate source follower transistor 300 in the z-y plane, in accordance with the illustrated axis prescription shown in Figure 3A FIG. 3. Figure 3D A top plan view (labeled 300d) of the saddle gate source follower transistor 300 is shown, in accordance with the illustrated axis prescription shown in Figure 3A FIG. 4. Figures 3A to 3D are described together.

[0038] The saddle gate source follower transistor 300 is shown as being supported by (i.e., implemented on, integrated with, etc.) a silicon substrate 205 such as a portion of a silicon wafer. A source region 350 and a drain region 355 are implanted into the substrate 205 and separated by a channel region 330 that effectively defines an active region of the device. A saddle gate structure 310 is formed to wrap around the top of the channel region 330 and laterally down the axial sides, as described more fully below. The source region 350 and the drain region 355 are typically implemented as doped wells implanted into the substrate 205 at either end of the gate, as can be seen in Figure 3A , 3C and 3D. In some implementations, the substrate 205 is a p-type substrate and the source region 350 and the drain region 355 are n-doped regions. In other implementations, the substrate 205 is an n-type substrate and the source region 350 and the drain region 355 are p-doped regions.

[0039] As in other metal oxide semiconductor field effect transistor (MOSFET) devices, applying a voltage potential at a gate terminal 312 of the saddle gate structure 310 creates an electric field that changes the conductivity of the channel region 330 between the source region 350 and the drain region 355. For example, applying a voltage of at least a threshold level to the gate terminal 312 can cause a depletion region to form in the channel region 330 of the substrate 205, which allows current to flow between the source region 350 and the drain region 355. In contrast, because the saddle gate structure 310 wraps around the top of the channel region 330 and laterally down the axial sides as described herein, applying a voltage potential at the gate terminal 312 of the saddle gate structure 310 creates an electric field from the top and axial sides of the channel region 330 that can produce effects similar to those of a planar source follower transistor having a significantly wider active region (e.g., with respect to noise performance, transconductance, and / or other characteristics).

[0040] As shown in Figure 3A and 3B , the saddle gate source follower transistor 300 includes a gate oxide layer 320 formed around the top and axial sides of the channel region 330 (i.e., the sides that extend along the length of the channel region 330), and the saddle gate structure 310 deposited around the top and axial sides of the gate oxide layer 320. The saddle gate structure 310 can be made of metal, conductive polysilicon material, and / or any other suitable material. In particular, the saddle gate structure 310 includes a seat 313 that extends over the top of the channel region 330, and a shield 315 that wraps around the axial sides of the channel region by being buried in the substrate 205 (e.g., into the side isolation regions described below). Figure 3BThe seat 313 of the saddle gate structure 310 is shown to form a planar (i.e., horizontal) width dimension 314 that extends across the channel region 330 in the “x” dimension (and also extends longitudinally over the channel region 330 in the “z” dimension). The shield 315 of the saddle gate structure 310 extends downward (i.e., generally in the “y” dimension) into the substrate 205 by a shield depth dimension 316. The shield depth dimension 316 can correspond to a maximum depth that the buried shield 315 extends into the substrate 205 (e.g., into a trench previously formed in the substrate 205 into an isolation region). In some embodiments, the shield depth dimension 316 can be greater than or equal to the planar width dimension 314. While the two shield depth dimensions 316 are shown as being equal, other embodiments can be implemented with different shield depth dimensions 316 (i.e., with each shield 315 having a different respective depth).

[0041] The shield depth dimension 316 increases the effective active area width (W) of the saddle gate source follower transistor 300. For example, the seat 313 defines a planar width dimension 314 (W) of 300 nanometers (nm), and each shield 315 defines a shield width dimension of 150 nm. In this example, the two shields 315 together provide an additional 300 nm of effective width, doubling the effective width of the device active area to 2W. With reference to the equation provided above, it can be seen that doubling the effective width of the device active area can increase the SNR of the device by a factor of four. Thus, the saddle gate source follower transistor 300 having these dimensions can exhibit an SNR that is approximately four times that of a conventional planar source follower transistor having the same planar active area width (W).

[0042] The gate oxide layer 320 serves as a dielectric layer between the saddle gate structure 310 and the channel region 330. In particular, at least a portion of the gate oxide layer 320 is sandwiched between the saddle gate structure 310 and the channel region 330 to form a dielectric around three sides of the channel region 330. In some embodiments, the gate oxide layer 320 can be formed by a thermal oxidation process. Figures 3A-3D As can be seen in the middle, the channel region 330 has a three-dimensional geometry that includes: an upper portion having an axial length dimension 318 (see Figure 3C , the dimension 318 extending in the “z” direction) and a planar width dimension 314; a first axial side portion (adjacent to the first shield 315a of the saddle gate structure 310) defined by a first side trench to have an axial length dimension; and a second axial side portion (adjacent to the second shield 315b of the saddle gate structure 310) defined by a second side trench to have an axial length dimension and a second shield depth dimension 316. Thus, at least as Figure 3A , and 3BAs shown, a gate oxide layer 320 is formed on at least an upper portion of the channel region 330, on upper portions of the first and second axial sides, and a saddle gate structure 310 is formed on the gate oxide layer 320 such that its seat portion 313 extends over the upper portion of the channel region (i.e., generally covering the region of the upper portion of the channel region and following its general contour), its first shield portion 315a extends over the first axial side of the channel region 330, and its second shield portion 315b extends over the second axial side of the channel region, such that the first and second shield portions 315 are buried under the lower surface of the semiconductor substrate 205.

[0043] Some embodiments include one or more isolation regions 325 around the outside and / or bottom of the shield portions 315 of the saddle gate structure 310. The isolation regions 325 can be shallow trench isolation (STI). The isolation regions 325 can be made of any suitable electrically isolating material, such as undoped polysilicon or silicon dioxide. As described below, the isolation regions 325 can be formed prior to forming the gate oxide layer 320 and the saddle gate structure 310. For example, isolation trenches are etched into the substrate 205 and filled with an isolation material. The trenches are then etched into the isolation material, which can ultimately at least partially define the geometry of the shield portions 315 of the saddle gate structure 310. The trenches etched into the isolation material also expose the substrate 205 to form the axial sidewalls of the channel region 330. The gate oxide layer 320 can be grown around the channel region 330, including on the axial sidewalls of the channel region 330 exposed by the etched trenches. As shown, embodiments of the isolation regions 325 can be formed in deeper trenches than those used to form the shield portions 15 of the saddle gate structure 310.

[0044] Some embodiments include additional structures. For example, Figure 3B A gate contact 312 is shown patterned onto the seat portion 313 of the saddle gate structure 310 and a spacer 340 (e.g., a nitride spacer) is deposited around the saddle gate structure 310 on the surface of the substrate 205. While not explicitly shown, embodiments can include other structures, such as additional doped regions, etc. For example, some embodiments include additional p-type implants along the interface between the isolation regions 325 and the substrate 205, such as to reduce dark current and time noise.

[0045] Figure 3A and 3BThe views are highly simplified views and are intended to illustrate only certain features. For example, while various regions and structures are shown as having square corners and / or defined edges, actual implementations of these regions and structures typically have organic shapes. Thus, the boundaries or edges of these regions and structures are not actually completely definable boundaries, but are often defined in a more statistical manner (e.g., by a nominal value, a process corner, etc.), as will be appreciated by those skilled in the art. Thus, the various illustrated regions and structures are generally intended to illustrate the general relative placement of structures and regions, the general isolation between structures and regions, etc.; but are not intended to define particular shapes, sizes, boundaries, and / or other features.

[0046] The novel saddle gate source follower transistor 300 can be used in various different types of integrated circuit applications. Some applications use such a saddle gate source follower transistor 300 to implement a source follower block 140 of in-pixel circuitry of an imaging pixel 105 (e.g., as shown in Figure 1 Such an image sensor device can be formed on a substrate to include an array of imaging pixels 105 supported by the substrate and operable to detect incident light to capture an image carried by the incident light. Each imaging pixel 105 can be structured to include a photosensitive device or element that is responsive to a portion of the incident light received by the photosensitive device to generate a pixel signal indicative of the received portion of the incident light. Each imaging pixel 105 includes in-pixel circuitry coupled to receive and process the pixel signal from the photosensitive device to generate a pixel output signal. Thus, the pixel output signals from the imaging pixels collectively carry image information of the image carried by the incident light.

[0047] The in-pixel circuitry in each imaging pixel 105 can include a source follower block 140 based on the above-described saddle gate source follower transistor 300 design supported by the substrate. In such implementations, the saddle gate source follower transistor 300 is coupled to a floating diffusion node positioned adjacent to a phototransducer block 110 that converts incident light to photocharge, and the photocharge is transferred to the floating diffusion node for readout by the source follower block 140 to convert the photocharge to a voltage pixel signal representative of the photocharge. Implementations of the source follower block 140 using the saddle gate source follower transistor 300 can reduce SNR and increase transconductance (gm) in the readout signal chain of each imaging pixel 105.

[0048] Figure 4 A simplified physical layout of an illustrative CIS pixel 400 having a saddle gate source follower transistor 300 integrated with a 2x2 phototransducer 115 arrangement is shown in accordance with various embodiments. The illustrative layout can be Figure 1An embodiment of a layout of a pixel 400 is shown in FIG. 4. The central region of the layout includes a photosensor block 110 having four photosensors 115 (e.g., photodiodes). The upper portion of the layout includes a gain block 120 (e.g., for a DCG) and a reset block 130 with respective contacts. The lower portion of the layout includes a select block 150 and a novel source follower block 140, implemented as a saddle gate source follower transistor 300 having a saddle gate structure 310. As can be seen, the width of each of the component blocks is established by the design of the layout. The imaging pixel 105 also includes a first oxide diffusion region for supporting the reset block 130, and a second oxide diffusion region for supporting the select block 150 and the saddle gate source follower transistor block, such that the select block 150 and the saddle gate source follower transistor block share a doped source region 350 implanted into the second oxide diffusion region.

[0049] As noted above, the active region of the active layer of the source follower block 140 has a definable width (W), indicated as the physical layout width 410 of the saddle gate source follower transistor 300, due at least to the doping parameters and the edge isolation structure. As noted above, the physical layout width 410 is based on the planar width dimension 314 of the saddle gate source follower transistor 300. The width 410 is determined, at least in part, by pixel design parameters and manufacturing process constraints. For example, as noted above, the pixel footprint design balances the allocated space between the photosensor block 110 and the supporting components including the source follower block 140. The allocated space can generally define a maximum (or nominal) width of the transistor components. As shown, embodiments of the saddle gate source follower transistor 300 can occupy substantially the same layout area as a conventional planar source follower transistor, including occupying the same physical layout width 410. Such embodiments allow the saddle gate source follower transistor 300 to fit within conventional pitch parameters (e.g., within typical physical design parameters for a standard 2x2 CIS pixel layout), including leaving the required area for the photosensor block 110, and allowing at least the drain contact 355 (corresponding generally to the drain region 355) and the gate contact 312 to be placed in locations that can comply with conventional manufacturing processes for a CIS pixel 400. Some embodiments also include a source contact. In other embodiments, as shown, the source region 350 of the saddle gate structure 310 is shared by the select block 150, and no other signal is coupled thereto; and can not require a source contact. Other embodiments can use other suitable physical layout dimensions in accordance with other CIS optical sensor block designs, other manufacturing process constraints, etc.

[0050] The saddle gate structure 310 can provide a significantly greater effective active width of the device even in embodiments where the physical layout width 410 and the physical layout channel length of the current channel of the CIS photoreceptor block are similar to those of a conventional planar source follower transistor used in conventional CIS photoreceptor blocks. For example, the effective width of the saddle gate source follower transistor 300 can correspond to the physical layout width of the saddle gate structure 310 plus the guard plate depth dimension 316 of each guard 315. In the illustrated embodiment, four photoreceptors 115 are coupled with the floating diffusion node 415 to which accumulated photocharge is transferred from the photoreceptors 115 for readout by in-pixel circuitry. The dashed rectangle shows a floating diffusion interconnect 420 through which the floating diffusion node 415 can be coupled with the gate contact 312 of the saddle gate source follower transistor 300 (and the source terminal of the reset block 130 and / or DCG) as part of a readout chain of the pixel 400.

[0051] Figure 5 A simplified physical layout of another illustrative CIS pixel 500 having an integrated saddle gate source follower transistor 300 with a 2x4 photoreceptor 115 arrangement is shown in accordance with various embodiments. The illustrative layout is similar to that described with reference to FIG. 4, but with the 2x4 photoreceptor 115 arrangement. The pixel 500 includes a 2x4 array of photoreceptors 115, a reset block 130, a DCG 140, and a saddle gate source follower transistor 300. The DCG 140 is coupled with the floating diffusion node 415 through a floating diffusion interconnect 420. The floating diffusion node 415 is coupled with the gate contact 312 of the saddle gate source follower transistor 300 through the floating diffusion interconnect 420. The floating diffusion node 415 is also coupled with the source terminal of the reset block 130 and the DCG 140. The pixel 500 also includes a reset block 130 and a DCG 140. The DCG 140 is coupled with the floating diffusion node 415 through a floating diffusion interconnect 420. The floating diffusion node 415 is coupled with the gate contact 312 of the saddle gate source follower transistor 300 through the floating diffusion interconnect 420. The floating diffusion node 415 is also coupled with the source terminal of the reset block 130 and the DCG 140. Figure 4The described layout, except that the photosensor block 110 is divided into two zones, each having four photosensors 115, such that the CIS pixel 500 includes eight photosensors 115 in a 2x4 arrangement. In the illustrated implementation, all eight photosensors 115 are coupled with the floating diffusion node 415, either directly or via floating diffusion interconnects 420, and all eight photosensors 115 share in-pixel circuitry. For example, all eight photosensors 115 are coupled with the saddle gate source follower transistor 300 via floating diffusion interconnects 420. In some implementations, the 2x4 photosensor 115 arrangement uses two transistors for each of the reset block 130 and the DCG block 120 (e.g., one shown on top of the upper portion of the photosensor block 110a, and one shown below the lower portion of the photosensor block 110b). Where the imaging pixel 105 also includes a first oxide diffusion region for supporting a first reset block 130 coupled with the floating diffusion region; a second oxide diffusion region for supporting a select block 150 and a saddle gate source follower transistor block, such that the select block 150 shares a doped source region 350 implanted into the second oxide diffusion region with the saddle gate source follower transistor block; and a third oxide diffusion region for supporting a second reset block coupled with the floating diffusion region; and the 2x4 optical sensor array includes a first 2x2 optical sensor array disposed between the first oxide diffusion region and the second oxide diffusion region, and a second 2x2 optical sensor array disposed between the third oxide diffusion region and the second oxide diffusion region.

[0052] Figure 6 A simplified circuit schematic 600 of a CIS pixel according to various embodiments described herein is shown. The illustrated implementation is similar to the CIS pixel 500 with a 2x4 photosensor 115 arrangement of Figure 5 by removing the portion of the schematic 600 labeled 110b, the schematic 600 can represent an implementation similar to the CIS pixel 400 with a 2x2 photosensor 115 arrangement of Figure 4 The schematic 600 shows all of the photosensors 115 and the gates of the photosensor blocks 140 (implemented by the saddle gate source follower transistors 300) coupled with the floating diffusion node 415.

[0053] Embodiments of the saddle gate source follower transistor 300 can be fabricated in various ways, including those described above. Figure 7 An illustrative integrated circuit portion fabrication process 700 for fabricating a saddle gate source follower transistor 300 on a semiconductor substrate of an integrated circuit according to various embodiments is shown. For more clarity, Figures 8A-8D A portion of the fabrication process 700 is shown along Figure 7illustrative views of the saddle gate source follower transistor 800 in fabrication at various stages of the fabrication process 700. As can be seen, the illustrative results of the fabrication process 700, Figure 8D the saddle gate source follower transistor 800d in fabrication shown in Figure 3B is substantially the same as the saddle gate source follower transistor 300 shown in

[0054] Figure 7 The portion of the fabrication process 700 shown in begins at stage 705, where an isolation region 325, such as a shallow trench isolation (STI) region, is etched and filled (labeled “STI etch” and “STI fill”). In some embodiments, the etching as used herein is performed using photolithography. Such an isolation region 325 can isolate the source follower transistor from other components of the CIS, e.g., adjacent blocks of the CIS pixel into which the source follower block is incorporated. At stage 710, a “saddle etch” process can be performed. As Figure 8A shown, trenches 810 are etched into the substrate 205 and / or into the previously formed isolation region 325. These trenches 810 will define the sides of the channel region and will at least partially define the geometry of the shield 315 of the saddle gate structure 310.

[0055] In some embodiments, the fabrication process 700 proceeds at stages 720 and 730 by implanting a buried channel to serve as the channel region 330. Figure 8B and 8C stages 720 and 730, respectively. Figure 8B The vertical arrow 820 in represents a substantially vertical implant used to implant an upper portion of the buried channel into the substrate 205. Figure 8C The angled arrow 830 in represents an angled implant used to implant an axial side portion of the buried channel into the substrate 205 via the trench 810. Figure 8C Also shown in the preceding Figure 8B is the upper portion of the implanted buried channel (labeled 330a).

[0056] The fabrication process 700 can proceed at stages 740 and 750 by forming a gate oxide layer 320 (labeled “Gate ox”) and depositing and etching the saddle gate structure 310 (labeled “Poly deposit / etch”). The results of these stages can be seen in Figure 8D . From stage 740, it can be seen that the gate oxide layer 320 has been formed over the top of the channel region 330 and around the axial sides. Figure 8D For example, after the implantation stage, the gate oxide layer 320 can grow on the exposed surfaces of the substrate 205 around the top and sides of the channel region 330. From stage 750, it can be seen that the saddle gate structure 310 has been deposited and etched to form the saddle gate structure 310. Figure 8DAs seen, the saddle gate structure 310 is deposited and patterned to include a seat 313 extending over the top of the channel region 330 and a shield 315 extending down the axial sides of the channel region 330, all insulated from the channel region 330 by the dielectric properties of the gate oxide layer 320. The gate structure 310 can be formed, for example, by depositing polysilicon, masking the polysilicon region corresponding to the saddle gate structure 310, and etching the unmasked portions of the polysilicon to leave behind the saddle gate structure 310. As shown, the gate contact 312 can also be patterned onto the seat 313 of the saddle gate structure 310.

[0057] Prior to stages 740 and 750, the resulting channel region 330 of the saddle gate source follower transistor 300 can include an upper portion, which was implanted in stage 720 and is bounded at the top by the top surface of the substrate 205, and axial sides, which were implanted in stage 730 and are bounded at the etched side surfaces of the substrate 205 (i.e., the interior surfaces of the trench 810). The saddle gate structure 310 (and the gate oxide layer 320) can then be formed around the upper and axial implanted portions of the channel region 330 according to the top and etched side surfaces of the substrate that bound the channel region 330.

[0058] As can be seen, the manufacture of the gate oxide layer 320, the saddle gate structure 310, and other structures of the saddle gate source follower transistor 300 can be integrated with standard manufacturing process techniques, such as deposition and etching. Moreover, other stages of the manufacturing process 700 (including those prior to and after the illustrated stages) can be implemented according to standard manufacturing processes for MOSFETs, CIS components, and the like. However, certain aspects of the illustrated manufacturing process 700 are particularly suited to the context of the implantation described herein for the saddle gate source follower transistor 300. For example, conventional so-called FIN-FET transistors that include a gate wrapped around a portion of a channel region are typically performed in a manner different from the illustrated manufacturing process 700. For such FIN-FET transistors, the doped substrate can typically be formed in the shape of the channel region, and the gate can be deposited around the top and sides of the doped substrate, thereby manufacturing an independent (e.g., discrete) transistor component. Such a FIN-FET process does not include various stages of the illustrated manufacturing process 700, such as the etching and filling of the isolation region (stage 705), the saddle etch (stage 710), and the like.

[0059] Some modern CIS implementations are fabricated such that the planar layout width of the source follower is approximately 300 nm. With such processes, some implementations of the saddle gate source follower transistor 300 can be fabricated such that the shield 315 has a shield depth dimension 316 of approximately 155 nm and a width (thickness) of approximately 50 nm. Some implementations can use a high aspect ratio etch process that has been adopted in conjunction with certain memory and logic applications. In some embodiments, to maintain a desired amount of axial side buried channel implant (e.g., at stage 730 of fabrication process 700), the saddle gate structure 310 is fabricated with a shield depth dimension 316 that is approximately twice the planar width dimension 314. In such embodiments, the seat 313 effectively contributes W to the effective active width of the device, while the shield 315 contributes an additional 4W to the effective active width of the device, resulting in a total increase of five times the effective active width of the device.

[0060] It will be understood that when an element or component is referred to as being "connected to" or "coupled to" another element or component, it can be directly connected or coupled to the other element or component or intervening elements or components can be present. In contrast, when an element or component is referred to as being "directly connected to" or "directly coupled to" another element or component, there are no intervening elements or components present. It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, etc., these elements, components, regions, etc. should not be limited by these terms. These terms are only used to distinguish one element, component, region, etc. from another element, component, region, etc. Thus, a first element, component, region, etc. discussed below could be termed a second element, component, region, etc. without departing from the teachings of the present application. As used herein, the terms "logic low," "low state," "low level," "logic low level," "low," or "0" are used interchangeably. The terms "logic high," "high state," "high level," "logic high level," "high," or "1" are used interchangeably.

[0061] As used herein, the terms "a," "an," and "the" can include both singular and plural references. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "have," "has" and their variants, when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. In contrast, the term "consisting of, when used in this specification, specifies the stated features, steps, operations, elements, and / or components, and the exclusion of additional features, steps, operations, elements, and / or components. Furthermore, as used herein, the word "and / or" can refer to and encompass any possible combinations of one or more of the associated listed items.

[0062] While the application is described herein with reference to the illustrative embodiments, the description is not intended to be construed in a limiting sense. Rather, the illustrative embodiments serve to explain the spirit of the application. Numerous modifications and variations will become apparent to those skilled in the art once the spirit of the application has been appreciated. Accordingly, the appended claims as can pertain to any such modifications and variations are intended to cover all such modifications and variations.

[0063] Furthermore, some of the features of the preferred embodiments of this application can be used to advantage without the corresponding use of other features. As such, the foregoing description shall not be construed to be a limitation on the scope thereof and it is understood that numerous other variations are possible. It is intended to cover all modifications and variations of this application included within the scope of the appended claims and their equivalents. It is intended to cover all of the true spirit and scope of the application. The application is defined with respect to the claims.

Claims

1. A complementary metal oxide semiconductor (CMOS) imaging sensor (CIS), comprising: Imaging pixels include: semiconductor substrates; a photosensor block including at least one photosensor configured to accumulate photocharge in response to exposure to illumination and to transfer the accumulated photocharge to a floating diffusion region for readout; and an intra-pixel circuit system coupled to the floating diffusion region to convert the accumulated photocharge into a pixel output signal, the intra-pixel circuit system comprising: Saddle-gate source-follower transistor block, including: a channel region having a three-dimensional geometry, comprising: an upper portion having an axial length dimension and a planar width dimension, a first axial side portion defined by a first side trench to have the axial length dimension and a first protection depth dimension, and a second axial side portion defined by a second side trench to have the axial length dimension and the second protection depth dimension, the channel region being implanted with a channel dopant; a gate oxide layer formed over at least an upper portion of the channel region, the first axial side, and the second axial side; and a saddle gate structure formed on the gate oxide layer to have a seat portion extending over the upper portion of the channel region, a first guard portion extending over the first axial side of the channel region, and a second guard portion extending over the second axial side of the channel region, The first protection portion and the second protection portion are buried below the upper surface of the semiconductor substrate; In which, the imaging pixel also includes: a first oxide diffusion region for supporting a first reset block coupled to the floating diffusion region; and a second oxide diffusion region for supporting a selection block and the saddle gate source follower transistor block, so that the selection block and the saddle gate source follower transistor block share an impurity-doped source region injected into the second oxide diffusion region.

2. The CIS according to claim 1, wherein: The saddle gate source follower transistor block further includes: filling a first side isolation region formed in a first isolation trench with an electrical isolation material, the first isolation trench being etched along at least the axial length to a first isolation trench depth deeper than the first trench depth in the semiconductor substrate; and filling an electrical isolation material into a second side isolation region formed in a second isolation trench, wherein the second isolation trench is etched along at least the axial length to a second isolation trench depth in the semiconductor substrate that is deeper than the second trench depth, The first side trench is etched into the electrically isolating material of the first isolation trench, and the second side trench is etched into the electrically isolating material of the second isolation trench.

3. The CIS according to claim 1, wherein: The saddle gate source follower transistor block further includes: A source region and a drain region are implanted into the semiconductor substrate, the source region is located at a first axial end of the channel region, and the drain region is located at a second axial end of the channel region, the second axial end is opposite to the first axial end and is separated from the first axial end by a distance corresponding to the axial length.

4. The CIS according to claim 1, wherein: The channel region is implanted with the channel dopant, so that the channel region comprises: an upper implantation portion formed by implanting the channel dopant into the upper portion of the channel region; a first axial side implant formed by angledly implanting the channel dopant into the first axial side of the channel region through the first side trench before forming the gate oxide layer and the saddle gate structure; and The second axial side implant portion is formed by implanting the channel dopant at an angle into the second axial side portion of the channel region through the second side trench before forming the gate oxide layer and the saddle gate structure.

5. The CIS according to claim 1, wherein: The saddle gate source follower transistor block further includes: A gate contact is patterned onto the saddle gate structure and coupled to the floating diffusion region.

6. The CIS according to claim 1, wherein: Each of the first protection depth dimension and the second protection depth dimension is greater than or equal to the planar width dimension.

7. The CIS according to claim 1, wherein: The photosensor block includes a 2×2 photosensor array, and all photosensors share the floating diffusion region for readout.

8. The CIS according to claim 1, wherein: The photosensor block includes a 2×4 photosensor array, and all photosensors share the floating diffusion region for readout.

9. The CIS according to claim 8, wherein: The imaging pixel further includes: a third oxide diffusion region for supporting a second reset block coupled to the floating diffusion region; and The 2×4 optical sensor array includes a first 2×2 optical sensor array disposed between the first oxide diffusion region and the second oxide diffusion region, and a second 2×2 optical sensor array disposed between the third oxide diffusion region and the second oxide diffusion region.

10. The CIS according to claim 2, wherein: The electrical isolation material is one of undoped polysilicon or silicon dioxide.

11. A method for fabricating a saddle-gate source-follower transistor block, the method comprising: The channel region of the saddle-gate source follower transistor block is formed by: Etching a first side trench along an axial length of the semiconductor substrate to a first trench depth; etching a second side trench along the axial length of the semiconductor substrate to a second trench depth, the second side trench being substantially parallel to the first side trench and separated from the first side trench by a horizontal distance, Such that the three-dimensional geometry of the channel region includes an upper portion, a first axial side portion, and a second axial side portion defined by the axial length, the horizontal distance, the first trench depth, and the second trench depth; and implanting channel dopants into the semiconductor substrate according to the three-dimensional geometric shape of the channel region; forming a gate oxide layer on the semiconductor substrate at least above the upper portion, the first axial side, and the second axial side of the channel region; and forming a saddle gate structure on the gate oxide layer to have: a seat portion extending over the upper portion of the channel region to have a planar width dimension corresponding to the horizontal distance, a first guard portion extending over the first axial side of the channel region to have a first guard depth dimension corresponding to the first trench depth, and a second guard portion extending over the second axial side of the channel region to have a second guard depth dimension corresponding to the second trench depth; The method is applied to the CIS according to any one of claims 1 to 10.

12. The method according to claim 11, further comprising: The side isolation regions are formed by: etching a first isolation trench along at least the axial length to a first isolation trench depth deeper than the first trench depth; etching a second isolation trench along at least the axial length to a second isolation trench depth deeper than the second trench depth; and filling the first isolation trench and the second isolation trench with an electrical isolation material; The first side trench is etched into the electrically isolating material of the first isolation trench, and the second side trench is etched into the electrically isolating material of the second isolation trench.

13. The method according to claim 11, further comprising: A source region and a drain region are implanted into the semiconductor substrate, the source region being located at a first axial end of the channel region, and the drain region being located at a second axial end of the channel region, the second axial end being opposite to the first axial end and being separated from the first axial end by a distance corresponding to the axial length.

14. The method according to claim 11, wherein Implanting channel dopants into the semiconductor substrate according to the three-dimensional geometric shape of the channel region comprises: First, implanting the channel dopant into the upper portion of the channel region to form an upper implant portion; and Next, the channel dopant is implanted into each of the first axial side portion and the second axial side portion of the channel region via the first side trench and the second side trench respectively to form a first axial side implant portion and a second axial side implant portion.

15. The method according to claim 11, further comprising: A gate contact is patterned onto the saddle gate structure.

16. The method according to claim 11, wherein The first trench depth is nominally equal to the second trench depth.

17. The method according to claim 11, wherein Each of the first protection depth dimension and the second protection depth dimension is greater than or equal to the planar width dimension.

18. The method of claim 11, wherein: The upper portion of the channel region has a planar length dimension corresponding to the axial length and a planar width dimension corresponding to the horizontal distance; The first axial side surface of the channel region has a first side length dimension corresponding to the axial length and a first side depth dimension corresponding to the first trench depth; and The second axial side surface has a second side length dimension corresponding to the axial length and a second side depth dimension corresponding to the second groove depth.

Images