Electronic substrate and electronic device

Abstract

An electronic substrate and an electronic device. The electronic substrate includes a first functional area, a second functional area and a peripheral area; the first functional area includes an opening, the second functional area is located in the opening, and the peripheral area includes an opening peripheral area located between the first functional area and the second functional area; the electronic substrate includes a substrate substrate and a detection wiring structure located on the substrate substrate; the detection wiring structure includes a first conductive wiring and a second conductive wiring located in the opening peripheral area, the first conductive wiring and the second conductive wiring extend from a first position respectively in the opposite direction along the edge of the second functional area and respectively partially surround the second functional area, and the first conductive wiring and the second conductive wiring have a spacing between each other at the first position; the first conductive wiring and the second conductive wiring are spaced from each other in a direction perpendicular to the substrate substrate by an insulating layer and are electrically connected to each other at the second position. The electronic substrate can optimize the detection wiring structure in the opening peripheral area.

Description

[0001] This application claims priority to Chinese Patent Application No. 202011137662.5 filed on October 22, 2020, the full text of which is incorporated by reference as a part of this application. Technical Field

[0002] Embodiments of the present disclosure relate to an electronic substrate and an electronic device. Background Art

[0003] With the rapid development and widespread application of electronic products, how to reduce the production cost of electronic products and how to improve the yield of electronic products have become one of the key issues that need to be solved. For example, a detection circuit can be used to detect whether there are problems such as circuit breakage and circuit failure in electronic products, thereby improving the yield of electronic products and reducing the production cost of electronic products. Summary of the invention

[0004] At least one embodiment of the present disclosure provides an electronic substrate, which includes a first functional area, a second functional area and a peripheral area surrounding the first functional area; the first functional area includes an opening, the second functional area is located in the opening, the peripheral area includes an opening peripheral area at least partially located in the opening, the opening peripheral area at least partially surrounds the second functional area and is located between the second functional area and the first functional area; the electronic substrate includes a base substrate and a detection wiring structure located on the base substrate, the detection wiring structure is arranged along the edge of the peripheral area, the first end of the detection wiring structure is configured to be connected to a detection signal source, and the second end of the detection wiring structure is configured to be connected to a detection circuit; the detection wiring structure includes a first conductive trace and a second conductive trace located in the opening peripheral area and at least partially surrounding the second functional area, the first conductive trace and the second conductive trace The first conductive trace and the second conductive trace respectively extend in reverse direction from the first position along the edge of the second functional area and partially surround the second functional area respectively, the first conductive trace and the second conductive trace are spaced from each other at the first position, and the contours of the orthographic projections of the first conductive trace and the second conductive trace on the substrate at least partially surround the orthographic projection of the second functional area on the substrate, so that the orthographic projection of the second functional area on the substrate is located in the area enclosed by the orthographic projections of the first conductive trace and the second conductive trace on the substrate; the electronic substrate comprises a first electrode layer, an insulating layer and a second electrode layer stacked in sequence on the substrate, the first conductive trace is located in the first electrode layer, the second conductive trace is located in the second electrode layer, the first conductive trace and the second conductive trace are spaced from each other in a direction perpendicular to the substrate through the insulating layer and are electrically connected to each other at the second position.

[0005] For example, in the electronic substrate provided in one embodiment of the present disclosure, the orthographic projection of the first conductive trace on the substrate and the orthographic projection of the second conductive trace on the substrate at least partially overlap with each other at the second position, and the first conductive trace and the second conductive trace are electrically connected to each other at the second position through a via structure that at least penetrates the insulating layer.

[0006] For example, in the electronic substrate provided in an embodiment of the present disclosure, there is a distance between the second position and the first position in the circumferential direction along the edge of the second functional area.

[0007] For example, in the electronic substrate provided in an embodiment of the present disclosure, in the circumferential direction along the edge of the second functional area, the distance between the first position and the second position is greater than or equal to 1 / 4 of the circumference of the edge of the second functional area.

[0008] For example, in an electronic substrate provided in an embodiment of the present disclosure, the opening peripheral area includes a first cofferdam area, a second cofferdam area and a spacing area, the first cofferdam area at least partially surrounds the first functional area, the spacing area at least partially surrounds the first cofferdam area, and the second cofferdam area at least partially surrounds the spacing area, the electronic substrate includes a first cofferdam structure and a second cofferdam structure, the first cofferdam structure is located in the first cofferdam area, the second cofferdam structure is located in the second cofferdam area, the first conductive trace is at least located between the second cofferdam area and the second functional area, the second conductive trace is at least located between the second cofferdam area and the second functional area, and in a direction perpendicular to the substrate, the first conductive trace and the second conductive trace are located on the side of the first cofferdam structure and the second cofferdam structure away from the substrate.

[0009] For example, the electronic substrate provided by an embodiment of the present disclosure also includes at least one first dummy electrode pattern and at least one second dummy electrode pattern located in the peripheral area of ​​the opening, the at least one first dummy electrode pattern and the at least one second dummy electrode pattern are located between the first functional area and the first cofferdam area, the at least one first dummy electrode pattern is located in the first electrode layer, and is spaced and insulated from the first conductive trace and the second conductive trace, respectively, and the at least one second dummy electrode pattern is located in the second electrode layer, and is spaced and insulated from the first conductive trace and the second conductive trace, respectively.

[0010] For example, in the electronic substrate provided in one embodiment of the present disclosure, the orthographic projection of the at least one first dummy electrode pattern on the base substrate at least partially surrounds the first functional area, the orthographic projection of the at least one second dummy electrode pattern on the base substrate at least partially surrounds the first functional area, and the orthographic projection of the at least one first dummy electrode pattern on the base substrate is located on a side of the orthographic projection of the at least one second dummy electrode pattern on the base substrate away from the first functional area.

[0011] For example, the electronic substrate provided by an embodiment of the present disclosure also includes a connecting wiring pattern, which is located at least in the opening peripheral area and partially surrounds the first functional area, and the first end and the second end of the connecting wiring pattern extend into the first functional area respectively; in the opening peripheral area, the orthographic projection of at least part of the connecting wiring pattern on the base substrate is located on the side of the orthographic projection of the at least one first dummy electrode pattern on the base substrate away from the second functional area, the connecting wiring pattern and the at least one first dummy electrode pattern are spaced and insulated from each other, and the connecting wiring pattern partially overlaps and is insulated from the at least one second dummy electrode pattern in a direction perpendicular to the base substrate.

[0012] In the opening peripheral area, the orthographic projection of the connecting wiring pattern on the base substrate is located between the orthographic projection of the at least one first dummy electrode pattern on the base substrate and the orthographic projection of the at least one second dummy electrode pattern on the base substrate, the connecting wiring pattern and the at least one first dummy electrode pattern are spaced and insulated from each other, and the connecting wiring pattern and the at least one second dummy electrode pattern are spaced and insulated from each other.

[0013] For example, in the electronic substrate provided in an embodiment of the present disclosure, the connection wiring pattern is located in the first electrode layer or the second electrode layer.

[0014] For example, in the electronic substrate provided in one embodiment of the present disclosure, in the circumferential direction along the edge of the second functional area, the first end of the connecting wiring pattern has a spacing with the first position and the second position respectively, and the second end of the connecting wiring pattern has a spacing with the first position and the second position respectively.

[0015] For example, in an electronic substrate provided in an embodiment of the present disclosure, the first cofferdam structure includes at least one layer of insulating structure, and the second cofferdam structure includes at least one layer of insulating structure.

[0016] For example, in an electronic substrate provided in an embodiment of the present disclosure, the first conductive trace and the second conductive trace form an arc-shaped trace structure including a protruding portion, and the protruding portion is at least located at the second position.

[0017] For example, in an electronic substrate provided in an embodiment of the present disclosure, the second position is at least located between the first cofferdam area and the first functional area.

[0018] For example, in the electronic substrate provided in an embodiment of the present disclosure, the first conductive trace and the second conductive trace form an arc-shaped trace structure, and the second position is at least located between the second cofferdam area and the second functional area.

[0019] For example, in the electronic substrate provided in one embodiment of the present disclosure, the detection wiring structure also includes a third conductive wiring and a fourth conductive wiring located in the peripheral area of ​​the opening, the third conductive wiring is located in the first electrode layer, and is connected to the first conductive wiring at one end of the first conductive wiring close to the first position, the fourth conductive wiring is located in the second electrode layer, and is connected to the second conductive wiring at one end of the second conductive wiring close to the first position, and the third conductive wiring and the fourth conductive wiring respectively extend approximately in a straight line from the first position in a direction away from the center of the second functional area.

[0020] For example, in an electronic substrate provided in an embodiment of the present disclosure, the detection routing structure also includes a first routing portion and a second routing portion, the first routing portion includes a first connection end and a second connection end, the first connection end of the first routing portion serves as the first end or the second end of the detection routing structure, the second connection end of the first routing portion is configured to be connected to the third conductive routing, the second routing portion includes a first connection end and a second connection end, the first connection end of the second routing portion serves as the second end or the first end of the detection routing structure, the second connection end of the second routing portion is configured to be connected to the fourth conductive routing, and the first routing portion, the third conductive routing, the first conductive routing, the second conductive routing, the fourth conductive routing and the second routing portion are sequentially connected to each other between the detection signal source and the detection circuit.

[0021] For example, in the electronic substrate provided in one embodiment of the present disclosure, the first routing portion includes a fifth conductive routing at least partially located in the first functional area, the second routing portion includes a sixth conductive routing at least partially located in the first functional area, the fifth conductive routing and the sixth conductive routing are located in the first electrode layer, the fifth conductive routing is connected to the third conductive routing and is integrally arranged, and the sixth conductive routing is electrically connected to the fourth conductive routing through a via structure that at least penetrates the insulating layer.

[0022] For example, in the electronic substrate provided in an embodiment of the present disclosure, the detection wiring structure extends substantially along an edge contour of the peripheral area on a side away from the first functional area.

[0023] For example, in an electronic substrate provided in an embodiment of the present disclosure, the electronic substrate includes a touch substrate, the first functional area is configured as a touch area, the touch substrate includes a touch electrode structure located on the base substrate, the touch electrode structure is at least partially located in the first functional area, the first part of the touch electrode structure is located in the first electrode layer, and the second part of the touch electrode structure is located in the second electrode layer.

[0024] At least one embodiment of the present disclosure further provides an electronic device, which includes the electronic substrate described in any embodiment of the present disclosure, and the electronic substrate is configured as a display substrate or a touch substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0026] Figure 1 It is a planar schematic diagram of an electronic product with a display function;

[0027] Figure 2A for Figure 1 A partial enlarged schematic diagram of the area AR11 shown in FIG.

[0028] Figure 2B For along Figure 2A A schematic diagram of a partial cross-sectional structure of the AA' line shown in FIG.

[0029] Figure 2C For along Figure 2A A schematic diagram of a partial cross-sectional structure of line EE' shown in FIG.

[0030] Figure 3 A schematic plan view of an electronic substrate provided for some embodiments of the present disclosure;

[0031] Figure 4A for Figure 3 An example of a partially enlarged schematic diagram of the area AR21 shown in FIG.

[0032] Figure 4B for Figure 4A A schematic diagram of a method for connecting a first conductive trace and a second conductive trace as shown in ;

[0033] Figure 5A For along Figure 4A A schematic diagram of a partial cross-sectional structure of line BB' shown in FIG.

[0034] Figure 5B For along Figure 4A A schematic diagram of a partial cross-sectional structure of line DD' shown in FIG.

[0035] Fig. 6A For along Figure 4A A schematic diagram of a partial cross-sectional structure of the CC' line shown in;

[0036] Figure 6B for Fig. 6A A schematic diagram of an example of a multi-layer insulation structure including the first cofferdam structure and the second cofferdam structure shown in FIG.

[0037] Figure 7 For along Figure 4A A schematic diagram of a partial cross-sectional structure of the FF' line shown in;

[0038] Figure 8 A schematic plan view of another electronic substrate provided for some embodiments of the present disclosure;

[0039] Fig. 9A for Figure 3 A partially enlarged schematic diagram of another example of the area AR21 shown in FIG.

[0040] Fig. 9B for Fig. 9A A partial enlarged schematic diagram of the area AR31 shown in FIG.

[0041] Fig. 9C for Fig. 9A A partial enlarged schematic diagram of the area AR32 shown in FIG.

[0042] Fig.10 for Figure 3 A partial enlarged schematic diagram of another example of the area AR21 shown in FIG.

[0043] Fig.11 A schematic diagram of a connection method between a detection wiring structure in an electronic substrate, a detection signal source, and a detection circuit provided in some embodiments of the present disclosure;

[0044] Fig.12 A schematic diagram of a connection method between a detection wiring structure in another electronic substrate, a detection signal source, and a detection circuit provided in some embodiments of the present disclosure;

[0045] Fig.13 A schematic diagram of an example of a partial cross-sectional structure of a first functional region of an electronic substrate provided in some embodiments of the present disclosure;

[0046] Fig.14A A schematic diagram of another example of a partial cross-sectional structure of a first functional region of an electronic substrate provided in some embodiments of the present disclosure;

[0047] Fig. 14BA schematic diagram of another example of a partial cross-sectional structure of a first functional region of an electronic substrate provided in some embodiments of the present disclosure; and

[0048] Fig.15 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0050] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0051] At present, in order to detect whether the preparation process has an adverse effect on the device performance or line connection in the electronic product, for example, whether the line on the electronic substrate is broken or has poor contact when the electronic substrate is cut, a circle of metal routing for panel crack detection (PCD) is usually set in the border area of ​​the electronic product along the outer edge of the electronic product.

[0052] Compared with other routing lines in the electronic product, the metal routing line is usually set at the position closest to the outer edge of the electronic product, such as the position closest to the cutting line when the electronic substrate is subjected to the cutting process. Therefore, by detecting the transmission of the electrical signal on the metal routing line, it can be determined whether the metal routing line has been subjected to adverse effects such as line breaking or poor contact during the preparation process (such as cutting), and further it can be determined whether the preparation process has caused adverse effects such as line breaking or poor contact to other routing lines or devices in the electronic product. For example, when it is determined that the electrical signal on the metal routing line can be transmitted normally, it can be basically determined that no adverse effects such as line breaking are caused to the line connection in the electronic product during the cutting process. Usually, based on the line layout in the border area and the narrow border design requirements of the electronic product, the above-mentioned metal routing lines in the border area usually adopt a single-layer routing structure.

[0053] With the widespread application of electronic products, users have further improved their requirements for functions and appearance of electronic products. In order to meet the different actual needs of users, the appearance or functional areas of electronic products sometimes need to be designed into irregular or special shapes. However, for electronic products with irregular or special shapes, the metal wiring of the above single-layer wiring structure is often difficult to achieve good detection results.

[0054] Figure 1 It is a planar schematic diagram of an electronic product with a display function. Figure 2A for Figure 1 A partial enlarged schematic diagram of the area AR11 shown in FIG. Figure 2B For along Figure 2A A schematic diagram of a partial cross-sectional structure of the AA' line shown in FIG. Figure 2C For along Figure 2A Schematic diagram of the partial cross-sectional structure of the EE' line shown in FIG.

[0055] For example, combined with Figure 1 as well as Figures 2A-2C As shown, the electronic product 10 includes a display area 101 and a frame area 102 surrounding the display area 101. The display area 101 is designed to have an irregular shape with an opening obtained by cutting, for example. The electronic product 10 can arrange devices such as a camera and a distance sensor in the opening of the display area 101, that is, the device is exposed through the opening so as to receive external light, for example, Figure 1 The electronic product 10 is arranged in the area 103 shown in FIG. 1 , thereby facilitating a narrow frame design of the electronic product 10 .

[0056] In order to avoid adverse effects on the functional layers of the display device in the display area 101, for example, two cofferdam structures 1041 and 1042 with different heights may be provided in the frame area 102 surrounding the display area 101 (for example, Figure 2C As shown, the maximum heights of the cofferdam structures 1041 and 1042 relative to the substrate 110 are different), and the organic film layers such as the pixel defining layer and the flat layer between the two cofferdam structures 1041 and 1042 are removed as much as possible to form a "groove" area. Furthermore, after packaging, the formed packaging layer can effectively prevent, for example, water vapor or oxygen from penetrating into the display area 101 of the electronic product 10, such as the interior of the display device or other devices.

[0057] When preparing the metal routing 105 for the above-mentioned panel circuit breaking detection in the border area 102, since the metal routing 105 needs to be set at a position close to the cutting line, for example, the metal routing 105 needs to be set on the side of the cofferdam structures 1041 and 1042 in the border area 102 away from the display area 101 to improve the accuracy and reliability of the detection results obtained using the metal routing 105.

[0058] Since a cutting process is also required when forming the area 103 in the opening, a metal trace 105 for panel disconnection detection also needs to be set in the partial border area 1021 surrounding the area 103 to ensure that in the process of forming the area 103 by the cutting process, no adverse effects such as circuit disconnection or poor contact are caused to the traces or devices located near the area 103 in the electronic product 10.

[0059] However, since the size of the part of the frame area 1021 between the display area 101 and the area 103 is relatively small, the spacing between the metal wiring 105 and the cofferdam structures 1041 and 1042 is also relatively small, for example, the spacing between the metal wiring 105 and the adjacent cofferdam structures 1042 is relatively small. The film thickness of the cofferdam structures 1041 and 1042 is often large, for example, greater than or even much greater than the film thickness of the metal wiring 105, so when forming the metal wiring 105, it is often easy to have a large amount of metal residue caused by factors such as film discontinuity. For example, Figure 2A and Figure 2B As shown, when performing an exposure process to form metal wiring 105, a large amount of metal material is likely to remain in the "groove" area formed between the cofferdam structures 1041 and 1042, resulting in a short circuit between the lines in this part of the border area 1021.

[0060] For example, in Figure 2AIn the area AR12 shown in FIG. 1 , since the left metal trace 105 and the right metal trace 105 extending in parallel in the same direction need to extend from the side of the cofferdam structures 1041 and 1042 away from the display area 101 (that is, the side close to the area 103) to the side close to the display area 101 and cover the cofferdam structures 1041 and 1042, it is easy to cause the following when forming the left metal trace 105 and the right metal trace 105: Figure 2B For example, a large amount of metal residue is easily generated on the left and right sides of the left metal trace 105 and the right metal trace 105, and because the distance between the left metal trace 105 and the right metal trace 105 in the area AR12 is very close, the left metal trace 105 and the right metal trace 105 may appear as shown in FIG. Figure 2B As shown in the situation, a short circuit caused by residual metal material is very likely to occur between the left metal routing 105 and the right metal routing 105. Therefore, it is difficult to effectively detect the signal transmission status in the border area 1021 surrounding the area 103 through the metal routing 105.

[0061] At least one embodiment of the present disclosure provides an electronic substrate, which includes a first functional area, a second functional area and a peripheral area surrounding the first functional area; the first functional area includes an opening, the second functional area is located in the opening, and the peripheral area includes an opening peripheral area at least partially located in the opening, the opening peripheral area at least partially surrounds the second functional area and is located between the second functional area and the first functional area; the electronic substrate includes a substrate substrate and a detection wiring structure located on the substrate substrate, the detection wiring structure is arranged along the edge of the peripheral area, the first end of the detection wiring structure is configured to be connected to a detection signal source, and the second end of the detection wiring structure is configured to be connected to a detection circuit; the detection wiring structure includes a first conductive wiring and a second conductive wiring located in the opening peripheral area and at least partially surrounding the second functional area, the first conductive wiring and the second The conductive traces extend from the first position in reverse direction along the edge of the second functional area and partially surround the second functional area respectively. The first conductive trace and the second conductive trace are spaced apart from each other at the first position. The contours of the orthographic projections of the first conductive trace and the second conductive trace on the substrate at least partially surround the orthographic projection of the second functional area on the substrate, so that the orthographic projection of the second functional area on the substrate is located within the area enclosed by the orthographic projections of the first conductive trace and the second conductive trace on the substrate. The electronic substrate includes a first electrode layer, an insulating layer and a second electrode layer stacked in sequence on the substrate, the first conductive trace is located in the first electrode layer, the second conductive trace is located in the second electrode layer, the first conductive trace and the second conductive trace are spaced apart from each other in a direction perpendicular to the substrate through the insulating layer and are electrically connected to each other at the second position.

[0062] In the electronic substrate provided by the above-mentioned embodiment of the present disclosure, by making the first conductive trace and the second conductive trace located in the opening peripheral area respectively located in different first electrode layers and second electrode layers, and making the first conductive trace and the second conductive trace spaced apart from each other in the direction perpendicular to the substrate through the insulating layer, the short circuit phenomenon or other electrical poor phenomena caused by factors such as material residue when forming the first conductive trace and the second conductive trace in the electronic substrate can be effectively reduced or avoided. Thus, the signal transmission condition of the detection trace structure in the opening peripheral area can be effectively detected by the first conductive trace and the second conductive trace, and the accuracy and reliability of the detection results obtained by using the detection trace structure can be improved, thereby improving the yield of the electronic substrate, reducing the production cost, and improving the reliability and stability of the electronic substrate, and optimizing the overall performance of the electronic substrate.

[0063] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals in different drawings will be used to refer to the same elements that have been described.

[0064] Figure 3 A schematic plan view of an electronic substrate provided in some embodiments of the present disclosure, Figure 4A for Figure 3 An example of a partially enlarged schematic diagram of the area AR21 shown in FIG. Figure 4B for Figure 4A A schematic diagram of a method for connecting a first conductive trace and a second conductive trace shown in FIG. Figure 5A For along Figure 4A Schematic diagram of the partial cross-sectional structure of the BB' line shown in FIG.

[0065] For example, combined with Figures 3 to 5A As shown, the electronic substrate 20 includes a first functional area 201, a second functional area 202, and a peripheral area 203 surrounding the first functional area 201. For example, the first functional area 201 and the second functional area 202 can be configured to have the same functions such as display and touch, or can also be configured to have different functions.

[0066] For example, taking the electronic substrate 20 as a display substrate as an example, the first functional area 201 is configured as a display area, and the second functional area 202 can also be configured as a display area, or it can also be configured as an area with other functions different from the display function, such as a touch area, a camera area, etc.; for example, taking the electronic substrate 20 as a touch substrate as an example, the first functional area 201 is configured as a touch area, and the second functional area 202 can also be configured as a touch area, or it can also be configured as an area with other functions different from the touch function, such as a display area, a camera area, etc.; for example, taking the electronic substrate 20 as a substrate having both display and touch functions as an example, the first functional area 201 is configured as an area having both display and touch functions, and the second functional area 202 can be configured as an area with other functions, such as a camera area, etc. The embodiments of the present disclosure do not impose specific restrictions on this.

[0067] The first functional area 201 includes an opening, and the second functional area 202 is located in the opening. For example, the opening may be Figure 3 The electronic substrate 20 shown in the figure is a closed opening obtained by cutting, for example; or, in some other embodiments, the opening may also be, for example Figure 8 The electronic substrate 30 shown is obtained by, for example, cutting and formed on one side (or multiple sides) of the first functional area 201. In the area where the opening is located, for example, in the second functional area 202 located in the opening, devices such as cameras and distance sensors can be arranged, thereby facilitating the realization of a narrow frame design of the electronic substrate.

[0068] It should be noted that the embodiment of the present disclosure does not impose any specific restrictions on the shape or contour of the electronic substrate 20. For example, the electronic substrate provided by the embodiment of the present disclosure may be as follows: Figure 3 or Figure 8 The square shape shown may also be other suitable regular shapes or irregular shapes such as a circle, a regular hexagon, a regular octagon, etc., and the embodiments of the present disclosure are not limited to this.

[0069] It should be noted that the embodiments of the present disclosure are based on Figure 3 The structure and function of the electronic substrate 20 are described by taking the closed opening shown in the figure as an example, but this does not constitute a limitation on the present disclosure. The embodiments of the present disclosure do not limit the setting position and form of the opening in the electronic substrate 20.

[0070] It should be noted that the embodiments of the present disclosure do not impose any specific restrictions on the number, shape or profile of the openings. For example, the number of openings in the embodiments of the present disclosure may be as follows: Figure 3 1 as shown in , or it may be 2, 3 or more; the openings in the embodiments of the present disclosure may be as shown in Figure 3The circle shown in the figure may also be other suitable regular shapes or irregular shapes such as square, regular hexagon, regular octagon, etc., and the embodiments of the present disclosure are not specifically limited to this.

[0071] The peripheral region 203 includes an opening peripheral region 2031 at least partially located in the opening, and the opening peripheral region 2031 at least partially surrounds the second functional region 202 and is located between the second functional region 202 and the first functional region 201. Figure 3 In the embodiment shown, the opening peripheral area 2031 is entirely located in the opening, and the opening peripheral area 2031 surrounds the entire area of ​​the second functional area 202. Figure 8 In the illustrated embodiment, the opening peripheral region 2031 is only partially located in the opening, and the opening peripheral region 2031 surrounds a portion of the second functional region 202 along a partial edge of the second functional region 202 .

[0072] like Figures 3 to 5A As shown, the electronic substrate 20 includes a base substrate 210 and a detection wiring structure (for example, including a first conductive wiring 221 and a second conductive wiring 222) located on the base substrate 210. The first end of the detection wiring structure is configured to be connected to the detection signal source 410, and the second end of the detection wiring structure is configured to be connected to the detection circuit 420. Therefore, by judging whether the detection wiring structure can form a normal signal transmission path between the detection signal source 410 and the detection circuit 420, it can be determined whether the detection wiring structure is adversely affected by, for example, a line break or poor contact.

[0073] For example, according to the function of the electronic substrate 20, the electronic substrate 20 may also include a display drive circuit layer and a light emitting element layer (corresponding to the display substrate), or the electronic substrate 20 may also include a touch circuit layer (corresponding to the touch substrate). The detection wiring structure may be formed by the same preparation process as one or more layers of the film layers included in the display drive circuit layer, the light emitting element layer or the touch circuit layer, or may be prepared separately, and the embodiments of the present disclosure are not limited to this.

[0074] For example, the detection wiring structure of the electronic substrate 20 can be prepared before the cutting process is performed, and after the preparation is completed, it is detected to determine whether the detection wiring structure can form a normal signal transmission path. If it can form a normal signal transmission path, it enters the following process. The detection wiring structure is set along the edge of the peripheral area 203, for example, it can be set along the cutting edge of the peripheral area 203. For example, after the electronic substrate 20 is subjected to the cutting process, the detection wiring structure is detected again, so that by judging the signal transmission situation on the detection wiring structure, it can be determined whether the cutting process or other preparation processes in the preparation process of the electronic substrate 20 cause adverse effects such as line disconnection or poor contact on the detection wiring structure, and then it can be determined based on the detection result of the detection wiring structure whether other wiring or devices in the electronic substrate 20 are subjected to adverse effects such as line disconnection or poor contact during the preparation process.

[0075] The detection wiring structure includes a first conductive wiring 221 and a second conductive wiring 222 located in the opening peripheral area 2031 and at least partially surrounding the second functional area 202. Figure 4A As shown, the first conductive trace 221 and the second conductive trace 222 substantially surround the entire area of ​​the second functional area 202 except the upper end portion. The first conductive trace 221 and the second conductive trace 222 extend from the first position P1 in the opposite direction along the edge of the second functional area 202 and respectively partially surround the second functional area 202. For example, Figure 4A As shown, the first conductive trace 221 extends from the first position P1 along the edge of the second functional area 202 in a counterclockwise direction to surround the left edge of the second functional area 202; the second conductive trace 222 extends from the first position P1 along the edge of the second functional area 202 in a clockwise direction to surround the right edge of the second functional area 202. The first conductive trace 221 and the second conductive trace 222 are spaced apart from each other at the first position P1; for example, Figure 4A As shown, at the first position P1 , the first conductive trace 221 and the second conductive trace 222 are spaced apart from each other in the first direction R1 .

[0076] The contour of the orthographic projection of the first conductive trace 221 and the second conductive trace 222 on the base substrate 210 at least partially surrounds the orthographic projection of the second functional region 202 on the base substrate 210, for example, Figure 4AAs shown, the contour of the orthographic projection of the first conductive trace 221 and the second conductive trace 222 on the base substrate 210 surrounds the other parts of the orthographic projection of the second functional area 202 on the base substrate 210 except the upper end part, so that the orthographic projection of the second functional area 202 on the base substrate 210 is located in the area surrounded by the orthographic projections of the first conductive trace 221 and the second conductive trace 222 on the base substrate 210. For example, Figure 4A As shown, the second functional area 202 is located in an area surrounded by an arc-shaped wiring structure formed by the first conductive wiring 221 and the second conductive wiring 222 .

[0077] It should be noted that the first position P1 may refer to a certain point, or may refer to a certain area or a certain part. Figure 4A Taking the embodiment shown as an example, the first position P1 may refer to the center point between the upper end of the first conductive trace 221 and the upper end of the second conductive trace 222 in the first direction R1, for example, the midpoint of the line between the upper end of the first conductive trace 221 and the upper end of the second conductive trace 222.

[0078] It should be noted that the first conductive trace 221 and the second conductive trace 222 can be as follows: Figure 4A As shown, they extend along the edge of the second functional area 202 in a roughly smooth arc shape, or they may extend along the edge of the second functional area 202 in a zigzag shape, a sawtooth shape, or other suitable shapes. The embodiments of the present disclosure do not limit the specific extension shapes of the first conductive trace 221 and the second conductive trace 222, as long as the overall extension direction of the first conductive trace 221 is the extension direction (for example, the circumferential direction) along the edge of the second functional area 202 and the overall extension direction of the second conductive trace 222 is the extension direction (for example, the circumferential direction) along the edge of the second functional area 202.

[0079] like Figures 3 to 5A As shown, the electronic substrate 20 includes a first electrode layer 231, an insulating layer 233, and a second electrode layer 232 which are sequentially stacked on a base substrate 210, a first conductive trace 221 is located in the first electrode layer 231, and a second conductive trace 222 is located in the second electrode layer 232. The first conductive trace 221 and the second conductive trace 222 are spaced apart from each other in a direction R3 perpendicular to the base substrate 210 through the insulating layer 233 and are electrically connected to each other at a second position P2. Thus, by electrically connecting the first conductive trace 221 and the second conductive trace 222 to each other at the second position P2, the first conductive trace 221 and the second conductive trace 222 can form a signal transmission path surrounding the second functional area 202, so as to realize the detection of the signal transmission status in the opening peripheral area 2031 surrounding the second functional area 202 by using the detection trace structure.

[0080] In the embodiment of the present disclosure, on the basis of using the first conductive trace 221 and the second conductive trace 222 to realize the detection trace structure to detect the signal transmission situation in the opening peripheral area 2031, the first conductive trace 221 and the second conductive trace 222 are respectively arranged in different first electrode layers 231 and second electrode layers 232, and the first conductive trace 221 and the second conductive trace 222 are spaced apart from each other in the direction R3 perpendicular to the base substrate 210 by the insulating layer 233, so that the short circuit phenomenon between the first conductive trace 221 and the second conductive trace 222 caused by, for example, material residue that may occur during preparation can be effectively reduced or avoided. Thus, the signal transmission range that can be detected by the detection trace structure including the first conductive trace 221 and the second conductive trace 222 in the opening peripheral area 2031 can be improved, which is conducive to realizing the effective detection of the signal transmission situation in the opening peripheral area 2031 by the detection trace structure. Furthermore, the accuracy and reliability of the detection results obtained by detecting the wiring structure can be improved, and it can be effectively determined whether the preparation process, such as the cutting process or other preparation processes, has an adverse effect on the line connection of the detection wiring structure. Based on the obtained detection results, it can be further determined whether other line connections or signal transmissions in the electronic substrate 20 are adversely affected during the preparation process, thereby improving the yield of the electronic substrate 20, reducing the preparation cost of the electronic substrate 20, and improving the reliability and stability of the electronic substrate 20, thereby optimizing the overall performance of the electronic substrate 20.

[0081] In some embodiments of the present disclosure, the first conductive trace 221 and the second conductive trace 222 include metal materials, for example, the first conductive trace 221 and the second conductive trace 222 may be single metal materials such as aluminum, molybdenum, copper, silver, or alloy materials of metal materials such as aluminum, molybdenum, copper, silver, for example, silver-palladium-copper alloy materials, etc. Therefore, in the embodiments of the present disclosure, by using the insulating layer 233 to space the first conductive trace 221 located in the first electrode layer 231 and the second conductive trace 222 located in the second electrode layer 232 in the direction R3 perpendicular to the base substrate 210, the short circuit phenomenon between the first conductive trace 221 and the second conductive trace 222 caused by the metal residue that may appear when the first conductive trace 221 and the second conductive trace 222 are formed can be weakened or avoided, thereby facilitating the effective and accurate detection of the signal transmission of the detection trace structure in the opening peripheral area 2031 through the first conductive trace 221 and the second conductive trace 222.

[0082] For example, the material of the insulating layer 233 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or may also include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0083] In some embodiments of the present disclosure, the detection wiring structure extends roughly along the edge contour of the side of the peripheral area 203 away from the first functional area 201, for example, it can extend roughly along the contour of the edge of one side of the peripheral area 203 formed by the cutting line. The detection wiring structure can be used to more accurately and effectively determine whether, for example, the cutting process or other preparation process of the electronic substrate 20 has an adverse effect on the line connection of the detection wiring structure, and based on the obtained detection results, it can be further determined whether other line connections or devices in the electronic substrate 20 are adversely affected during the preparation process.

[0084] For example, taking the first conductive trace 221 and the second conductive trace 222 located in the opening peripheral region 2031 as an example, the first conductive trace 221 and the second conductive trace 222 can extend roughly along the edge contour of the side of the opening peripheral region 2031 away from the first functional region 201, that is, roughly along the edge contour of the side of the opening peripheral region 2031 close to the second functional region 202, for example, roughly along the edge contour of the second functional region 202. As a result, the first conductive trace 221 and the second conductive trace 222 can be arranged closer to the position of the cutting line used to form the second functional region 202, thereby improving the accuracy of the signal transmission condition of the detection trace structure obtained through the first conductive trace 221 and the second conductive trace 222 in the opening peripheral region 2031, thereby improving the accuracy and reliability of the detection result obtained by using the detection trace structure.

[0085] For example, Figure 4A and Figure 5A As shown, the orthographic projection of the first conductive trace 221 on the base substrate 210 and the orthographic projection of the second conductive trace 222 on the base substrate 210 at least partially overlap each other at the second position P2, and the first conductive trace 221 and the second conductive trace 222 are electrically connected to each other at the second position P2 through a via structure H1 that at least penetrates the insulating layer 233.

[0086] It should be noted that the second position P2 may refer to a certain point or a certain area. Figure 4A Taking the illustrated embodiment as an example, the second position P2 may refer to a center point of a portion where the first conductive trace 221 and the second conductive trace 222 overlap each other in a direction R3 perpendicular to the base substrate 210 .

[0087] For example, at the second position P2, the first conductive trace 221 and the second conductive trace 222 overlap in the direction R3 perpendicular to the base substrate 210, which is conducive to setting the via structure H1 at the overlapping portion of the first conductive trace 221 and the second conductive trace 222 to achieve electrical connection between the first conductive trace 221 and the second conductive trace 222. Furthermore, the effective detection range of the detection trace structure in the opening peripheral area 2031 can be improved by the first conductive trace 221 and the second conductive trace 222 respectively located in different electrode layers, and the electrical connection mode between the first conductive trace 221 and the second conductive trace 222 can be optimized, and the trace layout design in the opening peripheral area 2031 can be optimized.

[0088] In some embodiments of the present disclosure, there is a gap between the second position P2 and the first position P1 along the circumferential direction of the edge of the second functional area 202. Figure 4A Taking the second functional area 202 having a substantially circular outline as shown in the figure as an example, the circumferential direction may refer to the direction along the circumference of the circle, for example, it may be in a clockwise direction or in a counterclockwise direction. Thus, the short circuit phenomenon caused by the material residue that may occur when forming the first conductive trace 221 and the second conductive trace 222 between the overlapping parts of the first conductive trace 221 and the second conductive trace 222 in the direction R3 perpendicular to the base substrate 210 and the part of the first conductive trace 221 or the second conductive trace 222 close to the first position P1 can be reduced or avoided.

[0089] For example, Figure 4A Taking the illustrated embodiment as an example, since the first conductive trace 221 and the second conductive trace 222 extend from the first position P1 to the second position P2 along the edge of the second functional area 202 respectively, and overlap each other at the second position P2 in the direction R3 perpendicular to the substrate 210, therefore, by keeping a distance between the second position P2 and the first position P1, a short circuit phenomenon caused by material residue that may occur when forming the first conductive trace 221 and the second conductive trace 222 can be reduced or avoided, thereby improving the accuracy and reliability of the signal transmission detection range of the detection trace structure including the first conductive trace 221 and the second conductive trace 222 in the opening peripheral area 2031, which is conducive to realizing the effective detection of the signal transmission situation in the opening peripheral area 2031 by the detection trace structure, thereby improving the accuracy and reliability of the detection result obtained by using the detection trace structure.

[0090] In some embodiments of the present disclosure, along the circumferential direction of the edge of the second functional area 202, the spacing between the first position P1 and the second position P2 is greater than or equal to 1 / 4 of the circumference of the edge of the second functional area 202, for example, it may be greater than or equal to 1 / 2 of the circumference of the edge of the second functional area 202. It should be noted that the above spacing refers to the minimum distance between the first position P1 and the second position P2 along the circumferential direction of the edge of the second functional area 202.

[0091] For example, in some embodiments of the present disclosure, Figure 4A As shown, the second functional area 202 can be an axisymmetric area, for example, an axisymmetric area with a roughly circular contour, and the first position P1 and the second position P2 are located on an axisymmetric line of the second functional area 202, so that in the circumferential direction along the edge of the second functional area 202, the distance between the first position P1 and the second position P2 is approximately equal to or greater than 1 / 2 of the circumference of the edge of the second functional area 202, for example, 1 / 2 of the circumference of the circle.

[0092] For example, for Figure 4A The second functional area 202 having a substantially circular outline as shown in FIG. 1 , the first position P1 and the second position P2 are located on or approximately on an extension line of a diameter of the circle. For example, the first position P1 and the second position P2 may be as shown in FIG. Figure 4A As shown in the figure, the first position P1 is located or approximately located on a straight line passing through the center of the circle and extending along the second direction R2, so that in the circumferential direction along the edge of the second functional area 202 (for example, in the circumferential direction of the circle), the first position P1 and the second position P2 can have a maximum spacing relative to each other, for example, in the circumferential direction along the edge of the second functional area 202, the spacing between the first position P1 and the second position P2 is greater than (for example, refer to Figure 4A as shown) or equal to (for example, refer to Fig.10 Thus, the short circuit phenomenon caused by the material residue that may occur when forming the first conductive trace 221 and the second conductive trace 222 can be further reduced or avoided between the overlapping portion of the first conductive trace 221 and the second conductive trace 222 in the direction R3 perpendicular to the substrate 210 and the portion of the first conductive trace 221 or the second conductive trace 222 close to the first position P1.

[0093] In some embodiments of the present disclosure, Figure 4AAs shown, the first conductive trace 221 and the second conductive trace 222 are symmetrically arranged relative to the axial symmetry line passing through the first position P1 and the second position P2, which is beneficial to optimize the preparation process of the first conductive trace 221 and the second conductive trace 222, and further improve the layout design of the first conductive trace 221 and the second conductive trace 222 in the opening peripheral area 2031.

[0094] In some embodiments of the present disclosure, 9A to 9C As shown, the first position P1 and the second position P2 may not be located on the axial symmetry line of the second functional area 202. For example, the first position P1 may be relatively approximately located at the "1 o'clock direction" of the circle, and the second position P2 may be relatively approximately located at the "5 o'clock direction" of the circle. For example, along the circumferential direction of the edge of the second functional area 202, the minimum spacing between the first position P1 and the second position P2 may also be approximately less than 1 / 2 of the circumference of the edge of the second functional area 202. For example, in this embodiment, the relative positions of the first position P1 and the second position P2 in the circumferential direction along the edge of the second functional area 202 may be appropriately adjusted according to other wirings or structures in the opening peripheral area 2031, so as to reduce or avoid the adverse effects of other wirings or structures in the opening peripheral area 2031 on, for example, the electrical connection between the first conductive wiring 221 and the second conductive wiring 222 at the second position P2. For example, the extension length of the first conductive trace 221 and the second conductive trace 222 in the circumferential direction of the edge of the second functional region 202 can be appropriately adjusted according to other traces or structures in the opening peripheral region 2031, and the embodiments of the present disclosure are not limited to this.

[0095] It needs to be explained that Fig. 9A for Figure 3 FIG. 1 is a partial enlarged schematic diagram of another example of the area AR21 shown in FIG. 1 , Fig. 9B for Fig. 9A A partial enlarged schematic diagram of the area AR31 shown in FIG. Fig. 9C for Fig. 9A For example, except that the relative positions of the first position P1 and the second position P2 in the direction along the edge of the second functional area 202 and the extension lengths of the first conductive trace 221 and the second conductive trace 222 in the circumferential direction of the edge of the second functional area 202 are different, 9A to 9C The other structures in the opening peripheral area 2031 shown in FIG. 2 are substantially the same as those in FIG. Figure 4A The same or similar parts as shown in the above will not be described in detail. 9A to 9C For details of other structures in the opening peripheral area 2031 shown in FIG. 2 , reference may be made to the corresponding descriptions in the following text.

[0096] Fig. 6AFor along Figure 4A A schematic diagram of a partial cross-sectional structure of the CC' line shown in FIG. Figure 6B for Fig. 6A A schematic diagram of an example of a multi-layer insulation structure including a first cofferdam structure and a second cofferdam structure shown in FIG. Figure 7 For along Figure 4A Schematic diagram of the partial cross-sectional structure of the FF' line shown in FIG.

[0097] In some embodiments of the present disclosure, Figure 4A and Fig. 6A As shown, the opening peripheral area 2031 includes a first cofferdam area 2041, a second cofferdam area 2042 and a spacing area 2043. The electronic substrate 20 includes a first cofferdam structure 241 and a second cofferdam structure 242. The first cofferdam structure 241 is located in the first cofferdam area 2041, and the second cofferdam structure 242 is located in the second cofferdam area 2042. The first cofferdam area 2041 at least partially surrounds the first functional area 201, for example Figure 4A As shown, the first functional area 201 can be completely surrounded, so that the first cofferdam structure 241 can effectively prevent, for example, water vapor or oxygen from penetrating into the first functional area 201, for example, the interior of the display device. The spacing area 2043 at least partially surrounds the first cofferdam area 2041, for example, completely surrounds the first cofferdam area 2041, and the second cofferdam area 2042 at least partially surrounds the spacing area 2043, for example, completely surrounds the spacing area 2043, so that the second cofferdam structure 242 can further effectively prevent, for example, water vapor or oxygen from penetrating into the display area 201, for example, the interior of the display device.

[0098] In some embodiments of the present disclosure, the first conductive trace 221 is at least located between the second cofferdam area 2042 and the second functional area 202, for example, at least a portion of the first conductive trace 221 is located between the second cofferdam area 2042 and the second functional area 202; the second conductive trace 222 is at least located between the second cofferdam area 2042 and the second functional area 202, for example, at least a portion of the second conductive trace 222 is located between the second cofferdam area 2042 and the second functional area 202. Thus, the first conductive trace 221 and the second conductive trace 222 can effectively and accurately detect signal transmission conditions in the opening peripheral area 2031, for example, near the cutting line used to form the second functional area 202, thereby improving the accuracy and reliability of the detection results obtained using the detection trace structure including the first conductive trace 221 and the second conductive trace 222.

[0099] For example, Fig. 6A and Figure 7As shown, in the direction R3 perpendicular to the base substrate 210, the first conductive trace 221 and the second conductive trace 222 are located on the side of the first cofferdam structure 241 and the second cofferdam structure 242 away from the base substrate 210, thereby avoiding the possible adverse effects of the first conductive trace 221 and the second conductive trace 222 on the first cofferdam structure 241 and the second cofferdam structure 242 on the penetration of, for example, water vapor or oxygen into the display area 201, for example, the interior of the display device, and the first conductive trace 221 and the second conductive trace 222 can be used to effectively and accurately determine whether, for example, the cutting process or other preparation processes have caused adverse effects on, for example, line connection or signal transmission in the opening peripheral area 2031.

[0100] For example, Fig. 6A As shown, the maximum height H2 of the second cofferdam structure 242 relative to the base substrate 210 is greater than the maximum height H1 of the first cofferdam structure 241 relative to the base substrate 210. Therefore, after packaging, the first cofferdam structure 241 and the second cofferdam structure 242 can more effectively block, for example, water vapor or oxygen from penetrating into, for example, the display area 101, and further avoid adverse effects on the various functional layers or structural layers in the electronic substrate 20.

[0101] For example, Figure 6B As shown, the first cofferdam structure 241 includes at least one insulating structure, for example, a multi-layer insulating structure 2411 stacked in layers. For example, the first cofferdam structure 241 may be as shown in FIG. Figure 6B As shown in the figure, it includes two layers of insulation structure 2411, or in some other examples, it can also include 3 layers, 4 layers or more layers of insulation structure; the second cofferdam structure 242 includes at least one layer of insulation structure, for example, including a multi-layer insulation structure 2421 stacked, for example, the second cofferdam structure 242 can be as follows Figure 6B As shown in the figure, it includes three layers of insulating structure 2421, or in some other examples, it may also include 2 layers, 4 layers, 5 layers or more layers of insulating structure. The embodiments of the present disclosure do not impose specific restrictions on the specific number of layers of insulating structure 2411 included in the first cofferdam structure 241 and the specific number of layers of insulating structure 2421 included in the second cofferdam structure 242. For example, it is sufficient that the maximum height H2 of the second cofferdam structure 242 relative to the base substrate 210 is greater than the maximum height H1 of the first cofferdam structure 241 relative to the base substrate 210.

[0102] Therefore, by adopting a multi-layer insulation structure to form the first cofferdam structure 241 and the second cofferdam structure 242 respectively, it is possible to more effectively prevent, for example, water vapor or oxygen from penetrating into the interior of, for example, the functional layers or structural layers of the display device in the display area 201, and to avoid adverse electrical effects on, for example, line connections or signal transmission in the electronic substrate 20.

[0103] For example, the material of the multilayer insulation structure 2411 and 2421 may include inorganic insulation materials such as silicon oxide, silicon nitride, silicon oxynitride, or may also include organic insulation materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin. The embodiments of the present disclosure do not specifically limit the materials of the multilayer insulation structure 2411 and 2421. For example, the materials of the insulation structures of each layer of the multilayer insulation structure 2411 and 2421 may be the same or partially the same as each other, or may be different from each other, and the embodiments of the present disclosure do not limit this.

[0104] In some embodiments of the present disclosure, a portion of the first conductive trace 221 located between the second cofferdam region 2042 and the second functional region 202 and a portion of the second conductive trace 222 located between the second cofferdam region 2042 and the second functional region 202 form an arc-shaped trace structure.

[0105] For example, Figure 4A As shown, the first conductive trace 221 and the second conductive trace 222 can form an arc-shaped trace structure including a protrusion, and the protrusion is located at least at the second position P2, and the second position P2 is located between the first cofferdam area 2041 and the first functional area 201. For example, the protrusion includes a portion between the first conductive trace 221 and the second conductive trace 222 that overlaps with each other in a direction R3 perpendicular to the base substrate 210 and is used to achieve electrical connection.

[0106] Thus, by making the overlapping portion between the first conductive trace 221 and the second conductive trace 222 in the direction R3 perpendicular to the base substrate 210 located on the side of the first cofferdam area 2041 close to the first functional area 201, that is, located on the side of the first cofferdam area 2041 away from the spacing area 2043 and the second cofferdam area 2042, the overlapping portion can be kept away from the "groove" portion formed by the first cofferdam structure 241 and the second cofferdam structure 242, so that the overlapping portion between the first conductive trace 221 and the second conductive trace 222 can be relatively flat, which is conducive to the formation of, for example, a via structure H1 or other electrical connection components for electrically connecting the first conductive trace 221 to the second conductive trace 222 in the overlapping portion.

[0107] For example, combined with Figure 7As shown, in order to reduce or avoid possible adverse effects on the devices or structures located in the first functional area 201, the thin film encapsulation layer 250, for example, covering the surface of the first functional area 201, is usually extended to the opening peripheral area 2031 during preparation. For example, the height L1 of the portion of the thin film encapsulation layer 250 located in the first functional area 201 relative to the base substrate 210 is basically maintained at about 7μm to 8μm, while the height of the portion of the thin film encapsulation layer 250 located in the opening peripheral area 2031 relative to the base substrate 210 gradually decreases with the distance away from the first functional area 201, for example Figure 7 As shown in the figure, the height L2 of the portion of the thin film encapsulation layer 250 located in the opening peripheral area 2031 and relatively closer to the first functional area 201 relative to the base substrate 210 is about 3μm to 5μm, and the height L3 of the portion of the thin film encapsulation layer 250 located in the opening peripheral area 2031 and relatively closer to the first cofferdam area 2041 relative to the base substrate 210 is about 0.1μm to 1μm, which easily leads to a large film layer discontinuity at a position close to the first cofferdam structure 241 in the opening peripheral area 2031. In an embodiment of the present disclosure, by setting the second position P2 away from the "groove" portion formed by the first cofferdam structure 241 and the second cofferdam structure 242, that is, setting the via structure for realizing the electrical connection between the first conductive trace 221 and the second conductive trace 222 away from the "groove" portion formed by the first cofferdam structure 241 and the second cofferdam structure 242, the overlapping portion between the first conductive trace 221 and the second conductive trace 222 can be made relatively flat, thereby improving the stability and reliability of the electrical connection between the first conductive trace 221 and the second conductive trace 222.

[0108] Moreover, in the case where the overlapping portion between the first conductive trace 221 and the second conductive trace 222 is located on the side of the first cofferdam area 2041 close to the first functional area 201, the size or area of ​​the overlapping portion between the first conductive trace 221 and the second conductive trace 222 in a plane parallel to the main surface of the base substrate 210 can also be appropriately increased, thereby further facilitating the electrical connection effect between the first conductive trace 221 and the second conductive trace 222.

[0109] For example, Fig.10As shown, the second position P2 may also be located between the second cofferdam area 2042 and the second functional area 202. For example, the overlapping portion between the first conductive trace 221 and the second conductive trace 222 in the direction R3 perpendicular to the base substrate 210 may be located between the second cofferdam area 2042 and the second functional area 202, and the first conductive trace 221 and the second conductive trace 222 form an arc-shaped trace structure that is approximately in the shape of a circular arc. Thus, the first conductive trace 221 and the second conductive trace 222 may be made closer to the position of the cutting line used to form the second functional area 202, thereby improving the accuracy and reliability of the detection results obtained by the first conductive trace 221 and the second conductive trace 222, and also reducing the trace layout of the first conductive trace 221 and the second conductive trace 222 in the opening peripheral area 2031, thereby optimizing the layout design in the opening peripheral area 2031. Furthermore, the overlapping portion between the first conductive trace 221 and the second conductive trace 222 in the direction R3 perpendicular to the base substrate 210 may further extend from between the second cofferdam area 2042 and the second functional area 202 to the side of the first cofferdam area 2041 away from the second cofferdam area 2042, so as to appropriately increase the size or area of ​​the overlapping portion between the first conductive trace 221 and the second conductive trace 222 in a plane parallel to the main surface of the base substrate 210, thereby further facilitating the electrical connection effect between the first conductive trace 221 and the second conductive trace 222.

[0110] It should be noted that the above embodiment of the present disclosure does not impose any specific restrictions on the electrical connection method between the first conductive trace 221 and the second conductive trace 222 at the second position P2. For example, for the portion where the first conductive trace 221 and the second conductive trace 222 overlap each other in the direction R3 perpendicular to the substrate 210, the following may be set: Figure 5A A via structure H1 as shown in the figure is used to realize the electrical connection between the first conductive trace 221 and the second conductive trace 222, thereby simplifying the preparation process and reducing the preparation cost; or, a plurality of via structures as shown in the figure can be provided at the overlapped portion between the first conductive trace 221 and the second conductive trace 222. Figure 5A The via structures H1 shown in the figure can improve the stability and reliability of the electrical connection between the first conductive trace 221 and the second conductive trace 222. For example, the plurality of via structures H1 can be arranged in one row or multiple rows, or can be arranged in other suitable ways.

[0111] It should be noted that, in some embodiments of the present disclosure, the first conductive trace 221 may also be formed in multiple electrode layers. For example, taking the case where the first conductive trace 221 is simultaneously formed in the first electrode layer 231 and the second electrode layer 232, for example, the first conductive trace 221 may be set to a double-layer trace structure extending around the edge of the second functional region 202, and the two-layer trace structures of the first conductive trace 221 respectively located in the first electrode layer 231 and the second electrode layer 232 may be electrically connected, for example, by a via structure that at least penetrates the insulating layer 233; for example, the portion of the first conductive trace 221 close to the first position P1 may adopt a single-layer trace structure, and the portion of the first conductive trace 221 away from the first position P1 may adopt a double-layer trace structure, so that the first conductive trace 221 and the second conductive trace 222 can be electrically connected through direct contact at the second position P2. For example, the second conductive trace 222 may also be formed in multiple electrode layers. For example, taking the example of the second conductive trace 222 being simultaneously formed in the first electrode layer 231 and the second electrode layer 232, the second conductive trace 222 can be configured as a double-layer trace structure extending around the edge of the second functional area 202, and the two-layer trace structures of the second conductive trace 222 respectively located in the first electrode layer 231 and the second electrode layer 232 can be electrically connected through a via structure penetrating the insulating layer; for example, the portion of the second conductive trace 222 close to the first position P1 can adopt a single-layer trace structure, and the portion of the second conductive trace 222 away from the first position P1 can adopt a double-layer trace structure, so that the first conductive trace 221 and the second conductive trace 222 can be electrically connected through direct contact at the second position P2.

[0112] It should be noted that, in the above-mentioned embodiment of the present disclosure, in order to clearly illustrate the arrangement of the first conductive trace 221 and the second conductive trace 222 in the opening peripheral area 2031, Figure 4A , Figure 4B and Fig.10 Other structures or devices that may be provided in the opening peripheral region 2031 are omitted, but this does not constitute a limitation on the structure or function of the opening peripheral region 2031 in the embodiments of the present disclosure. 9A to 9C Taking the specific example shown as an example, an example of the opening peripheral area 2031 is described, but it should be noted that the present disclosure includes but is not limited to this.

[0113] It should be noted that, in addition to the difference in relative positions of the first position P1 and the second position P2 along the edge of the second functional region 202 and the different extension lengths of the first conductive trace 221 and the second conductive trace 222 along the circumferential direction of the edge of the second functional region 202, 9A to 9C The other structures in the opening peripheral area 2031 shown in FIG. 2 are substantially the same as those in FIG. Figure 4A The same or similar parts as shown in , the repeated parts will not be repeated.

[0114] In some embodiments of the present disclosure, in the above Figures 3 to 7 The electronic substrate 20 shown is based on the combination of 9A to 9C As shown, the electronic substrate 20 further includes at least one first dummy electrode pattern 811 located in the opening peripheral region 2031, which may include, for example, Fig. 9A The electronic substrate 20 further includes at least one second dummy electrode pattern 812 located in the opening peripheral region 2031, for example, including: Fig. 9A The plurality of second dummy electrode patterns 812 shown in FIG. 8 are spaced apart from and insulated from each other.

[0115] The first dummy electrode pattern 811 and the second dummy electrode pattern 812 are located between the first functional area 201 and the first cofferdam area 2041; the first dummy electrode pattern 811 is located in the first electrode layer 231, and is spaced and insulated from the first conductive trace 221 and the second conductive trace 222 respectively; the second dummy electrode pattern 812 is located in the second electrode layer 232, and is spaced and insulated from the first conductive trace 221 and the second conductive trace 222 respectively. Thus, the first dummy electrode pattern 811 and the second dummy electrode pattern 812 can reduce or avoid mutual interference between the device or structure located in the first functional area 201 and the device or structure located in the opening peripheral area 2031 and the second functional area 202, thereby improving the stability and reliability of the electronic substrate 20.

[0116] It should be noted that, in some other embodiments of the present disclosure, the first dummy electrode pattern 811 may be located in the second electrode layer 232, and the second dummy electrode pattern 812 may be located in the first electrode layer 231; or, the first dummy electrode pattern 811 and the second dummy electrode pattern 812 may be located in the same first electrode layer 231 or the same second electrode layer 232; or, the first dummy electrode pattern 811 or the second dummy electrode pattern 812 may also adopt a double-layer electrode structure, for example, may include a portion located in the first electrode layer 231 and a portion located in the second electrode layer 232, and the two portions may be electrically connected, for example, by a via structure that at least penetrates the insulating layer 233, and the embodiments of the present disclosure are not limited to this.

[0117] For example, the first dummy electrode pattern 811 and the second dummy electrode pattern 812 may be spaced apart and insulated from each other, or the adjacent first dummy electrode pattern 811 and the second dummy electrode pattern 812 may be electrically connected to each other. For example, the first dummy electrode pattern 811 and the second dummy electrode pattern 812 may be in a floating or suspended state, or may be applied with the same or different electrical signals, which is not limited in the embodiments of the present disclosure.

[0118] For example, 9A to 9C As shown, among the plurality of first dummy electrode patterns 811, there is a spacing between adjacent first dummy electrode patterns 811, and the orthographic projections of the plurality of first dummy electrode patterns 811 on the base substrate 210 partially surround the first functional region 201. Alternatively, in some other embodiments of the present disclosure, only one first dummy electrode pattern 811 may be provided in the opening peripheral region 2031, and the orthographic projection of the first dummy electrode pattern 811 on the base substrate 210 completely surrounds the first functional region 201, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0119] For example, 9A to 9C As shown, among the plurality of second dummy electrode patterns 812, there is a spacing between adjacent second dummy electrode patterns 812, and the orthographic projections of the plurality of second dummy electrode patterns 812 on the base substrate 210 partially surround the first functional region 201. Alternatively, in some other embodiments of the present disclosure, only one second dummy electrode pattern 812 may be provided in the opening peripheral region 2031, and the orthographic projection of the second dummy electrode pattern 812 on the base substrate 210 completely surrounds the first functional region 201, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0120] For example, 9A to 9CAs shown, the orthographic projection of the first dummy electrode pattern 811 on the base substrate 210 is located on the side of the orthographic projection of the second dummy electrode pattern 812 on the base substrate 210 away from the first functional area 201, for example, the first dummy electrode pattern 811 is located in the "inner circle" closer to the second functional area 202, and the second dummy electrode pattern 812 is located in the "outer circle" closer to the first functional area 201. Alternatively, in some other embodiments of the present disclosure, the orthographic projection of the first dummy electrode pattern 811 on the base substrate 210 may also be located on the side of the orthographic projection of the second dummy electrode pattern 812 on the base substrate 210 close to the first functional area 201, for example, the second dummy electrode pattern 812 is located in the "inner circle" closer to the second functional area 202, and the first dummy electrode pattern 811 is located in the "outer circle" closer to the first functional area 201, and the embodiments of the present disclosure are not specifically limited to this. Alternatively, in some other embodiments of the present disclosure, the first dummy electrode pattern 811 and the second dummy electrode pattern 812 may be arranged in parallel along the same circle between the first functional area 201 and the second functional area 202 .

[0121] In some embodiments of the present disclosure, 9A to 9C As shown, the electronic substrate 20 further includes a connection wiring pattern 820. For example, the connection wiring pattern 820 is at least located in the opening peripheral area 2031 and partially surrounds the first functional area 201. For example, the connection wiring pattern 820 can be located in the opening peripheral area 2031 and the first functional area 201 at the same time. The first end 821 and the second end 821 of the connection wiring pattern 820 extend into the first functional area 201 respectively, so that the corresponding structures or devices (such as devices with display function or touch function) located on opposite sides of the second functional area 202 in the first functional area 201 can be electrically connected through the connection wiring pattern 820, thereby facilitating the improvement of the stability and reliability of signal transmission in the electronic substrate 20.

[0122] For example, refer to Fig. 9B As shown, in the case where the electronic substrate 20 includes a touch substrate, the connection wiring pattern 820 can be used to realize electrical connection between, for example, touch electrode structures 830 located in the first functional area 201 and located on the upper and lower sides of the second functional area 202, so that, for example, a touch signal for the first functional area 201 can be transmitted in the opening peripheral area 2031 through the connection wiring pattern 820 to enable the electronic substrate 20 to realize a touch function. For example, the touch electrode structure 830 may include, for example, Fig. 9B The multiple grids shown in FIG. 1 are used to form a grid-like electrode structure.

[0123] For example, in the opening peripheral area 2031, the orthographic projection of the connection wiring pattern 820 on the base substrate 210 is located between the orthographic projections of one or more first dummy electrode patterns 811 on the base substrate 210 and the orthographic projections of one or more second dummy electrode patterns 812 on the base substrate 210, that is, in a plane parallel to the base substrate 210, the connection wiring pattern 820 is located on the side of the first dummy electrode pattern 811 away from the second functional area 202, and is located on the side of the second dummy electrode pattern 812 away from the first functional area 201. The connection wiring pattern 820 and the first dummy electrode pattern 811 are spaced and insulated from each other, and the connection wiring pattern 820 and the second dummy electrode pattern 812 are spaced and insulated from each other. Thus, the first dummy electrode pattern 811 and the second dummy electrode pattern 812 can weaken or avoid possible interference between the signal transmitted on the connection wiring pattern 820 and other structures or devices in the first functional area 201 or the opening peripheral area 2031.

[0124] In some embodiments of the present disclosure, for example, Figures 9A to 9C As shown, the connection wiring pattern 820 is located in the first electrode layer 231. Alternatively, in some other embodiments of the present disclosure, the connection wiring pattern 820 may also be located in the second electrode layer 232; or, the connection wiring pattern 820 may also be located in the first electrode layer 231 and the second electrode layer 232 at the same time, for example, it may be alternately formed in the first electrode layer 231 and the second electrode layer 232 along the edge of the second functional area 202, and the embodiments of the present disclosure are not limited to this.

[0125] For example, Figures 9A to 9C As shown, in the circumferential direction along the edge of the second functional area 202, there is a spacing between the first end 821 of the connecting wiring pattern 820 and the first position P1 and the second position P2, respectively, and there is a spacing between the second end 822 of the connecting wiring pattern 820 and the first position P1 and the second position P2, respectively. That is, when the first conductive wiring 221 and the second conductive wiring 222 are arranged along the edge of the second functional area 202, both ends of the first conductive wiring 221 can be spaced from the first end 821 and the second end 822 of the connecting wiring pattern 820, respectively, and both ends of the second conductive wiring 222 can be spaced from the first end 821 and the second end 822 of the connecting wiring pattern 820, respectively. In this way, the adverse effects that may be generated between the signals transmitted on the connecting wiring pattern 820 and the signals on the first conductive wiring 221 and the second conductive wiring 222 can be reduced or avoided, and the stability of the electronic substrate 20 can be further improved.

[0126] For example, combined with Figure 4A , Figure 4B and Figure 5AAs shown, the detection wiring structure also includes a third conductive wiring 223 and a fourth conductive wiring 224 located in the opening peripheral area 2031. The third conductive wiring 223 is located in the first electrode layer 231, and is connected to the first conductive wiring 221 at one end of the first conductive wiring 221 close to the first position P1. For example, the third conductive wiring 223 can be integrally arranged with the first conductive wiring 221. The fourth conductive wiring 224 is located in the second electrode layer 232, and is connected to the second conductive wiring 222 at one end of the second conductive wiring 222 close to the first position P1. For example, the fourth conductive wiring 224 can be integrally arranged with the second conductive wiring 222. The third conductive wiring 223 and the fourth conductive wiring 224 extend approximately in a straight line from the first position P1 in a direction away from the center of the second functional area 202. For example, the third conductive trace 223 and the fourth conductive trace 224 extend from the side of the second cofferdam structure 242 close to the second functional area 202 to the side of the first cofferdam structure 241 close to the first functional area 201, that is, in a plane parallel to the base substrate 210, the third conductive trace 223 and the fourth conductive trace 224 span the "groove" portion formed by the first cofferdam structure 241 and the second cofferdam structure 242. Thus, by providing the third conductive trace 223 and the fourth conductive trace 224, it is possible to facilitate the connection between the first conductive trace 221 and the second conductive trace 222 and other traces in the detection trace structure, thereby simplifying the preparation process of the detection trace structure and reducing the preparation cost.

[0127] For example, the detection wiring structure further includes a first wiring portion 2201 and a second wiring portion 2202. The first wiring portion 2201 includes a first connection end and a second connection end, the first connection end of the first wiring portion 2201 serves as the first end or the second end of the detection wiring structure, and the second connection end of the first wiring portion 2201 is configured to be connected to the third conductive wiring 223. The second wiring portion 2202 includes a first connection end and a second connection end, the first connection end of the second wiring portion 2202 serves as the second end or the first end of the detection wiring structure, and the second connection end of the second wiring portion 2202 is configured to be connected to the fourth conductive wiring 224. The first wiring portion 2201, the third conductive wiring 223, the first conductive wiring 221, the second conductive wiring 222, the fourth conductive wiring 224, and the second wiring portion 2202 are sequentially connected to each other between the detection signal source 410 and the detection circuit 420. Therefore, by determining the signal transmission effect of the detection wiring structure between the detection signal source 410 and the detection circuit 420, the line connection status of the detection wiring structure in the peripheral area 203 (for example, the opening peripheral area 2031) can be accurately and effectively determined, and then based on the detection results of the detection wiring structure, it is judged or further detected whether other line connections or signal transmissions in the electronic substrate 20 during the preparation process are adversely affected by, for example, line disconnection or poor contact.

[0128] It should be noted that in some embodiments of the present disclosure, it can be as follows Figure 4B As shown, the first routing portion 2201 is connected to the detection circuit 420, and the second routing portion 2202 is connected to the detection signal source 410, for example, they are connected in sequence in the order of the detection circuit 420, the first routing portion 2201, the third conductive routing 223, the first conductive routing 221, the second conductive routing 222, the fourth conductive routing 224, the second routing portion 2202 and the detection signal source 410; or, in some other embodiments of the present disclosure, the second routing portion 2202 may be connected to the detection circuit 420, and the first routing portion 2201 may be connected to the detection signal source 410, for example, they are connected in sequence in the order of the detection signal source 410, the first routing portion 2201, the third conductive routing 223, the first conductive routing 221, the second conductive routing 222, the fourth conductive routing 224, the second routing portion 2202 and the detection circuit 420, and the embodiments of the present disclosure do not impose specific restrictions on this.

[0129] For example, the first routing portion 2201 includes a fifth conductive routing 225 at least partially located in the first functional region 201, for example, the fifth conductive routing 225 can be located in the first functional region 201 and the opening peripheral region 2031 to achieve electrical connection with the third conductive routing 223. The second routing portion 2202 includes a sixth conductive routing 226 at least partially located in the first functional region 201, for example, the sixth conductive routing 226 can be located in the first functional region 201 and the opening peripheral region 2031 to achieve electrical connection with the fourth conductive routing 224.

[0130] Figure 5B For along Figure 4A Schematic diagram of the partial cross-sectional structure of the DD' line shown in FIG. FIG. 4A to FIG. 5B As shown, the fifth conductive trace 225 and the sixth conductive trace 226 are located in the first electrode layer 231, the fifth conductive trace 225 is connected to the third conductive trace 223 and is integrally arranged, and the sixth conductive trace 226 and the fourth conductive trace 224 are electrically connected to each other through a via structure H2 that at least penetrates the insulating layer 233. Thus, while ensuring the connection between the first conductive trace 221 and the second conductive trace 222 and other traces in the detection trace structure, by making the fifth conductive trace 225 in the first trace portion 2201 and the sixth conductive trace 226 in the second trace portion 2202 both located in the same electrode layer, the preparation process of the detection trace structure in the electronic substrate 20 can be further simplified, and the preparation cost can be reduced.

[0131] For example, combined with FIG. 4A to FIG. 5BAs shown, the via structure H2 can be arranged on a side of the first cofferdam structure 241 and the second cofferdam structure 242 away from the second functional area 202, and the end of the sixth conductive trace 226 used for connecting with the fourth conductive trace 224 does not extend into the first cofferdam area 2041. For example, the distance between the via structure H2 and the first cofferdam structure 241 can be set relatively large, for example, the via structure H2 can be made closer to the display area 201, so that the via structure H2 and the sixth conductive trace 226 are relatively far away from the "groove" area formed by the first cofferdam structure 241 and the second cofferdam structure 242, thereby reducing or avoiding the short circuit phenomenon that may occur between the fifth conductive trace 225 and the sixth conductive trace 226 located in the same first electrode layer 231 due to factors such as material residue.

[0132] It should be noted that in some embodiments of the present disclosure, it can be as follows Figure 4B As shown, the fifth conductive trace 225 and the sixth conductive trace 226 are both located in the first electrode layer 231; or, in some other embodiments of the present disclosure, the fifth conductive trace 225 and the sixth conductive trace 226 are both located in the second electrode layer 232, and the embodiments of the present disclosure are not limited to this. Or, in some other embodiments of the present disclosure, the fifth conductive trace 225 and the sixth conductive trace 226 can also be located in different electrode layers according to actual needs.

[0133] In some embodiments of the present disclosure, the detection signal source 410 and the detection circuit 420 may be provided separately. For example, the detection signal source 410 and the detection circuit 420 may be arranged in the peripheral area 203 of the electronic substrate 20, such as the outer frame area of ​​the electronic substrate 20, so as to facilitate the connection with the detection wiring structure.

[0134] Fig.11 A schematic diagram of the connection between a detection wiring structure in an electronic substrate, a detection signal source, and a detection circuit provided in some embodiments of the present disclosure.

[0135] For example, in the case where the detection signal source 410 and the detection circuit 420 are provided separately, as shown in FIG. Fig.11 As shown, the detection signal source 410 and the detection circuit 420 can be arranged in the peripheral area 203 of the electronic substrate 20, thereby avoiding occupying the layout space in the functional areas (such as the first functional area 201 and the second functional area 202) of the electronic substrate 20, and reducing the adverse effects on the devices or structures arranged in the functional areas.

[0136] For example, the detection wiring structure can be arranged in the peripheral area 203 along the outer edge of the peripheral area 203, for example, Fig.11As shown in FIG. 1 , the first wiring portion 2201 and the second wiring portion 2202 in the detection wiring structure are respectively arranged along the outer edge of the electronic substrate 20, and are respectively connected to the detection circuit 420 and the detection signal source 410 located in the peripheral area 203. For example, the first wiring portion 2201 and the second wiring portion 2202 can be as follows Fig.11 As shown in , multiple turns of routing are arranged around the outer edge of the electronic substrate 20; or, in some other examples, the first routing portion 2201 and the second routing portion 2202 may also be arranged around only one turn of routing along the outer edge of the electronic substrate 20. For example, Fig.11 The multiple turns of wiring shown in the figure can be located in the same electrode layer, or can also be located in different electrode layers, so as to detect the signal transmission conditions in different electrode layers in the peripheral area 203 through the multiple turns of wiring. For example, the multiple turns of wiring located in different electrode layers can be connected by, for example, a via structure that at least penetrates the insulating layer.

[0137] In some embodiments of the present disclosure, for example, the detection circuit 420 can be connected to a device having a display function in the electronic substrate 20. When the signal provided by the detection signal source 410 can be normally transmitted to the detection circuit 420 through the detection wiring structure, the display device can be in a cut-off state under the control of the detection circuit 420 and does not emit light; when the signal provided by the detection signal source 410 cannot be normally transmitted to the detection circuit 420 through the detection wiring structure, the display device is in a suspended state or can be in a conducting state under the control of the detection circuit 420 and emit light, and then the signal transmission status on the detection wiring structure can be judged by the light-emitting state of the display device.

[0138] It should be noted that in some other embodiments of the present disclosure, according to different actual needs, such as according to the layout design requirements in the peripheral area of ​​the electronic substrate, the detection signal source and the detection circuit can also be set in, for example, the first functional area, and the embodiments of the present disclosure are not limited to this.

[0139] In some embodiments of the present disclosure, one or more functional devices or structures in the electronic substrate 20 may also be multiplexed to be used as a detection signal source 410 or a detection circuit 420 .

[0140] For example, in some embodiments of the present disclosure, Fig.12 As shown, the electronic substrate 20 includes a display substrate, and the first functional area 201 is configured as a display area. For example, the display substrate includes a plurality of pixel units 421 arranged in an array, each pixel unit 421 includes a driving circuit and a light-emitting element, and the driving circuit includes a first transistor. The first transistor is configured to be used as a detection circuit 420, and the second end of the detection wiring structure is configured to be electrically connected to the gate of the first transistor.

[0141] For example, the first transistor can be a driving transistor in the pixel unit 421 for driving the light-emitting element to emit light and controlling the magnitude of the driving current flowing through the light-emitting element, or can also be a light-emitting control transistor for controlling whether the driving current flows through the light-emitting element, or can also be a data writing transistor for controlling the writing of data signals. Thus, the light-emitting element can emit light or light of different brightness under the control of the first transistor, and then when the first transistor is used as the detection circuit 420, the electrical signal transmitted by the detection wiring structure is applied to the gate of the first transistor to control the working state of the first transistor (for example, control the conduction state of the first transistor), thereby realizing the detection of the signal transmission effect of the detection wiring structure through the light-emitting state of the light-emitting element electrically connected to the first transistor.

[0142] For example, the use of the first transistor as the detection circuit 420 to detect the signal transmission effect of the detection wiring structure can be performed in the non-luminous stage of the display substrate. For example, before the display substrate leaves the factory or before the display substrate is used to display a picture, the first transistor is used as the detection circuit 420 to detect the signal transmission condition on the detection wiring structure, so as to further determine whether, for example, the line connection or signal transmission in the display substrate is in a normal working state, thereby improving the stability and reliability of the display substrate.

[0143] The embodiments of the present disclosure do not specifically limit the type of the first transistor, for example, the first transistor can be an N-type transistor or a P-type transistor. For example, taking the detection signal source 410 as a signal source providing a low-level signal as an example, when the first transistor is an N-type driving transistor that drives the light-emitting element to emit light (for example, the light-emitting element emits light when the first transistor is in the on state), when the first transistor is used as the detection circuit 420, if the light-emitting element does not emit light, it means that the first transistor is in the off state, the low-level signal provided by the detection signal source 410 is applied to the gate of the first transistor, and no adverse phenomena such as line breakage occur in the detection wiring structure; if the light-emitting element emits light, it means that the first transistor is in the on state, the low-level signal provided by the detection signal source 410 is not applied to the gate of the first transistor, and adverse phenomena such as line breakage or poor contact may occur in the detection wiring structure. For example, taking the detection signal source 410 as a signal source that provides a high-level signal, when the first transistor is a P-type driving transistor that drives the light-emitting element to emit light (for example, the light-emitting element emits light when the first transistor is in the on state), when the first transistor is used as the detection circuit 420, if the light-emitting element does not emit light, it means that the first transistor is in the off state, and the high-level signal provided by the detection signal source 410 is applied to the gate of the first transistor, and no adverse phenomena such as line breakage occur in the detection wiring structure; if the light-emitting element emits light, it means that the first transistor is in the on state, and the high-level signal provided by the detection signal source 410 is not applied to the gate of the first transistor, and adverse phenomena such as line breakage or poor contact may occur in the detection wiring structure.

[0144] The embodiments of the present disclosure do not impose any specific restrictions on the type, material, structure, etc. of the first transistor, for example, it may be a top gate type, a bottom gate type, etc. For example, the active layer of the first transistor may be amorphous silicon, polycrystalline silicon (such as low temperature polycrystalline silicon, high temperature polycrystalline silicon), an oxide semiconductor (such as indium gallium tin oxide), etc. For example, the first transistor may be a thin film transistor, a field effect transistor, or other switching devices with the same characteristics.

[0145] It should be noted that the embodiments of the present disclosure do not limit the type and specific composition of the driving circuit. For example, the driving circuit can be a current-driven type or a voltage-driven type, and can be a 2T1C (i.e., two transistors and a capacitor, the two transistors include a driving transistor and a data writing transistor) driving circuit, or can be a driving circuit that further includes a compensation circuit (compensation transistor), a light-emitting control circuit (light-emitting control transistor), a reset circuit (reset transistor), etc. on the basis of 2T1C.

[0146] Fig.13This is a schematic diagram of an example of a partial cross-sectional structure of a first functional area of ​​an electronic substrate provided in some embodiments of the present disclosure. For example, the first functional area 201 can be configured as a display area. It should be noted that: Fig.13 The specific structures of the first transistor and the light-emitting element shown in the figure are only exemplary illustrations, and the embodiments of the present disclosure include but are not limited to them.

[0147] It should be noted that for the sake of clarity and brevity, Fig.13 Only the first transistor 501 located on the substrate 210 and the light-emitting element 502 electrically connected to the first transistor 501 are shown. For example, the first transistor 501 can be a driving transistor configured to operate in a saturated state and control the magnitude of the current driving the light-emitting element 502 to emit light. Alternatively, the first transistor 501 can also be a light-emitting control transistor for controlling whether the current driving the light-emitting element 502 to emit light flows. Alternatively, the first transistor 501 can also be a data writing transistor for controlling the writing of a data signal. The embodiments of the present disclosure do not limit the specific type of the first transistor 501.

[0148] like Fig.13 As shown, the first transistor 501 includes a gate 511 , a gate insulating layer 512 , an active layer 513 , a first electrode 514 and a second electrode 515 , and the second electrode 515 is electrically connected to the first light emitting electrode 521 of the light emitting element 502 .

[0149] For example, the gate 511 of the first transistor 501 can be located in the same electrode layer as the first conductive trace or the second conductive trace in the detection trace structure, for example, the gate 511 can be located in the same first electrode layer as the first conductive trace and formed by the same preparation process, or can be located in the same second electrode layer as the second conductive trace and formed by the same preparation process, thereby reducing the preparation cost of the electronic substrate and simplifying the preparation process. Alternatively, the first electrode 514 and the second electrode 515 of the first transistor 501 can be located in the same electrode layer as the first conductive trace or the second conductive trace in the detection trace structure, for example, the first electrode 514 and the second electrode 515 can be located in the same first electrode layer as the first conductive trace and formed by the same preparation process, or can be located in the same second electrode layer as the second conductive trace and formed by the same preparation process, thereby reducing the preparation cost of the electronic substrate and simplifying the preparation process.

[0150] In some other embodiments of the present disclosure, the first conductive trace and the second conductive trace in the detection trace structure may also be located in the same electrode layer as other structural layers or functional layers in the first functional area 201 (e.g., the display area 201), such as a display device, and formed using the same preparation process, and the embodiments of the present disclosure are not limited to this.

[0151] The first transistor 501 used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor, or may be a switching device with the same characteristics as other devices. The thin film transistor is used as an example for explanation in the embodiment of the present disclosure. The source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure. In the embodiment of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is directly described as the second pole.

[0152] For example, Fig.13 As shown, the light-emitting element 502 may be an organic light-emitting diode, and includes a first light-emitting electrode 521, a light-emitting layer 523, and a second light-emitting electrode 522. One of the first light-emitting electrode 521 and the second light-emitting electrode 522 is an anode, and the other is a cathode; for example, the first light-emitting electrode 521 is an anode, and the second light-emitting electrode 522 is a cathode. For example, the light-emitting layer 523 may be an organic light-emitting layer or a quantum dot light-emitting layer. For example, in addition to the light-emitting layer 523, the light-emitting element 502 may also include auxiliary functional layers such as a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer.

[0153] It should be noted that in Fig.13 In the illustrated embodiment, the light emitting element 502 is an organic light emitting diode, and the display substrate in the electronic substrate may be an organic light emitting diode display substrate. In some other embodiments of the present disclosure, the light emitting element may also be a quantum dot light emitting diode or other types of display devices, and accordingly, the display substrate in the electronic substrate may also be a quantum dot light emitting diode display substrate, a liquid crystal display substrate, an electronic paper display substrate or other types of substrates with display functions, which are not limited in the embodiments of the present disclosure.

[0154] In some embodiments of the present disclosure, the electronic substrate 20 includes a touch-control substrate, and the first functional area 201 is configured as a touch-control area. Fig.14A A schematic diagram of another example of a partial cross-sectional structure of a first functional region of an electronic substrate provided in some embodiments of the present disclosure, Fig. 14B A schematic diagram of another example of a partial cross-sectional structure of a first functional area of ​​an electronic substrate provided in some embodiments of the present disclosure, for example, the first functional area 201 may be configured as a touch area.

[0155] For example, the touch control substrate in the electronic substrate 20 includes a touch control electrode structure located on the base substrate 210, and the touch control electrode structure is at least partially located in the first functional area 201. The first portion 601 of the touch control electrode structure is located in the first electrode layer 231, and the second portion 602 of the touch control electrode structure is located in the second electrode layer 232, so that the first portion 601 of the touch control electrode structure can be formed in the same layer as the first conductive trace in the detection trace structure, and the second portion 602 of the touch control electrode structure can be formed in the same layer as the second conductive trace in the detection trace structure, thereby reducing the preparation cost of the electronic substrate 20 and simplifying the preparation process.

[0156] For example, the touch electrode structure can be directly formed on, for example Figure 7 The thin film encapsulation layer 250 shown in the figure is arranged on the thin film encapsulation layer 250 so that the touch electrode structure is relatively closer to the side where the user performs the touch operation, thereby improving the accuracy and stability of the touch function.

[0157] For example, in Fig.14A In the illustrated embodiment, the first portion 601 of the touch electrode structure may include a plurality of first electrode blocks 610 and a plurality of second electrode blocks 620, and the second portion 602 of the touch electrode structure may include a plurality of third electrode blocks 630. For example, the first electrode blocks 610 and the second electrode blocks 620 are spaced apart from each other and insulated in the first electrode layer 231, and the first electrode blocks 610 are spaced apart from and insulated from the third electrode blocks 630 located in the second electrode layer 232 through the insulating layer 233. For example, the plurality of first electrode blocks 610 located in the first electrode layer 231 are electrically connected to each other, and the second electrode blocks 620 located in the first electrode layer 231 are electrically connected to the third electrode blocks 630 located in the second electrode layer 232 through the via structure that at least penetrates the insulating layer 233, thereby making the plurality of second electrode blocks 620 located in the first electrode layer 231 electrically connected to each other through the third electrode blocks 630.

[0158] For example, the first electrode block 610 can be used as a touch sensing electrode, and the second electrode block 620 and the third electrode block 630 can be used as touch driving electrodes; or, the first electrode block 610 can be used as a touch driving electrode, and the second electrode block 620 and the third electrode block 630 can be used as touch sensing electrodes, which is not limited in the embodiments of the present disclosure.

[0159] For example, in Fig. 14BIn the illustrated embodiment, the first portion 601 of the touch electrode structure may include a plurality of first electrode blocks 610, and the second portion 602 of the touch electrode structure may include a plurality of second electrode blocks 620 and a plurality of third electrode blocks 630. For example, the second electrode blocks 620 and the third electrode blocks 630 are spaced apart from each other and insulated in the second electrode layer 232, and the first electrode blocks 610 are spaced apart from and insulated from the third electrode blocks 630 in the second electrode layer 232 through the insulating layer 233. For example, the plurality of third electrode blocks 630 in the second electrode layer 232 are electrically connected to each other, and the second electrode blocks 620 in the second electrode layer 232 are electrically connected to the first electrode blocks 610 in the first electrode layer 231 through the via structure that at least penetrates the insulating layer 233, thereby making the plurality of second electrode blocks 620 in the second electrode layer 232 electrically connected to each other through the first electrode blocks 610.

[0160] For example, the first electrode block 610 and the second electrode block 620 can be used as touch sensing electrodes, and the third electrode block 630 can be used as a touch driving electrode; or, the first electrode block 610 and the second electrode block 620 can be used as touch driving electrodes, and the third electrode block 630 can be used as a touch sensing electrode, which is not limited in the embodiments of the present disclosure.

[0161] In some other embodiments of the present disclosure, the first part and the second part of the touch electrode structure can also be separated and insulated from each other in the direction R3 perpendicular to the base substrate 210 by an insulating layer 233 located between the first electrode layer 231 and the second electrode layer 232, so as to be used as a touch sensing electrode and a touch driving electrode respectively. The embodiments of the present disclosure do not limit the specific setting method of the touch electrode structure.

[0162] In some embodiments of the present disclosure, the electronic substrate 20 may also include a display substrate and a touch substrate at the same time. For example, the first functional area 201 of the electrode substrate 20 may be configured as a display area and a touch area at the same time. For example, the electronic substrate 20 may be an On-cell or In-cell touch display substrate. The embodiments of the present disclosure do not specifically limit the specific type, function, etc. of the electronic substrate 20.

[0163] At least one embodiment of the present disclosure further provides an electronic device, which includes the electronic substrate described in any embodiment of the present disclosure, such as the electronic substrate 20 or the electronic substrate 30 in the above embodiments, and the electronic substrate can be configured as a display substrate or a touch substrate.

[0164] Fig.15 A schematic block diagram of an electronic device provided for some embodiments of the present disclosure.

[0165] For example, Fig.15As shown, the electronic device 70 includes an electronic substrate 701. For example, the electronic substrate 701 may be an electronic substrate provided by any embodiment of the present disclosure, such as the electronic substrate 20 or the electronic substrate 30 in the above-mentioned embodiment.

[0166] For example, the electronic substrate 701 can be configured as a display substrate. For example, the electronic substrate 701 can be a liquid crystal display (LCD) substrate, an organic light emitting diode (OLED) display substrate, a quantum dot light emitting diode (QLED) display substrate, an electronic paper display substrate, etc., or it can be other substrates with display functions, and the embodiments of the present disclosure are not limited to this.

[0167] For example, the electronic substrate 701 may also be configured as a touch substrate. For example, the electronic substrate 701 may be used as an On-cell touch substrate or an In-cell touch substrate, or may be other substrates with touch functions, which is not limited in the embodiments of the present disclosure.

[0168] For example, the electronic substrate 701 may also be configured as a display substrate and a touch substrate at the same time. For example, the electronic substrate 701 may be a touch display substrate having both display and touch functions. Alternatively, in addition to the display and touch functions, the electronic substrate 701 may also have other required functions according to different actual needs, and the embodiments of the present disclosure do not limit this.

[0169] The structure, function, technical effect, etc. of the electronic device provided by the above embodiments of the present disclosure may refer to the corresponding contents in the electronic substrate provided by the above embodiments of the present disclosure, and will not be repeated here.

[0170] For example, the electronic device provided in the embodiments of the present disclosure may be a display substrate, a display panel, a touch substrate, a touch panel, a touch display substrate, a touch display panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function and / or a touch function, and the embodiments of the present disclosure are not limited to this.

[0171] There are a few points to note:

[0172] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0173] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0174] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0175] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. An electronic substrate, comprising a first functional area, a second functional area and a peripheral area surrounding the first functional area; in, The first functional area includes an opening, and the second functional area is located in the opening, The peripheral region includes an opening peripheral region at least partially located in the opening, the opening peripheral region at least partially surrounding the second functional region and located between the second functional region and the first functional region; The electronic substrate comprises a base substrate and a detection wiring structure located on the base substrate. The detection wiring structure is arranged along the edge of the peripheral area, the first end of the detection wiring structure is configured to be connected to a detection signal source, and the second end of the detection wiring structure is configured to be connected to a detection circuit; The detection wiring structure includes a first conductive wiring and a second conductive wiring located in the peripheral area of ​​the opening and at least partially surrounding the second functional area. The first conductive trace and the second conductive trace respectively extend from the first position in reverse direction along the edge of the second functional area and respectively partially surround the second functional area, and the first conductive trace and the second conductive trace are spaced apart from each other at the first position. The contours of the orthographic projections of the first conductive trace and the second conductive trace on the substrate at least partially surround the orthographic projection of the second functional area on the substrate, so that the orthographic projection of the second functional area on the substrate is located within the area enclosed by the orthographic projections of the first conductive trace and the second conductive trace on the substrate; The electronic substrate comprises a first electrode layer, an insulating layer and a second electrode layer which are sequentially stacked on the base substrate. The first conductive trace is located in the first electrode layer, the second conductive trace is located in the second electrode layer, the first conductive trace and the second conductive trace are spaced apart from each other in a direction perpendicular to the substrate through the insulating layer and are electrically connected to each other at a second position.

2. The electronic substrate according to claim 1, wherein: The orthographic projection of the first conductive trace on the substrate and the orthographic projection of the second conductive trace on the substrate at least partially overlap each other at the second position, The first conductive trace and the second conductive trace are electrically connected to each other at the second position through a via structure that at least penetrates the insulating layer.

3. The electronic substrate according to claim 1 or 2, wherein: In the circumferential direction along the edge of the second functional area, there is a distance between the second position and the first position.

4. The electronic substrate according to claim 3, wherein: In the circumferential direction along the edge of the second functional area, the distance between the first position and the second position is greater than or equal to 1 / 4 of the circumference of the edge of the second functional area.

5. The electronic substrate according to claim 1 or 2, wherein: The opening peripheral area includes a first cofferdam area, a second cofferdam area and a spacing area, The first cofferdam area at least partially surrounds the first functional area, the spacing area at least partially surrounds the first cofferdam area, and the second cofferdam area at least partially surrounds the spacing area. The electronic substrate comprises a first cofferdam structure and a second cofferdam structure, wherein the first cofferdam structure is located in the first cofferdam region, and the second cofferdam structure is located in the second cofferdam region. The first conductive trace is at least located between the second cofferdam area and the second functional area, and the second conductive trace is at least located between the second cofferdam area and the second functional area. In a direction perpendicular to the substrate, the first conductive trace and the second conductive trace are located on a side of the first cofferdam structure and the second cofferdam structure away from the substrate.

6. The electronic substrate according to claim 5, further comprising at least one first dummy electrode pattern and at least one second dummy electrode pattern located in the peripheral area of ​​the opening, in, The at least one first dummy electrode pattern and the at least one second dummy electrode pattern are located between the first functional area and the first cofferdam area, The at least one first dummy electrode pattern is located in the first electrode layer, and is spaced apart from and insulated from the first conductive trace and the second conductive trace, respectively. The at least one second dummy electrode pattern is located in the second electrode layer, and is spaced apart from and insulated from the first conductive trace and the second conductive trace, respectively.

7. The electronic substrate according to claim 6, wherein: The orthographic projection of the at least one first dummy electrode pattern on the base substrate at least partially surrounds the first functional area, and the orthographic projection of the at least one second dummy electrode pattern on the base substrate at least partially surrounds the first functional area, The orthographic projection of the at least one first dummy electrode pattern on the base substrate is located on a side of the orthographic projection of the at least one second dummy electrode pattern on the base substrate that is away from the first functional region.

8. The electronic substrate according to claim 6, further comprising a connection wiring pattern, in, The connection wiring pattern is at least located in the peripheral area of ​​the opening and partially surrounds the first functional area, and the first end and the second end of the connection wiring pattern extend into the first functional area respectively; In the opening peripheral region, the orthographic projection of at least part of the connection wiring pattern on the base substrate is located on a side of the orthographic projection of the at least one first dummy electrode pattern on the base substrate away from the second functional region, The connection wiring pattern and the at least one first dummy electrode pattern are spaced apart and insulated from each other, and the connection wiring pattern partially overlaps and is insulated from the at least one second dummy electrode pattern in a direction perpendicular to the base substrate.

9. The electronic substrate according to claim 8, wherein: The connection wiring pattern is located in the first electrode layer or the second electrode layer.

10. The electronic substrate according to claim 8, wherein: In the circumferential direction along the edge of the second functional area, a first end of the connection wiring pattern is spaced from the first position and the second position, and a second end of the connection wiring pattern is spaced from the first position and the second position.

11. The electronic substrate according to claim 5, wherein: The first cofferdam structure includes at least one layer of insulating structure, and the second cofferdam structure includes at least one layer of insulating structure.

12. The electronic substrate according to claim 5, wherein: The first conductive trace and the second conductive trace form an arc-shaped trace structure including a protruding portion, The protrusion is located at least at the second position.

13. The electronic substrate according to claim 12, wherein: The second position is at least located between the first cofferdam area and the first functional area.

14. The electronic substrate according to claim 5, wherein: The first conductive trace and the second conductive trace form an arc-shaped trace structure, The second position is located at least between the second cofferdam area and the second functional area.

15. The electronic substrate according to claim 1 or 2, wherein: The detection wiring structure further includes a third conductive wiring and a fourth conductive wiring located in the peripheral area of ​​the opening, The third conductive trace is located in the first electrode layer and is connected to the first conductive trace at an end of the first conductive trace close to the first position. The fourth conductive trace is located in the second electrode layer and is connected to the second conductive trace at an end of the second conductive trace close to the first position, The third conductive trace and the fourth conductive trace respectively extend substantially in a straight line from the first position in a direction away from the center of the second functional area.

16. The electronic substrate according to claim 15, wherein: The detection wiring structure also includes a first wiring portion and a second wiring portion. The first wiring portion includes a first connection end and a second connection end, the first connection end of the first wiring portion serves as the first end or the second end of the detection wiring structure, and the second connection end of the first wiring portion is configured to be connected to the third conductive wiring. The second wiring portion includes a first connection end and a second connection end, the first connection end of the second wiring portion serves as the second end or the first end of the detection wiring structure, and the second connection end of the second wiring portion is configured to be connected to the fourth conductive wiring. The first trace portion, the third conductive trace, the first conductive trace, the second conductive trace, the fourth conductive trace, and the second trace portion are sequentially connected to one another between the detection signal source and the detection circuit.

17. The electronic substrate according to claim 16, wherein: The first routing portion includes a fifth conductive routing at least partially located in the first functional area, the second routing portion includes a sixth conductive routing at least partially located in the first functional area, The fifth conductive trace and the sixth conductive trace are located in the first electrode layer, The fifth conductive trace is connected to the third conductive trace and is integrally arranged, and the sixth conductive trace and the fourth conductive trace are electrically connected to each other via a via structure that at least penetrates the insulating layer.

18. The electronic substrate according to claim 1 or 2, wherein: The detection wiring structure substantially extends along an edge contour of the peripheral area on a side away from the first functional area.

19. The electronic substrate according to claim 1 or 2, wherein: The electronic substrate includes a touch substrate, the first functional area is configured as a touch area, The touch control substrate comprises a touch control electrode structure located on the base substrate, wherein the touch control electrode structure is at least partially located in the first functional area. The first portion of the touch electrode structure is located in the first electrode layer, and the second portion of the touch electrode structure is located in the second electrode layer.

20. An electronic device comprising the electronic substrate according to claim 1, wherein: The electronic substrate is configured as a display substrate or a touch control substrate.

Images