Current monitoring circuit, corresponding system and method

Abstract

Embodiments of the present disclosure relate to current monitoring circuits, corresponding systems and methods. In embodiments, an electronic circuit includes a controller configured to generate a pulse width modulated (PWM) signal to control a first current of an electrical load, a redundant current measurement circuit configured to measure the first current and provide a first current measurement signal and a second current measurement signal, a monitoring circuit coupled to the redundant current measurement circuit, the monitoring circuit configured to assert a current monitoring signal in response to finding that the first current measurement signal and the second current measurement signal agree with each other, wherein the monitoring circuit is configured to detect a lack of assertion of the current monitoring signal before expiration of a threshold time interval and, in response to detecting the lack of assertion of the current monitoring signal, force the controller to generate a first PWM signal pulse having a controlled duty cycle before expiration of the threshold time interval.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Italian patent application No. 102020000032042, filed on December 23, 2020, which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to electronic systems and methods, and in particular embodiments to current monitoring circuits, corresponding systems and methods. BACKGROUND

[0004] Specifications for functional safety of road vehicles, such as ISO 26262, define a risk classification scheme, referred to as ASIL (Automotive Safety Integrity Level), which helps define safety specifications compliant with ISO 26262. The ASIL scheme is built by performing a risk analysis of potential hazards by looking at the severity, exposure and controllability of the operating scenarios of the vehicle.

[0005] There are currently four ASIL categories: ASIL A, ASIL B, ASIL C, ASIL D, where ASIL D prescribes the highest integrity specification and ASIL A prescribes the lowest integrity specification.

[0006] Quite stringent specifications like ASIL-D apply to devices used in the automotive industry, for example high-side / low-side (HS-LS) drivers for driving electrical loads, for example solenoid loads (e.g. electromagnetic valves) with current regulated by means of pulse width modulation (PWM).

[0007] In these drivers, compliance with the specifications can be facilitated by providing a redundant current measurement path and a monitor configured to check the main current measurement path against the redundant current measurement path.

[0008] Redundancy can be applied in different ways (e.g. HS-LS comparison). Regardless of the implementation of the redundant current monitor, a limitation can arise when the PWM modulation reaches a “corner DC” condition, i.e. in the presence of a duty cycle close to 0% or close to 100%.

[0009] In some embodiments, a duty cycle of 5% or less is considered close to 0%. In some embodiments, a duty cycle of 95% or more is considered close to 100%.

[0010] As known, the “duty cycle” represents the ratio TON / (TON+TOFF) of the time TON in which the PWM signal is on or active, to the period of the PWM signal, which is the sum of the time TON and the time TOFF in which the PWM signal is off or inactive.

[0011] These "corner" conditions impede providing reliable redundant current measurements, e.g. within a time interval FTTI (Fault Tolerant Time Interval) of about 20 ms, when the current measurement path becomes unable to provide the desired sufficient measurement. SUMMARY

[0012] The present specification relates to techniques for monitoring current.

[0013] One or more embodiments can apply to on- and off-state diagnosis of redundant current monitors.

[0014] Some embodiments advantageously solve the previously outlined problems.

[0015] Some embodiments advantageously solve the previously outlined problems by using a circuit according to the present invention.

[0016] One or more embodiments can relate to corresponding systems. Valve drive systems for the automotive industry can be an example of such systems.

[0017] One or more embodiments can relate to corresponding methods.

[0018] One or more embodiments can include a valve driver block that can be activated (e.g. for testing purposes) even if the associated power stage is in off-state: a test pulse for off-state diagnosis is visible and reliable redundant current monitoring measurements, e.g. on SPI registers, are available.

[0019] For the sake of clarity and ease of explanation, a possible application of the embodiments in the field of valve drives for the automotive industry is discussed herein. The skilled person will understand in other ways that the embodiments are not limited to this exemplary application.

[0020] In an embodiment, a circuit, e.g., for driving a solenoid load in a motor vehicle, includes a controller configured to generate a pulse width modulated (PWM) signal to control a supply of current to an electrical load. A redundant current measurement circuit arrangement includes a first current sense path and a second current sense path to measure current in the electrical load and provide a first current measurement signal and a second current measurement signal. Responsive to finding that the first and second current measurement signals are adapted, a monitoring circuit arrangement coupled to the current measurement circuit arrangement asserts a current monitoring signal. The monitoring circuit arrangement is configured to detect a lack of assertion of the current monitoring signal before expiration of a threshold time interval and to force the controller to generate at least one PWM pulse having a controlled non-0% duty cycle before expiration of the threshold time interval. This can be a pulse having a duty cycle different from the duty cycle of the currently generated PWM signal (on state operation) or a pulse forced when the circuit is not currently generating a PWM signal (off state operation). BRIEF DESCRIPTION OF DRAWINGS

[0021] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings:

[0022] Figure 1 is a block diagram illustrating an implementation of independent HS / LS current measurement paths in a valve driver,

[0023] Figure 2 and Figure 3 is an exemplary diagram of possible time behavior of signals that can occur in embodiments discussed herein, and

[0024] Figure 4 is an exemplary block diagram in a transmission control unit that can incorporate embodiments. DETAILED DESCRIPTION

[0025] In the following description, one or more specific details are illustrated, in order to provide an example implementation of embodiments. One or more other examples can well not illustrate these specific details, or can illustrate different specific details. In other instances, well-known structures, materials, or operations have not been described in detail in order to avoid obscuring the understanding of the embodiments.

[0026] Reference within this specification to "an embodiment" or "one embodiment" means that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in an embodiment" or "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment.

[0027] Furthermore, in one or more embodiments, particular configurations, structures, or characteristics can be combined in any suitable manner.

[0028] The headings / labels provided herein are for convenience only and therefore do not interpret the extent of protection afforded by the embodiments.

[0029] A transmission control unit implemented as an integrated circuit (IC) for use in the automotive industry comprises as important circuit blocks valve drivers. These blocks can be used for regulating circuitry to drive solenoid loads with controlled current using current sensing and in PWM operation.

[0030] High safety level (e.g. ASIL-D compliant) and high precision of regulating current (up to + / - 0.25%) are desirable features which can involve implementation of a redundant current monitor able to reveal presence of possible errors in the main current sensing and regulating path.

[0031] Figure 1 An exemplary block diagram of an arrangement which can be used for regulating circuitry to drive solenoid loads (e.g. solenoid valves SV in a motor vehicle V) with controlled current using current sensing and in PWM operation is shown.

[0032] Generally, such control schemes are conventional in the art. This makes it unnecessary to provide a detailed description in the context of the present disclosure which mainly relates to redundant current monitoring in such control schemes, unless the context indicates otherwise.

[0033] The arrangement as exemplified in Figure 1 comprises current sensors S1, S2 for the high side (HS) and low side (LS), respectively. The sensors S1 and S2 cooperate with (high resolution) analog-to-digital converters (or abbreviated ADC, ADC HS and ADC LS) which convert the sensed voltages provided by the sensors S1 and S2 into digital codes.

[0034] In the present measurement of the valve driver block, independence between the LS and HS paths is desirable.

[0035] To this end, two (fully) independent signal paths are provided in the measurement chain as shown in Figure 1 comprising the two sensors S1, S2.

[0036] The independent HS and LS paths as shown in Figure 1 facilitate implementation of independence (HS and LS are suitable for comparison with each other) in compliance with ASIL-D specifications and redundant current monitoring.

[0037] For example, as shown in Figure 1As shown, the (single) digital channel coupled to the analog channel includes two sensors S1 and S2 and two ADCs, namely ADC HS and ADC LS. This (single) digital channel includes:

[0038] -ADC logic circuitry devices 10H (high) and 10L (low),

[0039] - Filter circuit devices 12H and 12L, and

[0040] - Calibration circuit devices 14H and 14L are expected to work in turn with (external) calibration sources 16H and 16L.

[0041] like Figure 1 The arrangement shown also includes a multiplexer 18 driven by a switching (pulse width modulation) signal PWM to alternately supply the outputs from the previously discussed high-side and low-side branches (essentially the outputs from calibration circuits 14H and 14L) to a current setpoint CS-sensitive controller 20 (e.g., a proportional-integral or PI controller), and is configured to generate the pulse width modulation signal PWM based on the signal supplied via the multiplexer 18.

[0042] The (average) value of the output from multiplexer 18 (represented in a general manner by box 22) indicates the average value of the entities sensed by sensors S1 and S2, i.e., in the exemplary case considered here, the average current supplied to the load (here, SV) by the high-side branch and low-side branch discussed earlier.

[0043] As shown in the figure, the PWM monitoring circuit 24 receives the PWM feedback signal from the input analog channel in order to verify that this PWM signal at the output of the valve driver is consistent with, for example, equal to (with a certain error tolerance) the value forced by the controller block 20 (e.g., PI controller).

[0044] This signal can be provided by an analog comparator that compares its output voltage to the voltage of the power source (battery). This can be done, for example, using a threshold value that is half the battery value.

[0045] This additional safety feature helps to comply with the ASIL-D specification according to ISO 26262.

[0046] The device can be configured to provide (e.g., on an SPI register) the duty cycle measured by box 24, and the system-level microcontroller can compare the measured value with a theoretical value set by box 20 (which can also be read from the SPI register). If the difference exceeds a certain threshold, the microcontroller can put the system into a "safe" state.

[0047] As shown, the comparator circuit arrangement 26 can be coupled to the outputs from the previously discussed high-side branch and low-side branch (basically the outputs from the calibration circuit arrangements 14H and 14L), with the ability to compare the two outputs (and thus the values S1 and S2 sensed by the sensor).

[0048] The information provided by block 24 can be used by block 26 (high-side, low-side comparison) for enhanced diagnostic purposes, as discussed below, i.e. in order to facilitate compliance with specifications by relying on a redundant current measurement path and a monitor configured to check the primary current measurement path against the redundant current measurement path.

[0049] Relying on Figure 1 The driver of the illustrated architecture can be for example incorporated in a transmission control unit for passenger vehicles (PV) and commercial vehicles (CV). The valve driver stage implemented in a transmission and brake control unit is an example of such possible application.

[0050] Further, it is again noted that the reference to such possible applications is merely exemplary and not a limitation of the embodiments. One or more embodiments can actually be applied in general to circuits for which a high level of safety is desired (e.g. up to ASIL-D), which can lead to redundancy of each function.

[0051] Figure 1 The illustrated solution is an example of implementation of the HS-LS comparison that facilitates compliance with specifications in a way that increases flexibility and significant savings in manufacturing costs.

[0052] It is noted that the mixed analog / digital implementation of the HS-LS comparison as detailed herein is merely an example of one possible way of applying a redundant current measurement path: for example, certain traditional solutions involve replicating the entire LS and HS path. In any case, as Figure 1 The illustrated solution shares certain limitations with more conventional solutions, which can arise in the case of “corner” situations involving PWM duty cycles close to 0% or 100%.

[0053] To summarize:

[0054] - In general, a certain safety level specification (e.g. ASIL-D) for valve drivers for sensing and regulating the current in an electrical load operated by PWM (e.g. solenoid loads for transmission applications in the automotive industry) can involve the use of a redundant current measurement path;

[0055] - As Figure 1The HS-LS comparison monitor exemplified in the middle, based on a hybrid analog / digital implementation and involving a traditional solution that replicates the entire LS and HS paths, can exhibit limitations in measuring current sufficiently when the PWM duty cycle approaches the "corner" condition.

[0056] For example:

[0057] - in the presence of PWM duty cycle values close to 0% (e.g. 5% or less), the active stage can not be able to measure current, and

[0058] - in the presence of PWM duty cycle values close to 100% (e.g. 95% or more), the recirculation stage can not be able to measure current.

[0059] The names "active stage" and "recirculation stage" apply differently depending on the configuration adopted by the application.

[0060] For example, in a low-side (LS) configuration:

[0061] - the active stage can comprise a low-side circuit arrangement comprising the associated measurement path, i.e. sensor S2, converter ADS LS, logic circuit arrangement 10L, filter circuit arrangement 12L and calibration circuit arrangement 14L expected to cooperate with calibration source 16L;

[0062] and

[0063] - the recirculation stage can comprise a high-side circuit arrangement comprising the associated measurement path, i.e. sensor S1, converter ADC HS, logic circuit arrangement 10H, filter circuit arrangement 12H and calibration circuit arrangement 14H expected to cooperate with calibration source 16H.

[0064] In a complementary way, in a high-side (HS) configuration:

[0065] - the active stage can comprise a high-side circuit arrangement comprising the associated measurement path, i.e. sensor S1, converter ADC HS, logic circuit arrangement 10H, filter circuit arrangement 12H and calibration circuit arrangement 14H expected to cooperate with calibration source 16H; and

[0066] - the recirculation stage can comprise a low-side circuit arrangement comprising the associated measurement path, i.e. sensor S2, converter ADS LS, logic circuit arrangement 10L, filter circuit arrangement 12L and calibration circuit arrangement 14L expected to cooperate with calibration source 16L.

[0067] As discussed, proper operation of the arrangement considered in this paper can benefit from reliable redundant current measurements, which helps to achieve the desired FTTI (Fault Tolerance Time Interval) performance, for example, equal to 20 ms.

[0068] By reference to, such as Figure 1 The PWM signal generated by the controller 20 (e.g., this could be a PI controller configured to operate based on a desired current setpoint and the average current measured via the circuitry discussed above) can declare a safety violation if there is a duty cycle close to 0% (very low load current) for a period exceeding the FTTI value setting or if there is a duty cycle value close to 100% (very high load current).

[0069] Under these conditions, because the inherent blanking time separates the active state from the recycle state and the transition between these states in the valve driver, the T of the PWM signal... ON or T OFF Providing sufficient current measurement within the interval becomes almost impossible.

[0070] In other words, when the duty cycle of the PWM signal is close to 0% (e.g., 5% or lower) or 100% (e.g., 95% or higher), T ON and T OFF Any one of them becomes "too short" to provide sufficient current measurement.

[0071] Note that such fading time can be caused by various factors, namely:

[0072] The analog slew rate time (T_SR) spent during the conversion and reaching full “on” operation of the power stage; and the inherent digital delay time (T_ADC), such as the freeze time and startup time of one or more ADCs, ADC HS, ADS LS that convert the analog current sensed at S1 and S2 into digital code.

[0073] The blanking time can vary depending on the specific implementation.

[0074] Values ​​of approximately 5 microseconds or higher are observed in current applications, which can result in appropriate operation being limited to duty cycle values ​​between approximately 5% and 95% when the PWM signal has a frequency of 10 kHz, as is the case in the exemplary applications discussed here.

[0075] Note that in recent applications using PWM frequencies increased to 20kHz, this limitation may become increasingly critical.

[0076] In those cases where no valid redundant current measurement is available within the defined FTTI, the MCU (microcontroller unit, e.g. SPI interface) can be utilized to assert a flag in a communication interface register in order to communicate the error to the MCU.

[0077] Two possible cases can be derived depending on the safety level of the application:

[0078] In high level safety applications, the operation can potentially be stopped even if no error is actually present,

[0079] In low level safety applications, the operation can continue even in the presence of errors.

[0080] In both cases, the unavailability of a reliable monitoring action can lead to critical situations.

[0081] In one or more embodiments, sufficient redundant current monitoring measurements are facilitated via an enhanced diagnostic function even in the presence of "corner" duty cycle values (theoretically 0% or 100%). In certain conditions, this function is able to force or enforce duty cycle values that are favorable to obtain valid current measurements.

[0082] In one or more embodiments, this enhanced diagnostic function can be implemented with, for example, Figure 1 the PWM monitoring circuit 24 of the TLE 4966-2 (e.g. by programming the monitoring circuit in a manner known per se to the person skilled in the art). As discussed, the monitoring circuit 24 can be (already) configured to receive PWM feedback signals from the input analog channels in order to verify that such PWM signals at the valve driver output are in agreement, e.g. equal (with a certain error tolerance), with the values enforced by the controller block 20.

[0083] For example, the diagnostic function can rely on the information provided by the circuit 24 in the presence of "corner" duty cycles: this information provided by the circuit 24 can be utilized in the block 20 to "force" duty cycle values that are sufficient to perform satisfactory redundant current monitoring functions within the FTTI (block 26). In other words, the diagnostic function exemplified here can be performed by the blocks 20, 24, which enable the block 26 to perform satisfactory redundant current monitoring functions (by HS-LS comparison, as exemplified here, or by other methods known to the person skilled in the art).

[0084] This diagnostic action can be designed to work in the on state (i.e. during PWM operation) and in the off state (i.e. the current setpoint CS of the controller 20 is equal to zero).

[0085] This facilitates (very) high application flexibility, since redundant current monitoring measurements can be available even before the load is actually driven in operation.

[0086] In one or more embodiments, the on-state diagnosis can be based on a correct HS-LS comparison (i.e. redundant current monitoring) measurement for each PWM pulse. This result can be achieved in a manner known per se, for example by means of information provided by the comparator as is currently available in valve drives: see for example comparator circuit arrangement 26, coupled to the output from the previously combined Figure 1 The output of the high-side branch and the low-side branch are discussed.

[0087] For example, in one or more embodiments, if due to a very low duty cycle, around 0%, no valid HS-LS comparison measurement is available within the defined FTTI (i.e. after a certain number of PWM waveforms within the total time which is shorter than the FTTI), the duty cycle is increased by an amount which facilitates obtaining a valid HS-LS comparison measurement.

[0088] In case of a PWM frequency in the order of 10 kHz and a FTTI value in the order of tens of ms (e.g. 20 ms), increasing the duty cycle of e.g. one PWM period (e.g. the PWM period just before the end of the FTTI) will have a negligible impact on the average value of the regulating current.

[0089] There is also the possibility to provide a flag to the MCU (e.g. controller 20) to indicate that such a diagnosis has been automatically activated during a regulating cycle.

[0090] In Figure 2 the described on-state functionality is illustrated.

[0091] Figure 2 The graphs in

[0092] the HS-LS comparison signal HS-LS COMP (valid = 1) from the comparator block 26,

[0093] the PWM signal generated by the controller 20 starts at the actuation start time SA (t = 0).

[0094] As illustrated in Figure 2 the duty cycle of the PWM signal is increased for a sufficient time (possibly only a single PWM pulse) to have a valid redundant current monitoring measurement before the FTTI setting expires. The deviation induced in the average current is found to be negligible.

[0095] In one or more embodiments, if no valid HS-LS comparison measurement is available within the defined FTTI due to the duty cycle being near 100% (where the duty cycle is reduced by an amount that facilitates obtaining a valid HS-LS comparison measurement), the same basic criteria are applied in a complementary manner.

[0096] For example, the duty cycle can be reduced (e.g., according to the slew rate time T SR and the intrinsic digital delay time T ADC, which can be assumed to be parameters known to blocks 20 and 26, as previously discussed) to a value sufficient to perform a satisfactory redundant current monitoring function (by HS-LS comparison as exemplified here or other methods known to those skilled in the art).

[0097] Likewise, in the presence of a PWM frequency on the order of 10 kHz and an FTTI value on the order of tens of ms (e.g., 20 ms), reducing the duty cycle of, for example, one PWM period (e.g., the PWM period immediately preceding the end of the FTTI) will have a negligible impact on the average value of the regulation current.

[0098] There is also the possibility of providing a flag to the MCU (e.g., controller 20) to indicate that such a diagnosis has been automatically activated during a regulation cycle.

[0099] In the exemplary case where the duty cycle of the PWM signal is too small (close to 0%) and is increased over a sufficient time (possibly only a single PWM pulse) to perform a satisfactory redundant current monitoring function, the on state as described can be shown in Figure 2 .

[0100] As described above, the same principle, with the necessary modifications, applies to the case where the duty cycle of the PWM signal is too large (close to 100%) and is reduced over a sufficient time (possibly only a single PWM pulse) to perform a satisfactory redundant current monitoring function.

[0101] Figure 2 The graphs in FIGURE 1 show the following possible time behaviors for a common time (abscissa) scale T:

[0102] the HS-LS comparison signal HS-LS COMP (valid = 1) from comparator block 26,

[0103] The PWM signal generated by controller 20 starts from the actuation start time SA (t = 0).

[0104] The duty cycle of the PWM signal is increased over a sufficient time (possibly only a single PWM pulse) (as described in Figure 2or reduced, to have valid redundant current monitoring measurements before the FTTI setting expires. The induced deviation in average current is found to be negligible.

[0105] In one or more embodiments, the off-state diagnostics can be activated automatically, even when the valve driver power stage is enabled and the setpoint CS is equal to zero (no current flows into the load recirculation path, always enabled and duty cycle fixed at 0%).

[0106] In these cases, at each FTTI, a test pulse can be applied to the channel, providing an on-state sufficient to obtain valid HS-LS comparison measurements.

[0107] In this case, even if the channel is not used at this time, the MCU (controller such as 20) is able to continuously detect possible errors, thus providing additional diagnostic coverage compared to the standard implementation, when the error can be detected before the first actuation of the load.

[0108] Figure 3 The off-state function described is shown in the diagram in

[0109] Figure 3 The diagram in shows the following possible time behaviors for a common time (abscissa) scale T:

[0110] The HS-LS comparison signal HS-LS COMP (valid = 1) from the comparator block 26,

[0111] The PWM signal generated by the controller 20 again indicates the nominal start of actuation (t = 0), in the range corresponding to the valve driver power stage enabled with a setpoint CS equal to zero (the recirculation path is always enabled with a duty cycle fixed at 0%, no current flows into the load and therefore there is no intention of "actuation"). It does not positively indicate this nominal start.

[0112] As Figure 3 indicated in the diagram, the duty cycle forced to "1" for a short time (possibly only a single PWM pulse before the expiration of the FTTI) is sufficient to perform a valid redundant current measurement, with negligible current flowing through the load (no load actuation).

[0113] One or more embodiments facilitate the automatic detection, from the information provided by the analog comparator usually available in the valve driver, whether a valid current measurement is available in the redundant current monitor. If the lack of such a valid measurement is diagnosed, a longer (higher) PWM duty cycle can be forced before the expiration of the FTTI from the last valid measurement, and a flag is provided when this action is implemented in the control loop.

[0114] One or more embodiments can be applied in HS-LS comparison and other conventional redundant current monitoring configurations.

[0115] It is found that one or more embodiments are effective in achieving enhanced diagnostics at very low load currents, where duty cycle values are critical and effective measurements cannot be obtained with redundant current monitors that result in current measurements that are out of specification limits (with the risk of falsely detecting errors or failing to detect errors).

[0116] It is additionally understood that the embodiments exemplified herein are generally "transparent" to the particular types of sensing and control performed in blocks such as S1, S2 and 20, and more generally to the particular applications contemplated for drive circuits including the redundant current monitors discussed herein.

[0117] Figure 4 Is an exemplary block diagram of a transmission control unit 1000 for passenger vehicles (PV) and commercial vehicles (CV) in which embodiments as described herein (generally denoted as 100) can be incorporated.

[0118] The following names apply to Figure 4 Certain blocks seen in

[0119] - 1002 - Charge pump

[0120] - 1008 - SPI interface

[0121] - 1020 - Internal power supply

[0122] - 1022 - Auxiliary oscillator

[0123] - 1024 - Main oscillator

[0124] - 1026 and 1028 - Main and auxiliary bandgap voltage references

[0125] - 1038 - Temperature monitor (cooperating with one or more current control drivers 100 as previously described)

[0126] - FET - Field effect transistor driven by driver 100

[0127] - L - Load(s), e.g. solenoid(s) powered by FET(s).

[0128] The skilled person will additionally note that the transmission control unit 1000 as shown in Figure 3 may include various other blocks / elements that are conventional in the art per se and not explicitly mentioned and / or referenced insofar as they are not particularly important to the embodiments.

[0129] The circuit as exemplified herein can include:

[0130] a controller (e.g., 20) configured to generate a pulse width modulated signal (e.g., PWM) to control supply of current to an electrical load (e.g., SV), the pulse width modulated signal having a duty cycle,

[0131] redundant current measurement circuitry (e.g., S1, 10H, 12H, 14H; S2, 10L, 12L, 14L) configured to measure current in the electrical load and provide first and second current measurement signals,

[0132] monitoring circuitry (e.g., 24, 26) coupled to the redundant current measurement circuitry, the monitoring circuitry configured to assert (e.g., high) a current monitor signal (e.g., HS-LS COMP) in response to finding that the first current measurement signal and the second current measurement signal agree with each other,

[0133] wherein the monitoring circuitry is configured to:

[0134] detect a lack of the asserted current monitor signal prior to expiration of a threshold time interval (e.g., FTTI), and

[0135] force the controller to generate at least one pulse of the pulse width modulated signal having a controlled duty cycle prior to expiration of the threshold time interval in response to detecting the lack of the asserted current monitor signal.

[0136] As exemplified herein, this can occur in turn-on state operation (e.g., see Figure 2 ) and turn-off state operation (e.g., see Figure 3 ).

[0137] In a circuit as exemplified herein, the monitoring circuitry can be configured to:

[0138] detect a lack of the asserted current monitor signal prior to expiration of a threshold time interval, wherein the controller is configured to generate (in turn-on state operation) the pulse width modulated signal having a first non-0% duty cycle, and

[0139] force the controller to generate at least one pulse of the pulse width modulated signal having a second non-0% duty cycle different from the first non-0% duty cycle prior to expiration of the threshold time interval in response to detecting the lack of the asserted current monitor.

[0140] In a circuit as exemplified herein (e.g., see Figure 2 ), the monitoring circuitry can be configured to force the controller to generate a single pulse of the pulse width modulated signal having a second non-0% duty cycle different from a first non-0% duty cycle prior to expiration of a threshold time interval.

[0141] In the circuit illustrated herein (e.g., again see Figure 2 ), the single pulse in the pulse width modulated signal can be the last pulse in the pulse width modulated signal before expiration of the threshold time interval (e.g., FTTI).

[0142] In the circuit as illustrated herein, the controller can be configured to generate the pulse width modulated signal with a first non-0% duty cycle that is in a low range adjacent to 0% (duty cycle close to 0%) or in a high range adjacent to 100% (duty cycle close to 100%).

[0143] In the circuit as illustrated herein, the monitoring circuitry can thus be configured to:

[0144] in response to detecting the lack of asserted current monitor, force the controller to generate at least one pulse of the pulse width modulated signal before expiration of the threshold time interval, the at least one pulse having:

[0145] in response to the pulse width modulated signal having a first non-0% duty cycle that is in a low range adjacent to 0%, a second non-0% duty cycle that is higher than the first non-0% duty cycle (i.e., increase duty cycle), and / or

[0146] in response to the pulse width modulated signal (PWM) having a first non-0% duty cycle that is in a high range adjacent to 100%, a second non-0% duty cycle that is lower than the first non-0% duty cycle (i.e., decrease duty cycle).

[0147] Note that regardless of how the current measurement is performed (e.g., HS-LS comparison or full redundancy), the amount of duty cycle increase or decrease to facilitate proper current measurement will ultimately depend on the particular implementation / configuration. By way of (non-limiting) reference, a sufficient measurement of (delta) current can be facilitated by having a PWM active time that is equal to or higher than the blanking time (T_SR plus T_ADC) discussed earlier.

[0148] In the circuit as illustrated herein:

[0149] The current measurement circuitry can include a first current sense path (e.g., SI, 10H, 12H, 14H) and a second current sense path (e.g., S2, 10L, 12L, 14L) configured to measure current in the electrical load and provide a first current measurement signal and a second current measurement signal, respectively,

[0150] The monitoring circuitry can be configured to perform a comparison of the first and second current measurement signals (e.g., at 26), and assert the current monitoring signal responsive to the comparison indicating that the first and second current measurement signals are adapted to one another.

[0151] A system as exemplified herein (e.g., 1000) can include:

[0152] The circuitry exemplified herein, and

[0153] at least one electrical load coupled to the circuitry and configured to receive a supply of electrical current controlled via the pulse width modulated signal generated by the controller.

[0154] A method of operating a circuit or system as exemplified herein can include operating a controller to generate a pulse width modulated signal to control a supply of electrical current to an electrical load, the pulse width modulated signal having a duty cycle, wherein responsive to detecting a lack of an asserted current monitoring signal (e.g., HS-LS COMP) prior to expiration of a threshold time interval (e.g., FTTI), the monitoring circuitry forces the controller to generate at least one pulse of the pulse width modulated signal having a controlled duty cycle prior to expiration of the threshold time interval (e.g., see the ON state operation as exemplified in Figure 2 or the OFF state operation as exemplified in Figure 2 ).

[0155] Details and embodiments can vary, even significantly, with respect to what is described by way of example only, without departing from the scope of protection.

Claims

1. An electronic circuit comprising: a controller configured to generate a pulse width modulated (PWM) signal to control a first current of an electrical load; a redundant current measurement circuit configured to measure the first current and provide a first current measurement signal and a second current measurement signal; and a monitoring circuit coupled to the redundant current measurement circuit, the monitoring circuit configured to assert a current monitoring signal in response to finding that the first current measurement signal and the second current measurement signal agree with each other, wherein the monitoring circuit is configured to: detect a lack of assertion of the current monitoring signal prior to expiration of a threshold time interval, wherein the controller is configured to generate the PWM signal with a first non-0% duty cycle, and in response to detecting the lack of assertion of the current monitoring signal, force the controller to generate a first PWM signal pulse with a second non-0% duty cycle different from the first non-0% duty cycle prior to expiration of the threshold time interval.

2. The electronic circuit of claim 1, wherein the monitoring circuit is configured to force the controller to generate a single PWM pulse of the PWM signal with the second non-0% duty cycle prior to expiration of the threshold time interval, wherein the first PWM signal pulse is the single PWM pulse.

3. The electronic circuit of claim 2, wherein the single PWM pulse is a last pulse in the PWM signal prior to expiration of the threshold time interval. the second non-0% duty cycle is higher than the first non-0% duty cycle when the first non-0% duty cycle is in a low range adjacent to 0%, and wherein the second non-0% duty cycle is lower than the first non-0% duty cycle when the first non-0% duty cycle is in a high range adjacent to 100%.

4. The electronic circuit of claim 1, wherein the first non-0% duty cycle is in a low range adjacent to 0% or in a high range adjacent to 100%, wherein, 5. The electronic circuit of claim 1, wherein: the redundant current measurement circuit comprises a first current sense path and a second current sense path configured to measure the first current and provide the first current measurement signal and the second current measurement signal, respectively; and the monitoring circuit is configured to perform a comparison of the first current measurement signal and the second current measurement signal and assert the current monitoring signal in response to the comparison indicating that the first current measurement signal and the second current measurement signal agree with each other.

6. A system comprising: an electrical load; a controller configured to generate a pulse width modulated (PWM) signal to control a first current of the electrical load; a redundant current measurement circuit configured to measure the first current and provide a first current measurement signal and a second current measurement signal; and a monitoring circuit coupled to the redundant current measurement circuit, the monitoring circuit configured to assert a current monitoring signal in response to finding that the first current measurement signal and the second current measurement signal agree with each other, wherein the monitoring circuit is configured to: ​ ​ detecting, prior to expiration of a threshold time interval, an absence of the asserted current monitor signal, wherein the controller is configured to generate the PWM signal with a first non-0% duty cycle, and forcing, in response to detecting the absence of the asserted current monitor signal, the controller to generate a first PWM signal pulse with a second non-0% duty cycle different from the first non-0% duty cycle prior to expiration of the threshold time interval.

7. The system of claim 6, wherein the electrical load comprises a solenoid valve.

8. The system of claim 7, wherein the solenoid valve is disposed within a motor vehicle.

9. The system of claim 6, wherein the system comprises a transmission control unit for a motor vehicle.

10. The system of claim 6, wherein the monitoring circuit is configured to force the controller to generate a single PWM pulse of the PWM signal with the second non-0% duty cycle prior to expiration of the threshold time interval, wherein the first PWM signal pulse is the single PWM pulse.

11. The system of claim 10, wherein the single PWM pulse is the last pulse in the PWM signal prior to expiration of the threshold time interval.

12. A method comprising: generating a pulse width modulated (PWM) signal to control a first current of an electrical load; measuring the first current with a first path and a second path, and providing a first current measurement signal and a second current measurement signal, respectively, based on the first current measured using the first path and the second path; asserting a current monitor signal in response to finding that the first current measurement signal and the second current measurement signal fit each other; detecting, prior to expiration of a threshold time interval, an absence of the asserted current monitor signal when the PWM signal has a first duty cycle; and generating, in response to detecting the absence of the asserted current monitor signal, a first PWM signal pulse with a second duty cycle different from the first duty cycle prior to expiration of the threshold time interval.

13. The method of claim 12, wherein generating the first PWM signal pulse comprises: generating a single PWM signal pulse prior to expiration of a threshold time interval.

14. The method of claim 13, wherein the second duty cycle is higher than the first duty cycle when the first duty cycle is below 50%, and the second duty cycle is lower than the first duty cycle when the first duty cycle is above 50%.

15. The method of claim 14, wherein the first duty cycle is below 5% or above 95%.

16. The method of claim 12, wherein the threshold time interval is about 20 ms.

17. The method of claim 12, wherein the PWM signal has a frequency between 10 kHz and 20 kHz.

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