Silicon-on-insulator chip structure with substrate-embedded optical waveguide and method

Abstract

This invention discloses a silicon-on-insulator (SOI) chip structure and method with a substrate-embedded optical waveguide. In the method, an optical waveguide is formed within a trench in a bulk substrate prior to the wafer bonding process that forms the SOI structure. Subsequently, a front-end process (FEOL) can be performed to form additional optical and / or electronic devices in and / or on top of the silicon layer. By embedding the optical waveguide in the substrate before wafer bonding, rather than forming it during the FEOL process, the strict limitations on the size of the core layer of the optical waveguide are avoided. The core layer of the substrate-embedded optical waveguide can be relatively large, allowing for a relatively long cutoff wavelength. Therefore, this substrate-embedded optical waveguide brings different functionalities to the SOI chip structure compared to FEOL optical waveguides.

Description

Technical Field

[0001] This invention relates to integrated circuits (ICs), and more specifically, to embodiments of a silicon-on-insulator (SOI) chip structure having at least one optical waveguide, and embodiments of a method for forming the SOI chip structure. Background Technology

[0002] Integrated circuit (IC) chips can combine both optical and electronic components. Such chips can be bulk semiconductor (e.g., bulk silicon) chip structures or semiconductor-on-insulator (e.g., silicon-on-insulator (SOI)) chip structures. Advantages associated with SOI chip structures include, but are not limited to, improved insulation, improved radiation tolerance, and reduced parasitic capacitance. A disadvantage associated with SOI chip structures involves integrating both optical and electronic components into the same SOI chip structure. Specifically, in an SOI chip structure with both optical and electronic components, the maximum size of the core layer of the optical waveguide can be limited by other critical dimensions (CDs). Unfortunately, since the size of the core layer of the optical waveguide determines the characteristics of the waveguide, including the cut-off wavelength (i.e., the maximum wavelength of any optical signal that can propagate through the waveguide), any limitation on the size of the core layer also affects functionality. Summary of the Invention

[0003] Embodiments of a silicon-on-insulator (SOI) chip structure are disclosed. The structure may include a substrate. Trenches may extend from the top and bottom surfaces of the substrate into the substrate. The structure may also include a substrate-embedded optical waveguide (referred to herein as a first waveguide) within the trench. The first waveguide may include a cladding layer disposed within the trench and a core layer on the cladding layer, such that the bottom and sides of the core layer are covered by the cladding layer. The structure may also include an insulating layer located on the top surface of the substrate and extending laterally over the first waveguide. The structure may further include a silicon layer on the insulating layer and one or more front-end-of-the-line (FEOL) devices having components in and / or above the silicon layer (i.e., above the insulating layer). The FEOL devices may include, for example, additional optical and / or electronic devices.

[0004] This document also discloses method embodiments for forming the aforementioned SOI chip structure. Typically, the method may include providing a substrate. A trench extending from a top surface to a bottom surface may be formed in the substrate. A substrate-embedded optical waveguide (referred to herein as a first waveguide) may be formed in the trench, such that it includes a cladding layer and a core layer. The cladding layer may be disposed along the bottom and sidewalls of the trench. The core layer may be located within the trench on the cladding layer, such that its bottom and sides are covered by the cladding layer. An insulating layer may be formed on the top surface of the substrate, such that it covers the first waveguide. After forming the insulating layer, a silicon layer may be formed on the insulating layer. After forming the silicon layer on the insulating layer, an FEOL process may be performed to form one or more FEOL devices (e.g., additional optical and / or electronic devices) having components in and / or above the silicon layer (i.e., above the insulating layer). Attached Figure Description

[0005] The invention will be better understood through the following detailed description with reference to the accompanying drawings, which are not necessarily drawn to scale, wherein:

[0006] Figure 1 A cross-sectional view of a chip structure with optical and electronic device regions;

[0007] Figures 2A to 2B Different cross-sectional views AA and BB are shown for embodiments of a silicon-on-insulator (SOI) chip structure with a substrate-embedded optical waveguide.

[0008] Figure 2C for Figures 2A to 2B (As described above) the cross-sectional views in the AA and BB directions and Figures 3A to 3B An exemplary layout diagram (as described below);

[0009] Figures 3A to 3B The images AA and BB show different cross-sectional views, illustrating another embodiment of an SOI chip structure with a substrate-embedded optical waveguide.

[0010] Figure 4 A cross-sectional schematic diagram of another embodiment of an SOI chip structure having a substrate-embedded optical waveguide;

[0011] Figure 5 A flowchart of an embodiment of the disclosed method;

[0012] Figure 6 and Figure 7 According to Figure 5 The flowchart forms a cross-sectional view of the partially completed structure;

[0013] Figures 8 to 10 According to Figure 5 The flowchart shows a cross-sectional view of the partially completed structure formed by process flow A; and

[0014] Figures 11 to 21 According to Figure 5 The flowchart shows a cross-sectional view of the partially completed structure formed by process flow B.

[0015] Explanation of main component symbols

[0016] 100 Silicon-on-Insulator (SOI) Chip Structure

[0017] 101 substrate

[0018] 102 Insulation layer

[0019] 104 interlayer dielectric (ILD) material

[0020] 105 Shallow Trench Isolation (STI) Area

[0021] 106 Silicon (Si) layer

[0022] 110 Optical Device Area

[0023] 112 Photodetector

[0024] 113 Silicon (Si) waveguide

[0025] 114 Silicon Nitride (SiN) Waveguide

[0026] 120 Electronic Device Area

[0027] 122 Field-Effect Transistor (FET)

[0028] 200.1 to 200.3 Silicon-on-Insulator (SOI) Chip Structure

[0029] 201 substrate

[0030] 202 Insulation Layer

[0031] 203 Etching Stop Layer

[0032] 204 Interlayer Dielectric (ILD) Material

[0033] 205 Shallow Trench Isolation (STI) Area

[0034] 206 Silicon (Si) layer

[0035] 210 Optical Device Area

[0036] 212 Photodetector

[0037] 213 Third Waveguide

[0038] 214a, 214b Second waveguide

[0039] 220 Electronic Device Area

[0040] 222 Field-Effect Transistor (FET)

[0041] 250 First Waveguide

[0042] 251 Coating Layer

[0043] 251L lower cladding layer

[0044] 251u top coating

[0045] 252 Core Layer

[0046] 253 Waveguide Extension

[0047] 255 trench

[0048] 259 V-groove / recess

[0049] 260 Insulation Area

[0050] 265 Additional Grooves

[0051] 281 Bottom

[0052] 282,283 Top surface

[0053] 289 Mid-stage process (MOL) contact

[0054] 290 fiber optic cable

[0055] 291 Coating Layer

[0056] 292 Core Layer

[0057] Process steps for 502, 504, 506, and 508

[0058] Process steps 510, 512, 514, 516

[0059] Process steps 518, 520, 522, 524

[0060] Process steps 526, 528, 530, 540

[0061] 801 Coating Material

[0062] 901 Core Materials

[0063] 1101 Coating Material

[0064] 1201 Protective Mask

[0065] 1301 core material

[0066] 1601 Additional Covering Material

[0067] d trench depth

[0068] t cladding ,t sub thickness

[0069] w core ,w trench width. Detailed Implementation

[0070] As mentioned above, the advantages associated with silicon-on-insulator (SOI) chip structures include, but are not limited to, improved insulation, improved radiation tolerance, and reduced parasitic capacitance. One disadvantage associated with SOI chip structures involves integrating both optical and electronic components into the same SOI chip structure. Specifically, in SOI chip structures with both optical and electronic components, the maximum size of the core layer of the optical waveguide can be limited by other critical dimensions (CDs).

[0071] For example, Figure 1 This is a cross-sectional view of an exemplary SOI chip structure 100. The SOI chip structure 100 includes: a substrate 101 (e.g., a silicon (Si) substrate); an insulating layer 102 (e.g., a buried oxide (BOX) layer) on the substrate 101; and a Si layer 106 on the insulating layer 102. The SOI chip structure 100 includes a plurality of device regions having an optical device region 110 and an electronic device region 120.

[0072] Optionally, the Si layer 106 is relatively thick in the optical device region 110 and relatively thin in the electronic device region 120. The optical device region 110 may include one or more optical devices above the insulating layer 102. Such optical devices may include, for example, one or more Si waveguides 113 (each Si waveguide having a Si core layer patterned into the Si layer 106), one or more silicon nitride (SiN) waveguides 114 (each SiN waveguide having a SiN core layer on a shallow trench isolation (STI) region 105 above the level of the Si waveguide 113), one or more photodetectors 112 (each photodetector 112 having components both within and above the Si layer 106), one or more optical modulators, etc. The electronic device region 120 may include one or more electronic devices. Such electronic devices may include complementary metal-oxide-semiconductor (CMOS) devices (e.g., one or more field-effect transistors (FETs) 122) and various other electronic devices (e.g., active or passive semiconductor devices, etc.). Optical and electronic devices may be covered by an interlayer dielectric (ILD) material 104. The ILD material 104 may have a planar top surface. Mid-process (MOL) contacts may extend vertically through the ILD material 104 to one or more optical and / or electronic devices as needed.

[0073] In this SOI chip structure 100, the maximum height of the core layer of the Si waveguide 113 is limited by a critical dimension (CD) associated with the Si layer 106. Specifically, the maximum height of the core layer of the Si waveguide 113 is limited by the maximum allowable height of the Si layer within the optical device region 110. Furthermore, the maximum height of the SiN core layer of the SiN waveguide 114 is at least partially limited by a critical dimension (CD) associated with the MOL contacts. Specifically, one of the CDs in the MOL contacts is a maximum allowable height, which is set to minimize contact resistance. Since the MOL contacts have a maximum height, since the MOL contacts and the ILD material 104 extending through those MOL contacts have co-planar top surfaces, and since the SiN core layer of the SiN waveguide 114 is embedded in the ILD material 104, then the maximum height of the SiN core layer may not exceed the height of the ILD material 104 above the top of the Si layer 106 within the optical device region 110. Unfortunately, since the size of the core layer of an optical waveguide determines its characteristics, including the cutoff wavelength (i.e., the maximum wavelength of any optical signal that can propagate through the waveguide), any restrictions on the size of the core layer will also affect functionality.

[0074] Based on the foregoing, this document discloses embodiments of a silicon-on-insulator (SOI) chip structure having a substrate-embedded optical waveguide. This document also discloses embodiments of a method for forming the SOI chip structure. In the method embodiments, a substrate-embedded optical waveguide (referred to herein as a first waveguide) is formed within a trench in a bulk substrate prior to the wafer bonding process for forming the SOI structure. Subsequently, a front-end process (FEOL) can be performed to form additional optical and / or electronic devices in and / or on top of the silicon layer. By embedding the optical waveguide in the substrate prior to wafer bonding rather than during the FEOL process, strict limitations on the size of the core layer of the optical waveguide are avoided. The core layer of the substrate-embedded optical waveguide can be relatively large, thus allowing for a relatively long cutoff wavelength. Therefore, this substrate-embedded optical waveguide can provide different functionalities to the SOI chip structure compared to any FEOL optical waveguide. Furthermore, due to the relatively large core layer of the substrate-embedded optical waveguide, improved coupling with off-chip optical fibers can be achieved.

[0075] More specifically, this document discloses various embodiments of silicon-on-insulator (SOI) chip structures 200.1-200.3, each embodiment including at least one first waveguide 250, particularly a substrate-embedded optical waveguide. Specifically, Figures 2A to 2B The images show different cross-sectional views AA and BB of a silicon-on-insulator (SOI) chip structure 200.1, respectively. Figure 2C An exemplary layout diagram is provided to illustrate the orientation of cross-sectional views AA and BB. Figures 3A to 3B The figures AA and BB show different cross-sectional views of the alternative SOI chip structure 200.2, respectively. It should be noted that... Figure 3A and Figure 3B The orientations in the cross-sectional diagrams AA and BB are basically the same as Figure 2C The directions shown are the same. Figure 4 Cross-sectional view AA of another alternative SOI chip structure 200.3.

[0076] SOI chip structures 200.1-200.3 may include a substrate 201. Substrate 201 may be, for example, a silicon (Si) substrate. Alternatively, substrate 201 may be any other substrate suitable for an SOI chip structure. Substrate 201 may have a bottom surface 281 and a top surface 282 opposite to the bottom surface. The bottom surface 281 and the top surface 282 may be substantially planar and parallel to each other. The thickness (t) of substrate 201, measured from the bottom surface 281 to the top surface 282 of substrate 201. sub It can be in the range of, for example, 1 micrometer (μm) to 10 μm or even larger (e.g., 50 μm, 100 μm, 150 μm, 200 μm or larger).

[0077] SOI chip structures 200.1-200.3 may also include at least one first waveguide 250, particularly a substrate-embedded optical waveguide. Specifically, a trench 255 may extend from the top surface 282 to the bottom surface 281 into the substrate 201. The dimensions of the trench 255 (including the depth of the trench 255) trench (e.g., measured from the top surface 282 of substrate 201 to the bottom surface of trench 255) can be determined according to the specific application and thickness (t) of substrate 201. sub The depth of trench 255 can vary depending on the thickness of substrate 201. For example, in some embodiments, trench 255 can be relatively shallow (e.g., the depth of trench 255 can be less than 1 / 4 of the thickness of substrate 201). In other embodiments, trench 255 can be relatively deep (e.g., the depth of trench 255 can be greater than 1 / 4, 1 / 2, 3 / 4, etc., of the thickness of substrate 201). Therefore, depending on the thickness of substrate 201, the depth of trench 255 can range from less than 1 micrometer (μm) to 10 μm or even greater (e.g., 50 μm, 100 μm, 150 μm, 200 μm or higher).

[0078] The first waveguide 250 may be primarily contained within the trench 255. That is, the first waveguide 250 may include a cladding layer 251. The cladding layer may be lined along the bottom surface and sidewalls of the trench 255. The first waveguide 250 may also include a core layer 252 centered on a horizontal portion of the cladding layer 251 and laterally surrounded by the cladding layer 251. Therefore, the bottom and sides of the core layer 252 are covered by the cladding layer 251. It should be understood that the dimensions of the core layer 252 will depend on the dimensions of the trench 255 and the thickness (t) of the cladding layer 251. cladding The depth of trench 255 (d) varies. For example, if the depth of trench 255 (d) trench The trench is approximately 60 μm wide, and the width (w) of the trench is approximately 60 μm. trench The thickness of the coating layer 251 is approximately 60 μm. cladding If the thickness is approximately 20 μm, then the width of the core layer 252 (w) is... core The thickness is approximately 20 μm, and the core layer is 252 (h) core The height is approximately 40 μm.

[0079] In any case, the cladding layer 251 of the first waveguide 250 may be made of a cladding material having a first refractive index, and the core layer 252 may be made of a core material having a second refractive index greater than the first refractive index to allow optical signals to propagate through the waveguide 250. In some embodiments, the cladding material of the cladding layer 251 may be an oxide material with a refractive index less than 2.0 and more specifically less than 1.6, such as silicon dioxide. In other embodiments, the cladding material of the cladding layer 251 may be a different oxide material or some other suitable cladding material with a similarly low refractive index, particularly a first refractive index having a second refractive index less than that of the core material. In some embodiments, the core material of the core layer 252 of the first waveguide 250 may be a nitride material with a refractive index greater than 2.0, such as silicon nitride (SiN). In other embodiments, the core material of the core layer 252 may be an oxide material that differs from the material used for the cladding material and similarly has a relatively high refractive index. For example, in some embodiments, the core material of the core layer 252 may be niobium oxide (NbO) with a refractive index of about 2.2 or higher. In other embodiments, the core material of the core layer 252 may be any other suitable core material having a similar high refractive index, particularly a core material having a second refractive index greater than the first refractive index of the covering material.

[0080] As discussed in more detail below regarding the method, in some embodiments, the overlay 251 may be a continuous or single-layer overlay material lining the bottom and sidewalls of the trench 255. In other embodiments, the overlay 251 may be a multi-layer overlay. For example, the overlay 251 may include a lower overlay 251l covering the bottom of the trench 255. The bottom surface of the core layer 252 may be adjacent to, narrower than, and substantially centered on the lower overlay 251l, such that the outer edge of the lower overlay 251l extends laterally beyond the sidewalls of the core layer 252. The overlay 251 may also include an upper overlay 251u, which is located above and adjacent to the outer edge of the lower overlay 251l, and extends upward along the sidewalls of the trench 255, such that it is further laterally positioned between and adjacent to the sidewalls of the trench 255 and the sidewalls of the core layer 252. In some embodiments, the lower cladding layer 251l and the upper cladding layer 251u may be made of the same cladding material (see the discussion of cladding materials above). In other embodiments, the lower cladding layer 251l and the upper cladding layer 251u may be made of different cladding materials (provided that the refractive index of both is less than that of the core material) (see also the discussion of cladding materials above).

[0081] The SOI chip structures 200.1-200.3 may further include an insulating layer 202 on the top surface 282 of the substrate 201. The insulating layer 202 may be, for example, a silicon dioxide layer (also referred to herein as a buried oxide (BOX) layer) or any other suitable insulating layer. It should be noted that the thickness of the insulating layer 202 may vary depending on the application and technology node. For example, the thickness of the insulating layer 202 may range from less than 100 nm to 0.5 μm or higher (e.g., approximately 2 μm). The insulating layer 202 may cover the top surface 282 of the substrate 201 and may further extend laterally over any embedded structures within the substrate 201 (e.g., over each first waveguide 250).

[0082] SOI chip structures 200.1-200.3 may have one or more distinct device regions. These device regions may include, for example, an electronic device region 220 and an optical device region 210. SOI chip structures 200.1-200.3 may also include a silicon layer 206 (particularly a single-crystal silicon layer) on an insulating layer 202, extending laterally and covering the insulating layer 202 in each device region. In some embodiments, the Si layer 206 may be thinner in the electronic device region 220 than in the optical device region 210. For example, in some embodiments, the thickness of the silicon layer 206 in the electronic device region 220 may be between 10 nm and 100 nm (e.g., approximately 88 nm), and the thickness of the silicon layer 206 in the optical device region 210 may be between 125 nm and 175 nm (e.g., approximately 150 nm or 160 nm).

[0083] SOI chip structures 200.1-200.3 may also include insulating regions, particularly shallow trench isolation (STI) regions 205 within the Si layer 206. STI regions 205 may include shallow trenches extending completely through the Si layer 206 to the insulating layer 202. Each shallow trench may be filled with one or more layers of insulating material. The insulating material for the STI regions 205 may be silicon dioxide or any other suitable insulating material. It should be noted that if the Si layer 206 is thicker within the optical device region 210 than in the electronic device region 220, the STI regions 205 within the optical device region 210 will also be thicker. The STI regions 205 may be patterned during processing so that they define the boundaries of insulating devices within and between various device regions as needed. An STI region 205 may be specifically located within the Si layer 206 in the optical device region 210 and aligned above the first waveguide 250. The STI regions 205 and the insulating layer 202 may provide additional cladding for the first waveguide 250.

[0084] The SOI chip structures 200.1-200.2 may also include one or more front-end process (FEOL) electronic devices in the electronic device region 220. Exemplary FEOL electronic devices may include active semiconductor devices and / or passive semiconductor devices. Active semiconductor devices may include, for example, complementary metal-oxide-semiconductor (CMOS) devices (e.g., one or more field-effect transistors (FETs) 222 as shown) or any other suitable type of active semiconductor device. Passive semiconductor devices may include resistors, capacitors, etc. Such FEOL electronic devices are well known in the art; therefore, details thereof are omitted from this specification to allow the reader to focus on the significant aspects of the disclosed embodiments.

[0085] As described above, the first waveguide 250 (i.e., the substrate-embedded optical waveguide) may be located within the substrate 101 in the optical device region 210. Optionally, the SOI chip structures 200.1-200.3 may also include one or more FEOL optical devices, which are also within the optical device region 210 but above the insulating layer 202. Exemplary FEOL optical devices that may be incorporated into the SOI chip structures 200.1-200.3 include any of the following: one or more second waveguides 214a-214b, one or more third waveguides 213, one or more photodetectors 212, and / or any other suitable FEOL optical devices.

[0086] More specifically, SOI chip structures 200.1-200.3 may include a third waveguide 213. The third waveguide 213 may be a Si optical waveguide comprising a Si core, which includes a portion of a Si layer 206 and has length and width dimensions defined by the STI region 205. The dimensions of the core layer of the third waveguide 213 (e.g., particularly height and width) may be significantly smaller than the dimensions of the core layer of the first waveguide 250 (see also the discussion of critical dimensions (CD) below). The cladding layer of the third waveguide 213 may be composed of a dielectric material immediately adjacent to the Si core layer (e.g., in laterally adjacent STI regions, in the underlying insulating layer 202, and in the upper ILD material 204). SOI chip structures 200.1-200.3 may also include other types of FEOL optical devices, such as photodetectors 212 (e.g., germanium photodetectors) and / or optical signal modulators. Each of these FEOL optical devices may include a portion of the Si layer 206 within the optical device region 210. Photodetectors and optical signal modulators are well known in the art, and therefore details of these devices are omitted from this specification in order to allow the reader to focus on the significant aspects of the disclosed embodiments.

[0087] SOI chip structures 200.1-200.3 may also include a conformal etch stop layer 203 covering some FEOL optical devices, such as the third waveguide 213, photodetector 212, and modulator within optical device region 210. Etch stop layer 203 may further cover FEOL electronics in electronic device region 220, as well as STI regions 205 within and between device regions 210 and 220. Etch stop layer 203 may be, for example, a silicon nitride (SiN) etch stop layer.

[0088] SOI chip structures 200.1-200.3 may also include one or more second waveguides 214a-214b within the optical device region 210. The core layer for each second waveguide 214a-214b may be aligned above the etch stop layer 203 and above the STI region 205 (as discussed in more detail below). The dimensions (e.g., particularly height and width) of the core layer of each second waveguide 214a-214b may be significantly smaller than the dimensions of the core layer of the first waveguide 250 (see also the discussion of critical dimensions (CD) below). SOI chip structures 200.1-200.3 may also include one or more layers of interlayer dielectric (ILD) material 204 on the etch stop layer 203, extending laterally over and covering the core layer of each second waveguide 214a-214b. The ILD material 204 may include, for example, doped silicon glass (e.g., phosphosilicate glass (PSG) or borosilicate glass (BPSG)), silicon dioxide, or any other suitable ILD material. In any case, this ILD material 204 should have a relatively low refractive index (e.g., below 2.0) to allow it to be used as a cladding material for the second waveguides 214a-214b. The ILD material 204 may have a planar top surface 283, which is substantially parallel to the planar bottom and top surfaces 281-282 of the substrate 201.

[0089] The refractive index of the core layer of each second waveguide 214a-214b can be greater than the refractive index of the surrounding dielectric material (e.g., the insulating material in the lower STI region 205 and the side and top ILD materials 204). In some embodiments, the core layer of each second waveguide 214a-214b can be SiN with a refractive index greater than 2.0.

[0090] The core layer 252 of the first waveguide 250 (i.e., the core layer 252 of the substrate-embedded optical waveguide) may be an elongated structure having a first end. Similarly, the core layers of each of the second waveguides 214a-214b may be elongated structures having a second end. In some embodiments, one of the second ends of the core layer of one of the second waveguides (e.g., see second waveguide 214a) may cover one of the first ends of the core layer 252 of the first waveguide 250 (e.g., see...). Figure 2C(Layout diagram). This configuration potentially enables evanescent-wave coupling between the two waveguides (i.e., between the first waveguide 250 and the second waveguide 214a). Those skilled in the art will recognize that "evanescent-wave coupling between waveguides" refers to placing the two waveguides close enough that the evanescent field generated by the waveguides excites a wave in the adjacent waveguide. However, evanescent-wave coupling may not be achievable depending on the core and cladding materials of the two waveguides (i.e., in the first waveguide 250 and the second waveguide 214a), and further depending on the separation distance between the core layers of the two waveguides. In this case, the SOI chip structure, particularly SOI chip structures 200.2 and 200.3, may further include a waveguide extender 253. Waveguide extension 253 may extend downward through STI region 205 and insulating layer 202 to core layer 252 of first waveguide 250, such that a first end of core layer 252 of first waveguide 250 and a second end of core layer of second waveguide 214a each contact waveguide extension 253 (as shown), thereby providing the desired coupling. Alternatively, waveguide extension 253 may extend only partially through STI region 205 and (optionally) insulating layer 202, such that proximity of waveguide extension 253 to the first end of core layer 252 of first waveguide 250 is sufficient to achieve evanescent wave coupling. Waveguide extension 253 may be made, for example, of the same core material as core layer 252 of first waveguide 250, the same core material as core layer of second waveguide 214a, or some other suitable core material.

[0091] Alternatively, the core layer 252 of the first waveguide 250 and the core layer of the second waveguide (e.g., see the second waveguide 214b) can be completely offset. For example, as shown, no part of the core layer of the second waveguide 214b may cover the core layer of the first waveguide 250.

[0092] Optionally, the SOI chip structure (e.g., see...) Figure 4 The SOI chip structure 200.3 may also include one or more additional insulating regions 260, particularly one or more substrate-embedded insulating regions within the electronics region 220. For example, the substrate 201 may have additional trenches 265. The additional trenches 265 may be located within the electronics region 220 and, like trenches 255, may extend from the top surface 282 to the bottom surface 281 of the substrate 201. The dimensions of the additional trenches 265 (including the depth of the additional trenches 265 measured from the top surface 282 of the substrate 201 to the bottom surface of the additional trenches 265) may vary depending on the specific application and thickness of the substrate 201. subThe depth of the additional trench 265 can vary depending on the thickness of the substrate 201. For example, in some embodiments, the additional trench 265 can be relatively shallow (e.g., the depth of the additional trench can be less than 1 / 4 of the thickness of the substrate 201). In other embodiments, the additional trench 265 can be relatively deep (e.g., the depth of the additional trench 265 can be greater than 1 / 4, 1 / 2, 3 / 4, etc., the thickness of the substrate 201). Therefore, depending on the thickness of the substrate 201, the depth of the additional trench 265 can range from less than 1 micrometer (μm) to 10 μm or greater (e.g., 50 μm, 100 μm, 150 μm, 200 μm or greater). In any case, the bottoms of trenches 255 and 265 can be located at the same level below the top surface 282 of the substrate 201 (as shown). Alternatively, the bottoms of trenches 255 and 265 can be located at different levels below the top surface 282 of the substrate 201. An insulating material can fill the additional trench 265 to form an insulating region 260 (i.e., the substrate is embedded in the insulating region). The insulating material filling the additional trench 265 can be, for example, the same material as the cladding material used for the cladding layer 251 (or, if applicable, the same cladding material used for the lower or upper layers of a multilayer cladding). Such a substrate-embedded insulating region can reduce parasitic capacitance. Furthermore, when / if the electronic device in the electronic device region 220 is to be used for a radio frequency (RF) application, a substrate-embedded insulating region 260 aligned below the electronic device (e.g., Figure 4 The SOI chip structure shown in 200.3 can provide improved harmonic reduction. It should be noted that by embedding the insulating region under a local substrate under a specific chip component, the need for a thick insulating layer 202 (i.e., a thick BOX layer) in some technologies can be eliminated.

[0093] SOI chip structures 200.1-200.3 may also include mid-process (MOL) contacts 289. These MOL contacts 289 may extend vertically through the ILD material 204 to optical and electronic devices as needed. For example, the MOL contacts 289 may rest on terminals of photodetectors 212, FETs 222, etc.

[0094] In SOI chip structures 200.1-200.3, the maximum height of the core layer of the third waveguide 213 (e.g., a Si optical waveguide) is limited by a critical dimension (CD) associated with the Si layer 206. Specifically, the maximum height of the core layer of the third waveguide 213 is limited by the maximum allowable height of the Si layer 206 within the optical device region 210. As described above, the thickness of the Si layer 206 within the optical device region 210 can be between 125 nm and 175 nm (e.g., approximately 150 nm or 160 nm). Furthermore, the maximum height of the core layer of each of the second waveguides 214a-214b is at least partially limited by a critical dimension (CD) associated with the MOL contact 289. Specifically, one of the CDs in the MOL contact 289 is the maximum allowable height, which is configured to minimize contact resistance. Because the MOL contact 289 has a maximum height, because the MOL contact and the ILD material 204 through which those MOL contacts extend have coplanar top surfaces, and because the core layer of each second waveguide 214a-214b is embedded in the ILD material 204, the maximum height of the core layer of each second waveguide 214a-214b can be varied to not exceed the height of the ILD material 204 above the top of the Si layer 206 within the optical device region 210. For example, in some embodiments, the maximum height of the core layer of each second waveguide 214a-214b (e.g., each SiN waveguide) above the STI region 205 can be 300 nm. Since the size of the core layer of the waveguide determines the characteristics of these waveguides, including the cutoff wavelength (i.e., the maximum wavelength of any optical signal that can propagate through the waveguide), the aforementioned limitation imposed on the size of the core layer of any second waveguide 214a-214b or third waveguide 213 also limits their functionality. However, since the first waveguide 250 is embedded within the substrate 201, it is not limited by the CD (cutoff wavelength) associated with front-end process (FEOL) or mid-end process (MOL) characteristics. Therefore, the size of the core layer 252 of the first waveguide 250 (which, depending on the thickness of the substrate 201, can potentially be measured in tens or hundreds of micrometers (μm)) can be significantly larger than the size of the core layer of any of the second waveguides 214a-214b and / or the third waveguide 213 (typically measured in hundreds of nanometers (nm)). Consequently, the first waveguide 250 will have a significantly higher cutoff wavelength than any of the second waveguides 214a-214b or the third waveguide 213, and will bring different functionality to the SOI chip structure compared to the second and third waveguides.

[0095] Furthermore, since the core layer 252 of the first waveguide 250 is relatively large, improved coupling with the external optical fiber can be achieved. More specifically, such as Figure 2B and Figure 3BAs shown, SOI chip structures 200.1-200.3 may also include a V-groove 259 in the substrate 201 on one side. The V-groove 259 may be configured to accommodate an external optical fiber 290. The optical fiber 290 may include a cylindrical core layer 292 and a cladding layer 291 wound around the core layer 292. As described above, a first end of the core layer 252 of the first waveguide 250 may be aligned below a second end of the core layer of the second waveguide 214a. In this case, the opposite first end of the core layer 252 of the first waveguide 250 may extend into and be exposed in the groove 259, such that the core layer 252 of the first waveguide 250 and the core layer 292 of the optical fiber 290 are end-to-end aligned. Since the core layer 252 of the first waveguide 250 can be relatively large, the core layer 252 can be designed to have one or more dimensions (e.g., height or height and width) that match or at least approximate the corresponding dimensions of the core layer 292 of the optical fiber, thereby improving the coupling between the off-chip optical fiber and the on-chip waveguide.

[0096] refer to Figure 5 The flowchart also discloses embodiments of a method for forming a silicon-on-insulator (SOI) chip structure, the chip structure having at least one substrate-embedded waveguide (e.g., as shown in the flowchart). Figures 2A to 4 (As shown in the figure and the detailed description above).

[0097] The method may include providing a substrate 201 (see process step 502 and...). Figure 6 The substrate 201 can be, for example, a silicon (Si) substrate. Alternatively, the substrate 201 can be any other substrate suitable for an SOI chip structure. The substrate 201 can have a bottom surface 281 and a top surface 282 opposite to the bottom surface. The bottom surface 281 and the top surface 282 can be substantially planar and parallel to each other.

[0098] The method may further include embedding the first waveguide 250 within a substrate 201 in the optical device region 210, and optionally, simultaneously embedding the insulating region 260 within a substrate 201 in the electronic device region 220.

[0099] Specifically, using conventional photolithography patterning and etching processes, one or more trenches can be formed in the substrate 201, such that each trench extends from the top surface 282 to the bottom surface 281 of the substrate 201 (see process step 504 and...). Figure 7 ).

[0100] For example, in process step 504, the trench 255 of the first waveguide 250 can be patterned and etched. The depth (d) of the trench 255 trench(As measured from the top surface 282 of substrate 201 to the bottom of trench 255) can be predetermined according to the desired application. For example, the depth of trench 255 can range from less than 1 micrometer (μm) to 10 μm or even greater (e.g., 50 μm, 100 μm, 150 μm, 200 μm or higher).

[0101] Optionally, at process step 504, additional trenches 265 for insulating region 260 may be patterned and etched simultaneously. The depth of additional trenches 265 (as measured from the top surface 282 of substrate 201 to the bottom of trench 255) may be predetermined according to the desired application. For example, the depth of additional trenches 265 may range from less than 1 micrometer (μm) to 10 μm or greater (e.g., 50 μm, 100 μm, 150 μm, 200 μm or greater). In any case, the bottoms of trenches 255 and 265 may be located at the same level below the top surface 282 of substrate 201 (as shown). Alternatively, the bottoms of trenches 255 and 265 may be located at different levels below the top surface 282 of substrate 201.

[0102] The method may further include forming at least one first waveguide 250 within trench 255 (i.e., substrate embedded optical waveguide), and, if applicable, simultaneously forming an insulating region 260 within an additional trench 265 (i.e., substrate embedded insulating region) (see process step 506). The formation of the first waveguide 250 within trench 255 and, if applicable, the simultaneous formation of the insulating region 260 within the additional trench 265 can be performed using any number of different process flows, including but not limited to process flow A and process flow B, which are shown in the flowchart and described in more detail below.

[0103] For example, referring to process flow A, the cladding material 801 of the first waveguide 250 can be conformally deposited on the top surface 282 of the substrate 101 and enter the trench (see process step 508 and...). Figure 8 Specifically, a conformal coating layer can be deposited such that it is lined along the sidewalls and bottom of the trench 255 without compressing or filling it. For example, if the depth of the trench 255 (d) trench The diameter of the trench is approximately 60 μm, and the width of the trench (w) is approximately 60 μm. trench The thickness of the coating layer 251 is approximately 60 μm. cladding The core material 901 for the first waveguide 250 can be approximately 20 μm thick to leave sufficient space for the core layer (e.g., approximately 20 μm). Next, the core material 901 for the first waveguide 250 can be deposited onto the cladding material 801 to fill the remaining space within the trench 255 (see process step 510 and...). Figure 9Then a polishing process (e.g., conventional chemical mechanical polishing (CMP)) can be performed to remove the cladding material 801 and the core material 901 from the top surface 282 of the substrate 201 (see process steps 512 and 501). Figure 10 As a result, the first waveguide 250 includes a cladding layer 251 and a core layer 252. The cladding layer 251 is lined on the bottom surface and sidewalls of the trench 255. The core layer 252 is centered on the horizontal portion of the cladding layer 251 and is laterally surrounded by the cladding layer 251. The cladding layer 251 is produced using process flow A; the cladding layer 251 is a continuous or single-layer cladding material that is lined along the bottom surface and sidewalls of the trench 255 and surrounds the bottom surface and sides of the core layer 252.

[0104] When forming the insulating region 260 simultaneously using process flow A, the overlay material (discussed in more detail below) should be a suitable insulating material. In this case, the width of the additional trench 265 for the insulating region 260 should be smaller than the width of the trench 255 for the first waveguide 250. More specifically, the width of the additional trench 265 should be such that it can completely fill the additional trench 265 when the overlay material for the first waveguide 250 is deposited (as shown). Alternatively, the width of the additional trench 265 should be such that when the overlay material for the first waveguide 250 is deposited, it can be pinched off at the top of the additional trench 265, thereby leaving space encapsulated within the additional trench 265 (e.g., air gap, gas filling gap, void, etc.) (not shown). Therefore, the insulating region 260 is completed when the final CMP process is performed in process step 512.

[0105] Alternatively, referring to process flow B, the cladding material 1101 for the lower cladding layer of the first waveguide 250 can be deposited on the top surface 282 of the substrate 101 and deposited into the trench (see process steps 514 and 515). Figure 11 Specifically, the cladding material 1101 may be deposited to fill the trench 255. Next, a polishing process (e.g., conventional CMP) may be performed to remove the cladding material 1101 from above the top surface 282 of the substrate 201. The cladding material 1101 may be further recessed into the trench 255 to the desired depth (see process step 516 and...). Figure 12 The recess in the coating material 1101 at process step 516 results in the formation of a lower coating layer 251l covering the bottom surface of the trench 255. In some embodiments, the coating material 1101 may be recessed such that the thickness of the lower coating layer is at least 20 μm. Subsequently, the core material 1301 may be deposited on the partially completed structure to completely fill the upper portion of the trench 255 (see process step 518 and...). Figure 13Then a polishing process (e.g., a conventional CMP process) can be performed to remove the core material 1301 from above the top surface 282 of the substrate 201, leaving it within the upper part of the trench 255 (see process step 520 and...). Figure 14 Next, the core material 1301 within the upper portion of the trench 255 can be patterned (e.g., using conventional photolithography patterning and selective etching processes) such that the core layer 252 for the first waveguide 250 remains substantially centered on the lower cladding layer 251l (see process steps 522 and...). Figure 15 As shown in the figure, after process step 522, the outer edge of the lower overlay layer 251l will extend laterally beyond the sidewall of the core layer 252, and the sidewall of the core layer 252 will be physically separated from the sidewall of the trench 255 by a gap. In some embodiments, the core material 1301 may be patterned such that the resulting sidewall of the core layer 252 is separated from the sidewall of the trench 255 by at least 20 μm. An additional overlay material 1601 may then be deposited to fill the gap between the sidewall of the core layer 252 and the sidewall of the trench 255 (see process step 524 and...). Figure 16 After depositing the additional coating material 1601, another polishing (e.g., conventional CMP) process may be performed to remove the additional coating material 1601 from above the top surface 282 of the substrate 201 (see process step 526 and...). Figure 17 The CMP process forms an upper coating layer 251u, which is located above and adjacent to the outer edge of the lower coating layer 251l, and extends upward along the sidewall of the trench 255, so that it is further laterally positioned between and adjacent to the sidewall of the trench 255 and the side of the core layer 252. A multilayer coating layer 251 is produced using process flow B.

[0106] Process B can also be used to simultaneously form an insulating region 260 within the additional trench 265. In this case, both the overlay material 1101 and the additional overlay material 1601 should be suitable insulating materials. In process B, the overlay material 1101 can be deposited at process step 514 to simultaneously fill both the trench 255 and the additional trench 265. Optionally, to protect the overlay material 1101 within the additional trench 265 during subsequent processing (e.g., during the recess of the overlay material 1101 in process step 516), a protective mask 1201 can be formed thereon (see...). Figure 12 After the cladding material 1101 is recessed in process step 516, the protective mask 1201 can be removed. In process step 522, the etching of the core material 1301 can be selective, minimizing the etching of the cladding material 1101 within the additional trench 265. If necessary, depositing additional cladding material 1601 at process step 524 can refill the additional trench 265. The CMP process at process step 526 can result in the completion of the insulating region 260 within the additional trench 265.

[0107] In process flow A or process flow B, the cladding material of the first waveguide 250 may have a first refractive index, and the core material of the first waveguide 250 may have a second refractive index greater than the first refractive index to allow optical signals to propagate through the waveguide 250. In some embodiments, the cladding material may be an oxide material with a refractive index less than 2.0 and more specifically less than 1.6, such as silicon dioxide. In other embodiments, the cladding material may be a different oxide material or some other suitable cladding material with a similarly low refractive index, particularly having a first refractive index less than the second refractive index of the core material. It should be noted that in process flow B, the cladding material 1101 and the additional cladding material 1601 may be the same or different, such that the lower cladding layer 251l and the upper cladding layer 251u are the same or different. In any case, the refractive index of the cladding material 1101 and the additional cladding material 1601 should be less than the refractive index of the core material. In some embodiments, the core material may be a nitride material with a refractive index greater than 2.0, such as silicon nitride (SiN). In other embodiments, the core material may be an oxide material, different from the material used for the coating material, and similarly has a relatively high refractive index. For example, in some embodiments, the core material may be niobium oxide (NbO) with a refractive index of about 2.2 or higher. In other embodiments, the core material may be any other suitable core material with a similarly high refractive index, particularly a second refractive index greater than the first refractive index of the coating material.

[0108] about Figure 17 The partially completed structure is shown; the remaining process steps are illustrated in the accompanying drawings. However, it should be understood that alternative approaches can also be used for... Figure 10 The partially completed structure shown in the diagram performs these same process steps.

[0109] Specifically, the method may further include forming an insulating layer 202 on the top surface 282 of the substrate 201, such that it covers any embedded structures therein, including the first waveguide 250 and the insulating region 260 (see process step 528 and...). Figure 18 The insulating layer 202 may be, for example, a silicon dioxide layer (also referred to herein as a buried oxide (BOX) layer). The deposition thickness of the insulating layer 202 can vary depending on the application and technology node. For example, the insulating layer 202 can be deposited to have a thickness from less than 100 nm to 0.5 μm or higher (e.g., approximately 2 μm). It should be noted that by locally forming a substrate embedded insulating region, the need to deposit a thick insulating layer 202 (i.e., a thick BOX layer) in some technologies can be eliminated.

[0110] The method may further include forming a silicon layer 206 (particularly a monocrystalline silicon layer) on the insulating layer 202 to form an SOI structure (see process step 530 and...). Figure 19 The silicon layer 206 can be formed using conventional wafer bonding processes. For example, an additional silicon substrate can be bonded to the top surface of the insulating layer 202 (e.g., using smart dicing or other suitable wafer bonding processes). Polishing processes (e.g., conventional CMP processes) or other suitable processes can then be used to reduce the silicon layer 206 to the desired thickness. As described above, regarding SOI chip structures, in some embodiments, the Si layer 106 can be thinner in the electronic device region 220 than in the optical device region 210. For example, in some embodiments, the thickness of the silicon layer 206 in the electronic device region 220 can be between 50 nm and 100 nm (e.g., approximately 88 nm), and the thickness of the silicon layer 206 in the optical device region 210 can be between 125 nm and 175 nm (e.g., approximately 150 nm or 160 nm). Various techniques for changing the thickness of a layer in one region relative to another are well known in the art; therefore, details of these techniques are omitted from this specification to allow the reader to focus on the significant aspects of the disclosed methods.

[0111] The method may also include forming an isolation region within the Si layer 206, particularly a shallow trench isolation (STI) region 205 (see...). Figure 20 For example, shallow trenches can be formed (e.g., using conventional photolithography patterning and etching techniques) extending completely through the Si layer 206 to the insulating layer 202. Each shallow trench can be filled with one or more layers of insulating material. The insulating material for the STI region 205 can be silicon dioxide or any other suitable insulating material. It should be noted that if the Si layer 206 is thicker within the optical device region 210 than within the electronic device region 220, the STI region 205 within the optical device region 210 will also be thicker. Alternatively, the thickness of the STI and Si in the electronic device region can be reduced after the STI is formed. In any case, the STI regions 205 can be patterned within and between the individual device regions in the silicon layers so that they define the boundaries of the device regions and so that they insulate the device as needed. An STI region 205 can specifically be located within the Si layer 206 in the optical device region 210 and aligned above the first waveguide 250. The STI region 205 and the insulating layer 202 can provide additional cladding for the first waveguide 250.

[0112] Optionally, the method may further include forming a waveguide extension 253 to enhance the coupling between the first waveguide 250 and the second waveguide, which will subsequently be formed in process step 540 discussed below (see [link to documentation]). Figure 21Specifically, an opening can be formed (e.g., photolithographic patterning and etching) such that the opening extends vertically through the STI region 205 and the insulating layer 202, exposing the top of the core layer 252 of the first waveguide 250. For example, the opening can be filled using the same core material as the core layer 252 of the first waveguide 250 or the same core material used for the core layer of the second waveguide, thereby forming the waveguide extension 253. Alternatively, the opening may extend only to a certain depth above the level of the core layer 252, but close enough to enable evanescent wave coupling with the waveguide extension 253 formed therein.

[0113] The method may further include performing a front-end process (FEOL) to form any one or more of one or more additional optical devices in the optical device region 210 and / or one or more electronic devices in the electronic device region 220 (see process step 540 and...). Figures 2A to 2C , Figures 3A to 3B , Figure 4 Exemplary FEOL electronic devices that may be formed at process step 540 may include active semiconductor devices and / or passive semiconductor devices. Active semiconductor devices may include, for example, complementary metal-oxide-semiconductor (CMOS) devices (e.g., one or more field-effect transistors (FETs) 222 as shown) or any other suitable type of active semiconductor device. Passive semiconductor devices may include resistors, capacitors, etc. Exemplary FEOL optical devices that may be incorporated into SOI chip structures 200.1-200.3 include any of the following: one or more second waveguides 214a-214b (e.g., SiN waveguides), one or more third waveguides 213 (e.g., Si waveguides), one or more photodetectors 212 (e.g., germanium photodetectors), and / or any other suitable FEOL optical devices. Techniques for forming such FEOL electronic and optical devices are well known in the art; therefore, details thereof are omitted in this specification to allow the reader to focus on the significant aspects of the disclosed embodiments.

[0114] After the FEOL process is completed, one or more layers of interlayer dielectric (ILD) material 204 can be formed on the partially completed structure, and a polishing process (e.g., conventional CMP process) can be performed. The ILD material 204 can be, for example, doped silicon glass (e.g., phosphosilicate glass (PSG) or borosilicate glass (BPSG)), silicon dioxide, or any other suitable ILD material. In any case, the ILD material 204 should have a relatively low refractive index (e.g., below 2.0) to allow it to be used as a cladding material for the second waveguides 214a-214b. The method may also include forming mid-section process (MOL) contacts 289. These MOL contacts 289 can extend vertically through the ILD material 204 to optical and electronic devices as needed. For example, the MOL contacts 289 can land on terminals of photodetectors 212, FETs 222, etc.

[0115] It should be noted that in the described method, the maximum height of the core layer of the third waveguide 213 (e.g., a Si optical waveguide) will be limited by a critical dimension (CD) associated with the Si layer 206. Specifically, the maximum height of the core layer of the third waveguide 213 will be limited by the maximum permissible height of the Si layer 206 within the optical device region 210. Furthermore, the maximum height of the core layers of each of the second waveguides 214a-214b will be limited, at least partially, by a critical dimension (CD) associated with the MOL contact 289. Specifically, one of the CDs in the MOL contact 289 is a maximum permissible height, which is configured to minimize the resistance of the contact 289. Because the MOL contact 289 has a maximum height, because the MOL contact and the ILD material 204 through which those MOL contacts extend have coplanar top surfaces, and because the core layer of each second waveguide 214a-214b is embedded within the ILD material 204, the maximum height of the core layer of each second waveguide 214a-214b may not exceed the height of the ILD material 204 above the top of the Si layer 206 within the optical device region 210. For example, in some embodiments, the maximum height of the core layer of each second waveguide 214a-214b (e.g., each SiN waveguide) above the STI region 205 may be 300 nm. Since the size of the core layer of the waveguide determines the characteristics of these waveguides, including the cutoff wavelength (i.e., the maximum wavelength of any optical signal that can be propagated by the waveguide), the aforementioned limitation on the size of the core layers of the second waveguides 214a-214b and the third waveguide 213 also limits their functionality. However, since the first waveguide 250 is embedded within the substrate 201, it is not limited by the cutoff wavelength (CD) associated with front-end process (FEOL) or mid-end process (MOL) characteristics. Therefore, a core layer 252 of the first waveguide 250 can be formed such that its size (measured in tens or hundreds of micrometers (μm) depending on the final thickness of the substrate 201) is significantly larger than the size (typically measured in hundreds of nanometers (nm)) of any core layer of the second waveguides 214a-214b and / or the third waveguide 213. Thus, this method can produce an SOI chip structure with multiple waveguides (e.g., the first waveguide 250, the second waveguides 214a-214b, and the third waveguide 213), and the first waveguide 250 can have a cutoff wavelength significantly higher than any of the second waveguides 214a-214b or the third waveguide 213, thus giving the SOI chip structure different functionality compared to the second and third waveguides.

[0116] It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not restrictive. For example, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, as used herein, the terms “comprising,” “including,” “containing,” and / or “comprises” specify the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. Additionally, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “below,” “under,” “above,” “parallel,” and “upright” are used to describe the relative positions shown in the accompanying drawings (unless otherwise stated), and terms such as “contact,” “direct contact,” “adjacent,” “directly adjacent,” and “directly adjacent” are used to indicate that at least one element is in physical contact with another element (without any other element separating the elements). The term "lateral" is used herein to describe the relative position of elements, and more specifically, to indicate that an element is positioned above or below another element to the side of that element, as these elements are oriented and shown in the accompanying drawings. For example, an element laterally adjacent to another element will be located next to that element, an element laterally adjacent to another element will be located directly next to that element, and an element laterally surrounding another element will be adjacent to and abut against the outer side wall of that element. The corresponding structures, materials, actions, and equivalents of all means or steps plus functional elements in the appended claims are intended to include any structures, materials, or actions used to perform a function in combination with elements of the other specifically claimed claims.

[0117] The description of various embodiments of the present invention is given for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application or improvement relative to technology found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A silicon-on-insulator (SiI) chip structure, comprising: substrate; A first waveguide, located in a trench of the substrate, wherein the first waveguide comprises: A covering layer lining the trench, wherein the covering layer has a horizontal portion located above and immediately adjacent to the bottom of the trench, and a vertical portion located laterally adjacent to the sidewalls of the trench and extending vertically from the horizontal portion to the top of the trench; and A core layer is located on the covering layer, wherein the core layer is located above and adjacent to the horizontal portion, extends laterally between and adjacent to the vertical portions, and further extends vertically from the horizontal portion to the top of the trench. An insulating layer, located above and adjacent to the substrate and extending laterally beyond at least the vertical portion of the covering layer at the top of the trench; and A silicon layer, which is located above and adjacent to the insulating layer.

2. The silicon-on-insulator (SCI) chip structure according to claim 1, in, The substrate includes silicon. The cladding layer of the first waveguide includes an oxide cladding layer, and The core layer of the first waveguide includes either a silicon nitride core layer or an oxide core layer, which are different from the oxide cladding layer.

3. The silicon-on-insulator chip structure according to claim 1, wherein, The covering layer includes a multilayer covering layer having a lower covering layer and an upper covering layer, the lower covering layer including the horizontal portion and on the bottom of the trench, and the upper covering layer including the vertical portion and above the lower covering layer and laterally adjacent to the sidewall of the trench.

4. The silicon-on-insulator (SiI) chip structure according to claim 1, further comprising: An insulating region located in the silicon layer above the first waveguide; as well as At least one second waveguide is located above the insulating region.

5. The silicon-on-insulator chip structure according to claim 4, wherein, The core layer of the second waveguide covers the core layer of the first waveguide.

6. The silicon-on-insulator (SiI) chip structure according to claim 5, further comprising: A waveguide extension extending through the insulating region and the insulating layer, wherein the core layer of the first waveguide and the core layer of the second waveguide are in contact with the waveguide extension.

7. The silicon-on-insulator chip structure according to claim 4, wherein, The core layer of the second waveguide is completely offset from the core layer of the first waveguide.

8. The silicon-on-insulator chip structure according to claim 4, wherein, The core layer of the second waveguide is smaller than the core layer of the first waveguide.

9. The silicon-on-insulator (SiI) chip structure according to claim 4, further comprising: The third waveguide, wherein the core layer of the third waveguide includes a portion of the silicon layer.

10. The silicon-on-insulator (SiI) chip structure according to claim 1, further comprising: Additional optical devices, including a portion of the silicon layer.

11. The silicon-on-insulator (SiI) chip structure according to claim 1, further comprising: Electronic devices that include a portion of the silicon layer.

12. The silicon-on-insulator (SCI) chip structure according to claim 1, in, The substrate has additional trenches. The structure also includes an insulating area in the additional trench, and The insulating layer also extends laterally over the insulating area.

13. A method for forming a silicon-on-insulator (SCI) chip structure, the method comprising: Provide substrate; Forming trenches in the substrate; A first waveguide is formed in the trench, wherein the first waveguide includes: A covering layer lining the trench, wherein the covering layer has a horizontal portion located above and immediately adjacent to the bottom of the trench, and a vertical portion located laterally adjacent to the sidewalls of the trench and extending vertically from the horizontal portion to the top of the trench; and A core layer is located on the covering layer, wherein the core layer is located above and adjacent to the horizontal portion, extends laterally between and adjacent to the vertical portions, and further extends vertically from the horizontal portion to the top of the trench. An insulating layer is formed above the substrate and adjacent to the substrate, extending laterally to at least the vertical portion of the covering layer at the top of the trench; and A silicon layer is formed above and adjacent to the insulating layer.

14. The method according to claim 13, wherein, The formation of this first waveguide includes: Depositing a coating material to line the trench; and Deposit core material onto the cladding layer to fill the trench.

15. The method according to claim 13, wherein, The formation of this first waveguide includes: Deposit coating material to fill the trench; The cladding material is recessed to leave a lower cladding layer for the first waveguide at the bottom of the trench; Deposit core material onto the lower cladding layer to fill the trench; Patterning the core material within the trench to form the core layer of the first waveguide, and separating the core layer from the sidewalls of the trench; and Additional coating material is deposited to fill the gap between the core layer and the sidewall of the trench, forming an upper coating layer above the lower coating layer.

16. The method of claim 13, further comprising: During the formation of this trench, additional trenches are simultaneously formed in the substrate; as well as The additional trench is filled with an insulating material to form an insulating region, wherein the insulating material of the insulating region and the cladding material used for the first waveguide are the same material, and wherein the insulating layer is deposited on the substrate to cover both the first waveguide and the insulating region.

17. The method of claim 13, further comprising: An insulating region is formed in the silicon layer; as well as A second waveguide is formed above the insulating region, wherein the size of the core layer of the second waveguide is smaller than the size of the core layer of the first waveguide.

18. The method of claim 17, further comprising: A waveguide extension is formed extending through the insulating region and the insulating layer, wherein the second waveguide is formed after the waveguide extension such that the core layer of the second waveguide contacts the waveguide extension.

19. The method of claim 17, further comprising using the silicon layer to form at least one of a third waveguide, an additional optical device, and an electronic device.

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