Duty cycle calibration circuit and method, chip and electronic device

Abstract

The duty cycle calibration circuit and method, chip and electronic equipment, the duty cycle calibration circuit obtains the number of counting pulses generated in the high level state and low level state of the correction clock signal in the pre-design counting period by using the counting clock signal with higher frequency than the correction clock signal through the counting unit, thereby obtaining the actual duty cycle of the correction clock signal. Compared with the method of obtaining the duty cycle of the correction clock signal by comparing the correction clock signal with the reference clock signal, the problem of inaccurate detection of the duty cycle of the correction clock signal caused by the influence of the reference clock signal can be overcome, so that the accuracy of the duty cycle detection can be improved, and the precision of the duty cycle calibration can be improved.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, specifically to a duty cycle calibration circuit and method, chip, and electronic device. Background Technology

[0002] The concept of duty cycle applies only to periodic signals. The duty cycle of a periodic signal is the ratio between the duration of its high-level state and the length of the clock cycle. For example, a 50% duty cycle means that the signal is high for half of the time in one clock cycle.

[0003] Duty cycle calibration is of great value in many high-performance circuit applications, including dynamic logic circuits, analog circuits, arrays, etc., and is especially important in clock source circuits.

[0004] Therefore, how to accurately calibrate the duty cycle of the clock signal has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a duty cycle calibration circuit and method, chip and electronic device to improve the accuracy of duty cycle calibration.

[0006] To achieve the above objectives, embodiments of the present invention provide a duty cycle calibration circuit, comprising:

[0007] A counting unit is adapted to receive a correction clock signal; acquire the number of counting pulses generated in the high-level and low-level states of the correction clock signal within a preset counting period; and the frequency of the counting clock signal that generates the counting pulses is higher than the frequency of the correction clock signal.

[0008] The control unit is adapted to receive the number of counting pulses generated in the high-level and low-level states of the correction clock signal within the preset counting period; obtain the current duty cycle information of the correction clock signal based on the number of counting pulses generated in the high-level and low-level states of the correction clock signal within the preset counting period; compare the current duty cycle of the correction clock signal with a preset target duty cycle; and generate a corresponding control signal based on the comparison result between the duty cycle of the correction clock signal and the target duty cycle.

[0009] The duty cycle adjustment unit is adapted to receive the control signal and the input clock signal; adjust the duty cycle of the input clock signal according to the received control signal to obtain the corresponding correction clock signal until the duty cycle of the generated correction clock signal reaches the target duty cycle.

[0010] Accordingly, embodiments of the present invention also provide a chip including a duty cycle calibration circuit as described in any of the preceding claims.

[0011] Accordingly, embodiments of the present invention also provide an electronic device, including the chip as described above.

[0012] Accordingly, embodiments of the present invention also provide a duty cycle calibration method, comprising:

[0013] The number of counting pulses generated during the high-level and low-level states of the correction clock signal within a preset counting period is obtained; the frequency of generating the counting pulses is higher than the frequency of the correction clock signal.

[0014] The current duty cycle information of the correction clock signal is obtained based on the number of counting pulses generated in the high-level and low-level states of the correction clock signal within a preset counting period.

[0015] The current duty cycle of the correction clock signal is compared with the preset target duty cycle;

[0016] Based on the comparison between the current duty cycle of the correction clock signal and the target duty cycle, a corresponding control signal is generated;

[0017] The duty cycle of the input clock signal is adjusted according to the control signal until the duty cycle of the generated correction clock signal reaches the target duty cycle.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0019] The duty cycle calibration circuit provided in this embodiment of the invention obtains the number of high-level and low-level states of the calibration clock signal within a preset counting period by using a counting clock signal with a clock signal frequency higher than that of the calibration clock signal through a counting unit. This allows the actual duty cycle of the calibration clock signal to be obtained. Compared with the method of comparing the calibration clock signal with a reference clock signal to obtain the duty cycle of the calibration clock signal, this method can overcome the problem of inaccurate duty cycle detection of the calibration clock signal caused by the influence of the reference clock signal. Therefore, it can improve the accuracy of duty cycle detection and thus improve the accuracy of duty cycle calibration. Attached Figure Description

[0020] Figure 1 A schematic diagram of a duty cycle calibration circuit according to an embodiment of the present invention is shown;

[0021] Figure 2 A schematic diagram of the structure of a counting unit in an embodiment of the present invention is shown;

[0022] Figure 3 This is a schematic diagram of the structure of a duty cycle adjustment unit in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of the structure of a duty cycle shaping module in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of the structure of a delay submodule in an embodiment of the present invention;

[0025] Figure 6 This is a pulse timing diagram of the relevant signals of a duty cycle calibration circuit in an embodiment of the present invention;

[0026] Figure 7 This is a schematic flowchart of a duty cycle calibration method according to an embodiment of the present invention. Detailed Implementation

[0027] Existing duty cycle calibration circuits suffer from inaccurate duty cycle detection, resulting in low accuracy of duty cycle calibration.

[0028] Specifically, the calibration clock signal is compared with a preset reference clock signal to obtain the duty cycle detection information of the calibration clock signal. However, when the reference clock signal is affected, the duty cycle detection of the calibration clock signal will be inaccurate, thus affecting the accuracy of the duty cycle calibration.

[0029] To address the aforementioned problems, this invention provides a duty cycle calibration circuit, comprising: a counting unit adapted to receive a calibration clock signal; acquiring the number of counting pulses generated in the high-level and low-level states of the calibration clock signal within a preset counting period; wherein the frequency of the counting clock signal generating the counting pulses is higher than the frequency of the calibration clock signal; a control unit adapted to receive the number of counting pulses generated in the high-level and low-level states of the calibration clock signal within the preset counting period; acquiring the current duty cycle information of the calibration clock signal based on the number of counting pulses generated in the high-level and low-level states of the calibration clock signal within the preset counting period; comparing the current duty cycle of the calibration clock signal with a preset target duty cycle; generating a corresponding control signal based on the comparison result between the current duty cycle of the calibration clock signal and the target duty cycle; and a duty cycle adjustment unit adapted to receive the control signal and an input clock signal; adjusting the duty cycle of the input clock signal according to the control signal to acquire the calibration clock signal until the duty cycle of the calibration clock signal reaches the target duty cycle.

[0030] The duty cycle calibration circuit provided in this embodiment of the invention obtains the actual duty cycle of the calibration clock signal by using a counting clock signal with a clock signal frequency higher than that of the calibration clock signal within a preset counting period, which employs a counting clock unit to acquire the number of counting pulses generated in the high-level and low-level states of the calibration clock signal. Compared with the method of comparing the calibration clock signal with a reference clock signal to obtain the duty cycle of the calibration clock signal, this method can overcome the problem of inaccurate duty cycle detection of the calibration clock signal caused by the influence of the reference clock signal, thus improving the accuracy of duty cycle detection and consequently improving the precision of duty cycle calibration.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 A schematic diagram of a duty cycle calibration circuit according to an embodiment of the present invention is shown. See also Figure 1 A duty cycle calibration circuit in an embodiment of the present invention may include a counting unit 10, a control unit 20, and a duty cycle adjustment unit 30. The counting unit 10 is coupled to the control unit 20, and the control unit 20 is also coupled to the duty cycle adjustment unit 30.

[0033] The counting unit 10 has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the counting unit 10 is coupled to the duty cycle adjustment unit 30. The second input terminal of the counting unit 10 is used to receive a preset counting clock signal. The first and second output terminals of the counting unit 10 are respectively coupled to the control unit 20. The counting unit 10 is used to receive the correction clock signal output by the duty cycle adjustment unit 30 and to obtain the number of counting pulses generated in the high-level and low-level states of the correction clock signal within a preset counting period. The frequency at which the counting clock signal generates the counting pulses is higher than the frequency of the correction clock signal.

[0034] Figure 2 A schematic diagram of the structure of a counting unit according to an embodiment of the present invention is shown. Figure 2 As shown, the counting unit includes a first counting module 110 and a second counting module 120.

[0035] The first counting module 110 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first counting module 110 serves as the first input terminal of the counting unit or is coupled to the first input terminal of the counting unit, and is used to receive the correction clock signal CLK. cal The second input terminal of the counting module 110 serves as the second input terminal of the counting unit or is coupled to the second input terminal of the counting unit, and is used to receive the counting clock signal CLK.cnt The first counting module 110 is used to obtain the first number of counting pulses generated during the high-level state of the correction clock signal within the preset counting period.

[0036] In this embodiment, the first counting module 110 includes a first OR gate 111, a first AND gate 112, and a first counter 113. The first input terminal of the first OR gate 111 serves as the first input terminal of the first counting module 110 or is coupled to the first input terminal of the first counting module 110, and is used to receive the correction clock signal CLK. cal The second input terminal of the first OR gate 111 serves as the second input terminal of the first counting module 110 or is coupled to the second input terminal of the first counting module 110, and is used to receive the counting clock signal CLK. cnt The output of the first OR gate 111 is coupled to the first input of the first AND gate 112; the second input of the first AND gate 112 is used to receive the first counting control signal CNT_1, and the output of the first AND gate 112 is coupled to the input of the first counter 113; the output of the first counter 113 serves as the output of the first counting module 110 or is coupled to the output of the first counting module 110. The first counting control signal CNT_1 is high during the preset counting period.

[0037] The second counting module 120 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second counting module 120 serves as the first input terminal of the counting unit or is coupled to the first input terminal of the counting unit, and is used to receive the correction clock signal CLK. cal The second input terminal of the second counting module 120 serves as the second input terminal of the counting unit or is coupled to the second input terminal of the counting unit, and is used to receive the counting clock signal CLK. cnt The output terminal of the second counting module 120 serves as the second output terminal of the counting unit or is coupled to the second output terminal of the counting unit. The second counting module 120 is used to obtain the second number of counting pulses generated during the low-level state of the correction clock signal within the preset counting period.

[0038] In this embodiment, the second counting module 120 includes a second AND gate 121, a second OR gate 122, and a second counter 123. The first input terminal of the second AND gate 121 serves as the first input terminal of the second counting module 120 or is coupled to the first input terminal of the second counting module 120, and is used to receive the correction clock signal CLK. cal The second input terminal of the second AND gate 121 serves as the second input terminal of the second counting module 120 or is coupled to the second input terminal of the second counting module 120, and is used to receive the counting clock signal CLK. cntThe output of the second AND gate 121 is coupled to the first input of the second OR gate 122; the second input of the second OR gate 122 is used to receive the second counting control signal CNT_2; the output of the second AND gate 122 is coupled to the input of the second counter 123; the output of the second counter 123 serves as the output of the second counting module 120 or is coupled to the output of the second counting module 120. The second counting control signal CNT_2 is low during the preset counting period.

[0039] Please continue reading Figure 1 The control unit 20 has a first input terminal, a second input terminal, and an output terminal. The first and second input terminals of the control unit 20 are coupled to the counting unit 10, and the output terminal of the control unit 20 is coupled to the duty cycle adjustment unit 30. The control unit 20 is used to receive the number of counting pulses generated during the high and low states of the correction clock signal within a preset counting period; to obtain the current duty cycle information of the correction clock signal based on the number of counting pulses generated during the high and low states of the correction clock signal within the preset counting period; to compare the current duty cycle of the correction clock signal with a preset target duty cycle; and to generate a corresponding control signal based on the comparison result between the current duty cycle of the correction clock signal and the target duty cycle.

[0040] The duty cycle adjustment unit 30 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the duty cycle adjustment unit 30 is coupled to the control unit 20, the second input terminal of the duty cycle adjustment unit 30 is used to receive the input clock signal, and the output terminal of the duty cycle adjustment unit 30 is coupled to the counting unit 10. The duty cycle adjustment unit 30 is used to receive the control signal and the input clock signal; adjust the duty cycle of the input clock signal according to the received control signal to obtain the correction clock signal until the duty cycle of the correction clock signal reaches the target duty cycle.

[0041] Specifically, the control unit 20 includes a finite state machine. The finite state machine has a preset number of states, which can be switched between to output different control signals to the duty cycle adjustment unit 30, so that the duty cycle adjustment unit 30 can adjust the duty cycle of the input clock signal accordingly based on the control signals.

[0042] In this embodiment, the finite state machine uses boost control signals and buck control signals to control the duty cycle of the correction clock signal. Specifically, the finite state machine generates a corresponding boost control signal when it determines that the current duty cycle of the correction clock signal is lower than the target duty cycle; and generates a corresponding buck control signal when it determines that the duty cycle of the correction clock signal is higher than the target duty cycle.

[0043] Accordingly, the duty cycle adjustment unit 30 is used to generate multiple levels of adjustment voltage; when receiving the boost control signal, it adjusts the duty cycle of the input clock signal using the next level adjustment voltage which is higher than the current level adjustment voltage; when receiving the buck control signal, it adjusts the duty cycle of the input clock signal using the next level adjustment voltage which is lower than the current level adjustment voltage.

[0044] Figure 3 A schematic diagram of a duty cycle adjustment unit according to an embodiment of the present invention is shown. See also Figure 3 An embodiment of the present invention provides a duty cycle adjustment unit including a voltage adjustment module 310 and a duty cycle shaping module 320. The voltage adjustment module 310 and the duty cycle shaping module 320 are coupled to each other.

[0045] The voltage adjustment module 310 has an input terminal and an output terminal. The input terminal of the voltage adjustment module 310 serves as the first input terminal of the duty cycle adjustment unit or is coupled to the first input terminal of the duty cycle adjustment unit. The output terminal of the voltage adjustment module 310 is coupled to the duty cycle shaping module 320. The voltage adjustment module 310 is used to divide a preset first power supply voltage using multiple series-connected voltage divider resistors to generate multiple adjustable voltage levels. When receiving the boost control signal, it selects and outputs the next adjustable voltage level that is higher than the current adjustable voltage level; when receiving the buck control signal, it selects and outputs the next adjustable voltage level that is lower than the current adjustable voltage level.

[0046] Specifically, the regulating voltage providing module 310 includes a regulating voltage generating submodule 311 and a selection output submodule 312. The regulating voltage generating submodule 311 and the selection output submodule 312 are coupled to each other.

[0047] The adjustable voltage generation submodule 311 has an input terminal and N output terminals. The input terminal of the adjustable voltage generation submodule 311 is used to receive the first power supply voltage VDD1, and the N output terminals of the adjustable voltage generation submodule 311 are respectively coupled to the selection output submodule 312. The adjustable voltage generation submodule 311 can use multiple series-connected voltage divider resistors to divide the preset first power supply voltage, generate multiple adjustable voltage levels, and output them.

[0048] Specifically, the voltage generation submodule 311 includes a current source I1 and N series-connected voltage divider resistors R. t1 ~R tN (N is an integer greater than 1). The first terminal of current source I1 receives the first power supply voltage VDD1, and the second terminal of current source I1 is connected through N series-connected voltage divider resistors R. t1 ~R tN Grounding.

[0049] It should be noted that the N output terminals of the voltage generation submodule 311 are respectively connected to N voltage divider resistors R. t1 ~R tN A one-to-one correspondence is set. Specifically, there are N voltage divider resistors R t1 ~R tN The first terminal is respectively used as one of the N output terminals of the regulating voltage generation submodule 311 or respectively coupled to the N output terminals of the regulating voltage generation submodule 311. Specifically, the voltage divider resistor R t1 The first terminal serves as the first output terminal of the regulating voltage generation submodule 311 or is coupled to the first output terminal of the regulating voltage generation submodule 311, and the voltage divider resistor R t2 The first terminal serves as the second output terminal of the voltage regulation generation submodule 311 or is coupled to the second output terminal of the voltage regulation generation submodule 311, ..., voltage divider resistor R tN The first end is either used as the Nth output terminal of the regulating voltage generation submodule 311 or coupled to the Nth output terminal of the regulating voltage generation submodule 311.

[0050] Accordingly, the selection output submodule 312 has N input terminals, a control terminal, and an output terminal. The N input terminals of the selection output submodule 312 are respectively used to receive the N adjustable voltage levels output by the adjustable voltage generation submodule 311. The control terminal of the selection output submodule 312 serves as an input terminal of the adjustable voltage supply module 310 or is coupled to an input terminal of the adjustable voltage supply module 310. The output terminal of the selection output submodule 312 serves as an output terminal of the adjustable voltage supply module 310 or is coupled to an output terminal of the adjustable voltage supply module 310. The selection output submodule 312 is used to receive the boost control signal Ctrl. inc When the voltage is higher than the current voltage setting, select and output the next voltage setting; upon receiving the step-down control signal Ctrl... dec When the voltage is lower than the current voltage setting, select the next voltage setting and output it.

[0051] In this embodiment, the selection output submodule 312 includes a multiplexer (MUX). The multiplexer has N input terminals and N output terminals, which serve as the N input terminals and N output terminals of the selection output submodule 312, respectively. In other embodiments, the selection output submodule can also be implemented using other functions with the same structure, which are not limited here.

[0052] The duty cycle shaping module 320 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the duty cycle shaping module 320 serves as the second input terminal of the duty cycle adjustment unit or is coupled to the second input terminal of the duty cycle adjustment unit. The second input terminal of the duty cycle shaping module 320 is coupled to the output terminal of the regulating voltage providing module 310. The output terminal of the duty cycle shaping module 320 serves as the output terminal of the duty cycle adjustment unit or is coupled to the output terminal of the duty cycle adjustment unit. The duty cycle shaping module 320 is used to receive a corresponding level regulating voltage; and uses the received corresponding level regulating voltage to adjust the duty cycle of the input clock signal to obtain the corrected clock signal.

[0053] Please continue reading Figure 3 In this embodiment, the duty cycle shaping module 320 includes a first inverter 321 and a second inverter 322. The first inverter 321 and the second inverter 322 are coupled to each other.

[0054] The first inverter 321 includes a first PMOS transistor P1 and a first NMOS transistor N1. The gate of the first PMOS transistor P1 is coupled to the gate of the first NMOS transistor N1 and serves as or is coupled to the first input terminal of the duty cycle shaping module 320. The source of the first PMOS transistor P1 receives the second power supply voltage VDD2. The drain of the first PMOS transistor P1 is coupled to the drain of the first NMOS transistor N1 and serves as or is coupled to the output terminal of the first inverter 321. The source of the first NMOS transistor N1 is grounded. The first inverter 321 is used to adjust the ratio of the conduction time of the first PMOS transistor P1 and the first NMOS transistor N1 using a corresponding voltage adjustment level, thereby controlling the input clock signal CLK. in The duty cycle is adjusted, and the input clock signal CLK is adjusted accordingly. in Perform inversion processing to obtain the inverted clock signal.

[0055] The second inverter 322 includes a second PMOS transistor P2 and a second NMOS transistor N2. The gate of the second PMOS transistor P2 is coupled to the gate of the second NMOS transistor N2 and serves as or is coupled to the input of the second inverter 322. The source of the second PMOS transistor P2 receives the second power supply voltage VDD2. The drain of the second PMOS transistor P2 is coupled to the drain of the second NMOS transistor N2 and serves as or is coupled to the output of the duty cycle shaping module. The source of the second NMOS transistor N2 is grounded. The second inverter 322 buffers and inverts the inverted clock signal output from the first inverter 321 to generate the correction clock signal CLK. cal .

[0056] In this embodiment, the duty cycle shaping module 320 further includes a bias voltage generation submodule (not shown).

[0057] The bias voltage generation submodule has an input terminal and an output terminal. The input terminal of the bias voltage generation submodule serves as the first input terminal of the duty cycle shaping module 320 or is coupled to the first input terminal of the duty cycle shaping module 320. The output terminal of the bias voltage generation submodule is coupled to the input terminal of the first inverter 321. The bias voltage generation submodule is used to receive the corresponding level adjustment voltage and perform bias processing on the corresponding level adjustment voltage to obtain the corresponding bias voltage.

[0058] In this embodiment, the bias voltage generation submodule includes a first resistor R1. The first end of the first resistor R1 serves as the input terminal of the bias voltage generation submodule or is coupled to the input terminal of the bias voltage generation submodule, and the second end of the first resistor R1 serves as the output terminal of the bias voltage generation submodule or is coupled to the output terminal of the bias voltage generation submodule.

[0059] In this embodiment, the duty cycle shaping module 320 further includes an AC coupling submodule (not shown).

[0060] The AC coupling submodule has an input terminal and an output terminal. The input terminal of the AC coupling submodule serves as the second input terminal of the duty cycle shaping module 320 or is coupled to the second input terminal of the duty cycle shaping module 320. The output terminal of the AC coupling submodule is coupled to the input terminal of the first inverter 321. The AC coupling submodule is used to process the input clock signal CLK. in DC signal isolation processing is performed.

[0061] In this embodiment, the AC coupling submodule includes a first capacitor C1. The first terminal of the first capacitor C1 serves as the input terminal of the AC coupling submodule or is coupled to the input terminal of the AC coupling submodule, for receiving the input clock signal CLK. in The second terminal of the first capacitor C1 serves as the output terminal of the AC coupling submodule or is coupled to the output terminal of the AC coupling submodule, and is coupled to the input terminal of the first inverter 321.

[0062] In other embodiments, the duty cycle shaping unit can also be implemented using other structures with the same function.

[0063] Figure 4 A schematic diagram of another duty cycle shaping module in an embodiment of the present invention is shown; Figure 5 It shows Figure 4 A schematic diagram of the delay submodule in the duty cycle shaping module of a certain embodiment is shown. See also [reference needed]. Figure 4 and Figure 5 The duty cycle shaping module includes a third inverter 421, a first selection submodule 422, a delay submodule 423, a third OR gate 424, and a second selection submodule 425.

[0064] The third inverter 421 has an input terminal and an output terminal. The input terminal of the third inverter 421 is coupled as the second input terminal of the duty cycle shaping module or the second input terminal of the duty cycle shaping module, and is used to receive the input clock signal CLK. in The output of the third inverter 421 is coupled to the first input of the first selection submodule 422. The third inverter 421 is used to receive the input clock signal CLK. in and the input clock signal CLK in The input inverted clock signal is obtained by performing inversion processing.

[0065] The first selection submodule 422 has a first input terminal, a second input terminal, a selection control terminal, and an output terminal. The first input terminal of the first selection submodule 422 serves as the first input terminal of the duty cycle shaping module or is coupled to the first input terminal of the duty cycle shaping module, and is used to receive the input clock signal CLK. in The second input terminal of the first selection submodule 422 is coupled to the output terminal of the third inverter 421. The selection control terminal of the first selection submodule 422 is used to receive the first selection control signal SELECT1. The output terminal of the first selection submodule 422 is coupled to the delay submodule 423, the third OR gate 424, and the second selection submodule 425, respectively. The first selection submodule 422 is used to receive the first selection control signal SELECT1 and select the input clock signal CLK according to the first selection control signal SELECT1.in Alternatively, the input inverted clock signal can be used as the selection clock signal. Specifically, when the duty cycle of the correction clock signal is higher than the target duty cycle, the first selection control signal SELECT1 is logic 1; when the duty cycle of the correction clock signal is lower than the target duty cycle, the first selection control signal SELECT1 is logic 0.

[0066] As an example, the first selection submodule 422 is a multiplexer. In other embodiments, the first selection submodule 422 can also be other structures with the same function, which are not limited here.

[0067] The delay submodule 423 has an input terminal, a control terminal, and an output terminal. The input terminal of the delay submodule 423 is coupled to the first selection submodule 422. The control terminal of the delay submodule 423 serves as the first input terminal of the duty cycle shaping module or is coupled to the first input terminal of the duty cycle shaping module. The output terminal of the delay submodule 423 is coupled to the first input terminal of the third OR gate 424. The delay submodule 423 can receive the selection clock signal and use the corresponding voltage adjustment level to delay the selection clock signal to obtain a delayed clock signal.

[0068] As an example, the delay submodule 423 includes (M-1) voltage-controlled capacitors Cx1 to CxM and M buffers Buf1 to BufM connected in series (M is an integer greater than 1). The first terminal of each voltage-controlled capacitor Cxi (i is an integer greater than or equal to 1 and less than or equal to M) is used to receive the corresponding level adjustment voltage V. TUNEi The second end of each voltage-controlled capacitor Cxi is coupled to the output of the corresponding buffer Bufi.

[0069] The third OR gate 424 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the third OR gate 424 is coupled to the delay submodule 423, the second input terminal is coupled to the first selection submodule 422, and the output terminal is coupled to the second selection submodule 425. The third OR gate 424 is used to receive the selected output clock signal and the delayed clock signal, and to obtain an initial correction clock signal based on the output clock signal and the delayed clock signal.

[0070] The second selection submodule 425 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second selection submodule 425 is coupled to the first selection submodule 422, the second input terminal of the second selection submodule 425 is coupled to the output terminal of the third OR gate 424, and the output terminal of the second selection submodule 425 serves as the output terminal of the duty cycle shaping module or is coupled to the output terminal of the duty cycle shaping module. The second selection submodule 425 is used to receive a second selection control signal SELECT2 and select the selection clock signal and the initial correction clock signal as the correction clock signal CLK according to the second selection control signal SELECT2. cal .

[0071] As an example, the second selection submodule 425 is a multiplexer. In other embodiments, the second selection submodule 425 can also be other structures with the same function, which are not limited here.

[0072] The structure of the duty cycle calibration circuit in the embodiments of the present invention has been described above. The working principle of the duty cycle calibration circuit described above will be described below.

[0073] Figure 6 The pulse timing diagram of the relevant signals of the duty cycle calibration circuit in an embodiment of the present invention is shown; Figure 7 This is a schematic flowchart of a duty cycle calibration method according to an embodiment of the present invention. (See also...) Figures 1 to 7 The duty cycle calibration method in this embodiment of the invention may specifically include:

[0074] Step S701: Obtain the number of counting pulses generated in the high-level and low-level states of the correction clock signal within a preset counting period; the frequency of the counting clock signal that generates the counting pulses is higher than the frequency of the correction clock signal.

[0075] The number of counting pulses generated in the high-level and low-level states of the correction clock signal within a preset counting period is obtained in order to subsequently obtain the current duty cycle of the correction clock signal.

[0076] Counting clock signal CLK cnt Used to correct the clock signal CLK within a preset counting period. cal The high-level and low-level states are detected. Specifically, the correction clock signal CLK within a preset counting period is acquired. cal The first number of counting pulses generated in the high-level state, and the correction clock signal CLK within the preset counting period. cal The second number of counting pulses generated in the low-level state.

[0077] Therefore, the counting clock signal CLK cntThe frequency needs to be higher than the correction clock signal CLK. cal So that the counting clock signal CLK can be used cnt Obtain the calibration clock signal CLK within the preset counting period. cal The number of counting pulses generated in the high-level and low-level states.

[0078] Counting clock signal CLK cnt It can be generated by any suitable clock signal source. As an example, a ring oscillator (VCO) is used to generate the counting clock signal CLK. cnt .

[0079] It is understandable that the clock signal CLK is being calibrated. cal Given a fixed frequency, if the counting clock signal CLK cnt The higher the frequency, the more accurate the correction clock signal CLK will be within the preset counting period. cal The larger the values ​​of the first number of counting pulses generated in the high-level state and the second number of counting pulses generated in the low-level state, the more accurately the first and second numbers can reflect the subtle differences between the acquired first and second numbers. Therefore, this can improve the accuracy of the subsequently acquired correction clock signal CLK. cal The accuracy of the duty cycle helps to improve the accuracy of duty cycle calibration.

[0080] The preset counting period can be set according to actual needs. Specifically, the preset counting period is related to the counting clock signal CLK. cnt With the correction clock signal CLK cal The frequency is related to the counting accuracy.

[0081] For example, when the frequency ratio between the counting clock signal and the correction clock signal is 100:1, only 1% counting accuracy can be achieved in one correction clock cycle. Therefore, when the counting accuracy is 1‰, 10 correction clock cycles are required to achieve it.

[0082] Therefore, the preset counting period and the counting clock signal CLK cnt With the correction clock signal CLK cal The frequency ratio is directly proportional to the counting accuracy, while it is inversely proportional to the counting accuracy.

[0083] In this embodiment, the counting unit 10 is used to acquire the correction clock signal CLK within a preset counting period. cal The number of counting pulses generated in the high-level and low-level states. Specifically, the first counting module 110 acquires the correction clock signal CLK within a preset counting period. calThe first count of counting pulses generated under the high-level state is obtained, and the correction clock signal CLK within the preset counting period is obtained by the second counting module 120. cal The second number of counting pulses generated under the low-high level state.

[0084] Before counting is performed using the counting unit 10, a corresponding initialization operation is performed to put the counting unit 10 into a ready state. Specifically, the counting enable signal CNT_EN, the first counting control signal CNT_1, the second counting control signal CNT_2, and the counting reset signal RST are set.

[0085] Specifically, the counting enable signal CNT_EN and the first counting control signal CNT_1 are at a high level during the counting clock cycle, the second counting control signal CNT_2 is at a high level during the counting clock cycle, and before the start of the counting clock cycle, the counting values ​​of the first counting module and the second counting module are cleared to zero by the counting reset signal RST.

[0086] Counting begins in the first counting module 110 when the calibration clock signal CLK is activated. cal When in a high-level state, the output signal of the first OR gate 111 is determined by the counting clock signal CLK. cnt The decision is made by the output signal of the first OR gate 111 and the counting clock signal CLK. cnt The same applies. Simultaneously, the second output of the first AND gate 112 is used to receive the first counting control signal CNT_1, and the first counting control signal CNT_1 is high during the counting period. Therefore, the output signal of the second AND gate 112 is determined by the counting clock signal CLK at its first input. cnt The decision is made such that the output signal of the second AND gate 112 is synchronized with the counting clock signal CLK. cnt Similarly, this allows the first counter 113 to correct the clock signal CLK within a preset counting period. cal The counting pulses generated under the high-level state are used for counting.

[0087] Similarly, in the second counting module 120, when the calibration clock signal CLK... cal When in a low-level state, the output signal of the second AND gate 121 is determined by the counting clock signal CLK. cnt The decision is made between the output signal of the second AND gate 121 and the counting clock signal CLK. cnt The same applies. Simultaneously, the second output of the second OR gate 122 is used to receive the second counting control signal CNT_2, and the second counting control signal CNT_2 is low during the counting period. Therefore, the output signal of the second OR gate 122 is determined by the counting clock signal CLK at its first input.cnt The decision is made such that the output signal of the second OR gate 122 is synchronized with the counting clock signal CLK. cnt Similarly, this allows the second counter 123 to correct the clock signal CLK within a preset counting period. cal The counting is performed using the counting pulses generated during the low-level state.

[0088] Step S702: Obtain the current duty cycle information of the correction clock signal based on the number of counting pulses generated in the high-level and low-level states of the correction clock signal within the preset counting period.

[0089] Obtain the correction clock signal CLK cal The current duty cycle information, to be compared with the correction clock signal CLK. cal The target duty cycle is compared, and the correction clock signal CLK can be adjusted based on the comparison result. cal The target duty cycle is adjusted.

[0090] Specifically, the clock signal CLK is corrected according to the preset counting period. cal The correction clock signal CLK is obtained by counting the number of clock signals generated in the high-level and low-level states. cal The steps for obtaining the current duty cycle information include: calculating the correction clock signal CLK within a preset counting period. cal The first number of counting pulses generated in the high-level state is equal to the number of correction clock signals CLK within the preset counting period. cal The correction clock signal CLK is obtained by comparing the ratio between the first number of counting pulses generated in the high-level state and the sum of the second number of counting pulses generated in the low-level state. cal The current duty cycle information.

[0091] For example, if the number of counting clock signals generated by the correction clock signal in the high-level state and the low-level state within the preset counting period is 2500 and 7500 respectively, then the current duty cycle of the correction clock signal is 2500 / (2500+7500), which is 25%.

[0092] In this embodiment, the control unit 20 obtains the correction clock signal CLK based on the number of counting pulses generated during the high-level and low-level states of the correction clock signal CLKcal within a preset counting period. cal The current duty cycle information.

[0093] Specifically, when the preset counting period ends, the control unit 20 generates a corresponding read control signal Ctr_Read and sends it to the counting unit 10, so that the first counting module 110 and the second counting module 120 in the counting unit 10 correct the clock signal CLK within the preset counting period. cal The first number of counting pulses generated in the high-level state and the second number of counting pulses generated in the low-level state are latched respectively. Then, the control unit 20 obtains the correction clock signal CLK within the preset counting period from the first counting module 110 and the second counting module 120 in the counting unit 10, respectively. cal The first number of counting pulses generated in the high-level state and the second number of counting pulses generated in the low-level state are used to calculate the correction clock signal CLK by using the first number and the second number obtained from the first counting module 110 and the second counting module 120 in the counting unit 10, respectively. cal The current duty cycle information.

[0094] It can be seen that by correcting the clock signal CLK within the preset counting period... cal The correction clock signal CLK is obtained by counting the first number of counting pulses generated in the high-level state and the second number of counting pulses generated in the low-level state. cal Instead of comparing the calibration clock signal with the reference clock signal to obtain the current duty cycle information of the calibration clock signal, the current duty cycle information of the calibration clock signal is obtained. This avoids the inaccuracy of the current duty cycle of the calibration clock signal due to the inaccuracy of the reference clock signal, thus improving the accuracy of duty cycle detection and consequently improving the accuracy of duty cycle calibration.

[0095] Step S703: Compare the duty cycle of the correction clock signal with the preset target duty cycle, and generate a corresponding control signal based on the comparison result between the duty cycle of the correction clock signal and the preset target duty cycle.

[0096] The correction clock signal CLK cal The duty cycle is compared with the preset target duty cycle, the corresponding comparison result is obtained, and a corresponding control signal is generated based on the comparison result to realize the calibration of the clock signal CLK. cal Duty cycle control.

[0097] In this embodiment, the control unit 20 is used to transmit the correction clock signal CLK. cal The duty cycle is compared with the preset target duty cycle, and the correction clock signal CLK is used as the basis for the comparison. cal The duty cycle is compared with the preset target duty cycle, and the corresponding control signal is generated.

[0098] Subsequently, by adjusting the regulating voltage V TUNE The size of the voltage is adjusted to control the duty cycle of the input clock signal. Accordingly, the control unit 20 uses a boost control signal Ctrl. inc and buck control signal Ctrl dec To achieve the adjustment of voltage V TUNE Adjustments.

[0099] Specifically, the control unit 20 determines the correction clock signal CLK. cal When the current duty cycle is higher than the target duty cycle, the buck control signal Ctrl is generated. dec To achieve voltage regulation V TUNE The reduction adjustment; in determining the correction clock signal CLK cal When the current duty cycle is lower than the target duty cycle, the boost control signal Ctrl is generated. inc To achieve voltage regulation V TUNE Incremental adjustments.

[0100] Step S704: Adjust the duty cycle of the input clock signal according to the control signal until the duty cycle of the generated correction clock signal reaches the target duty cycle.

[0101] The input clock signal CLK is adjusted according to the received control signal. in The duty cycle is adjusted to ultimately correct the clock signal CLK. cal The duty cycle has reached the target duty cycle.

[0102] In this embodiment, the duty cycle adjustment unit 30 adjusts the input clock signal CLK according to the received control signal. in The duty cycle is adjusted.

[0103] Specifically, the regulating voltage supply module 310 in the duty cycle adjustment unit 30 uses multiple voltage divider resistors R connected in series. t1 ~R tN The preset first power supply voltage VDD1 is divided to generate multiple adjustable voltage levels V. TUNE1～ V TUNEN Upon receiving the boost control signal Ctrl inc When the voltage is higher than the current voltage setting, select and output the next voltage setting; upon receiving the step-down control signal Ctrl... dec When the voltage is lower than the current voltage setting, select the next voltage setting and output it.

[0104] In this embodiment, the regulating voltage providing module 310 in the duty cycle adjustment unit 30 uses the regulating voltage generation submodule 311 to generate regulating voltages for multiple levels. The regulating voltages for N levels generated by the regulating voltage generation submodule 311 can be calculated using the following formula:

[0105] V TUNEi =VDD-I TUNE *(R t1 +R t2 +……+R t(i-1) (1)

[0106] Among them, V TUNEi I represents the voltage adjustment at the i-th gear. TUNE R represents the constant current output by the current source. t(i-1) This represents the (i-1)th voltage divider resistor, where i is an integer greater than or equal to 1 and less than or equal to N.

[0107] The selection output submodule 312 in the voltage supply module 310 receives the boost control signal Ctrl. inc When the voltage is higher than the current voltage setting, select and output the next voltage setting; upon receiving the step-down control signal Ctrl... dec When the voltage is lower than the current voltage setting, select the next voltage setting and output it.

[0108] From formula (1), it can be seen that adjusting the voltage V TUNEi The voltage is inversely proportional to the gear level (i), meaning the voltage at a higher gear is lower than the voltage at a lower gear. Therefore, the current gear's voltage is the same as the voltage at the i-th gear (V). TUNEi When the voltage of the next adjustment level is higher than the current adjustment level, the adjustment voltage is V. TUNE(i-1) The next adjustment voltage, which is lower than the current adjustment voltage, is V. TUNE(i+1) .

[0109] The duty cycle shaping module 320 in the duty cycle adjustment unit 30 receives the corresponding gear adjustment voltage V. TUNEi And adjust the voltage V according to the received corresponding gear level. TUNEi For the input clock signal CLK in The duty cycle is adjusted.

[0110] Please see Figure 3 In this embodiment, the voltage V is adjusted using the received corresponding gear level. TUNEi For the input clock signal CLK in When adjusting the duty cycle, the first capacitor C1 will input the clock signal CLK. inAfter DC filtering, the output is sent to the input of the first inverter 311 to eliminate the input clock signal CLK. in The DC signal in the circuit causes interference with the duty cycle adjustment.

[0111] At the same time, the voltage adjustment module 310 provides the corresponding adjustable voltage V. TUNEi After biasing through the first resistor R1, a corresponding bias voltage is generated and provided to the input terminal of the first inverter 311, thereby providing a bias voltage for the duty cycle shaping module. Therefore, by adjusting the voltage at the appropriate level, the on-time ratio of the first PMOS transistor P1 and the first NMOS transistor N1 in the first inverter 311 is adjusted; that is, by adjusting the bias voltage, the on-time ratio of the first PMOS transistor P1 and the first NMOS transistor N1 in the first inverter 311 is adjusted, thereby achieving the adjustment of the input clock signal CLK. in The first inversion process is performed to generate the corresponding inverted clock signal and adjust the duty cycle of the inverted clock signal.

[0112] Specifically, when the bias voltage is larger, the conduction time of the first PMOS transistor P1 decreases, and the conduction time of the first NMOS transistor N1 increases accordingly, thereby reducing the duty cycle of the inverted clock signal; conversely, when the bias voltage is smaller, the conduction time of the first PMOS transistor P1 increases, and the conduction time of the first NMOS transistor N1 decreases accordingly, thereby increasing the duty cycle of the inverted clock signal.

[0113] Next, the first inverted clock signal is buffered and inverted using a second inverter 322, so that the generated correction clock signal CLK cal With input clock signal CLK in Maintain in-phase. Furthermore, correct the clock signal CLK. cal The clock signal CLK is inverted from the first inverted clock signal; therefore, as the duty cycle of the first inverted clock signal increases, the correction clock signal CLK... cal The duty cycle of the clock signal decreases accordingly; when the duty cycle of the first inverting clock signal decreases, the correction clock signal CLK... cal The duty cycle is increased accordingly.

[0114] Therefore, the clock signal CLK is corrected. cal When the current duty cycle is higher than the target duty cycle, the adjustment voltage V of the input duty cycle shaping module is reduced. TUNE To reduce the correction clock signal CLK cal The duty cycle; when the clock signal CLK is corrected. cal When the current duty cycle is lower than the target duty cycle, the adjustment voltage V of the input duty cycle shaping module is increased. TUNE To improve the calibration clock signal CLK calThe duty cycle is adjusted. This process is repeated until the generated correction clock signal CLK is obtained. cal The duty cycle reaches the target duty cycle.

[0115] In other embodiments, the duty cycle shaping module 320 can also select an input clock signal or an inverted input clock signal with a duty cycle lower than the target duty cycle, and perform duty cycle boosting processing on the input clock signal or the inverted input clock signal with a duty cycle lower than the target duty cycle, so that the duty cycle of the acquired corrected clock signal reaches the target duty cycle. See details below. Figure 4 and Figure 5 .

[0116] like Figure 4 and Figure 5 As shown, initially, both the first selection control signal SELECT1 and the second selection control signal SELECT2 are logic 0. At this time, the input clock signal CLK... in As the calibration clock signal CLK cal Output is performed. If the calibration clock signal CLK... cal The current duty cycle is higher than the target duty cycle, indicating that the input clock signal CLK... in If the duty cycle of the input clock signal is higher than the target duty cycle, the first selection control signal SELECT1 changes from logic 0 to logic 1, causing the first selection submodule 422 to output the input inverted clock signal with a duty cycle lower than the target duty cycle as the selection clock signal. Conversely, if the calibration clock signal CLK... cal The current duty cycle is lower than the target duty cycle, indicating that the input clock signal CLK... in If the duty cycle is lower than the target duty cycle, the value of the first selection control signal SELECT1 remains unchanged at logic 0, and the first selection submodule 422 will select the input clock signal CLK with a duty cycle lower than the target duty cycle. in It is used as a selection clock signal for output.

[0117] After setting the value of the first selection control signal SELECT1, the value of the second selection control signal SELECT2 is changed from logic 0 to logic 1, so that the second selection submodule 425 outputs the initial correction clock signal output by the third OR gate 424 as the correction clock signal.

[0118] The initial correction clock signal output by the third OR gate 424 is generated based on the selection clock signal and the delayed clock signal. Specifically, after the selection clock signal and the delayed clock signal are logically ORed by the third OR gate 424, the rising edge of the initial correction clock signal output by the third OR gate 424 is determined by the rising edge of the selection clock signal, while the falling edge of the initial correction clock signal is determined by the falling edge of the delayed clock signal obtained by delaying the selection clock signal.

[0119] Therefore, in the calibration clock signal CLK cal If the duty cycle is less than the target duty cycle, the voltage V is adjusted by increasing the corresponding level. TUNEi This increases the delay time of the delay submodule 423, delaying the arrival of the falling edge of the delay clock signal, thereby increasing the duty cycle of the correction clock signal; if the duty cycle of the correction clock signal is greater than the target duty cycle, the voltage V is adjusted by reducing the corresponding level. TUNEi This reduces the delay time of the delay submodule 423, allowing the falling edge of the delayed clock signal to arrive earlier, thereby reducing the duty cycle of the correction clock signal. This process is repeated until the generated correction clock signal CLK is obtained. cal The duty cycle reaches the target duty cycle.

[0120] Accordingly, embodiments of the present invention also provide a chip, including the aforementioned duty cycle calibration circuit. The duty cycle calibration circuit has been described in the foregoing section and will not be repeated here.

[0121] Accordingly, embodiments of the present invention also provide an electronic device, including the aforementioned chip, wherein the chip includes the duty cycle calibration circuit. The duty cycle calibration circuit has been described in the foregoing section and will not be repeated here.

[0122] The foregoing describes multiple embodiments of the present invention. The optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed or made public by the present invention.

[0123] While the embodiments of the present invention have been disclosed above, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A duty cycle calibration circuit, characterized in that, include: The counting unit is suitable for receiving a correction clock signal; The number of counting pulses generated in the high-level and low-level states of the correction clock signal within a preset counting period is obtained; the frequency of the counting clock signal that generates the counting pulses is higher than the frequency of the correction clock signal. The control unit is adapted to receive the number of counting pulses generated in the high-level and low-level states of the correction clock signal within the preset counting period; obtain the current duty cycle information of the correction clock signal based on the number of counting pulses generated in the high-level and low-level states of the correction clock signal within the preset counting period; compare the current duty cycle of the correction clock signal with a preset target duty cycle; and generate a corresponding control signal based on the comparison result between the current duty cycle of the correction clock signal and the target duty cycle. The duty cycle adjustment unit is adapted to receive the control signal and the input clock signal; adjust the duty cycle of the input clock signal according to the control signal to obtain a corresponding correction clock signal until the duty cycle of the correction clock signal reaches the target duty cycle; Specifically, the duty cycle adjustment unit includes: an adjustment voltage providing module, adapted to receive a first power supply voltage and perform voltage division processing on the first power supply voltage using multiple series-connected voltage divider resistors to generate multiple adjustment voltage levels; when receiving a boost control signal, selecting and outputting the next adjustment voltage level that is higher than the current adjustment voltage level; and when receiving a buck control signal, selecting and outputting the next adjustment voltage level that is lower than the current adjustment voltage level. The duty cycle shaping module includes a first inverter composed of a first PMOS transistor and a first NMOS transistor, adapted to receive a corresponding level adjustment voltage and use the received corresponding level adjustment voltage to adjust the conduction time ratio between the first PMOS transistor and the first NMOS transistor, thereby adjusting the duty cycle of the input clock signal.

2. The duty cycle calibration circuit according to claim 1, characterized in that, The counting unit includes: The first counting module is adapted to obtain the first number of counting pulses generated during the high-level state of the correction clock signal within the preset counting period; The second counting module is adapted to obtain the second number of counting pulses generated when the correction clock signal is in a low-level state within the preset counting period.

3. The duty cycle calibration circuit according to claim 2, characterized in that, The first counting module includes a first OR gate, a first AND gate, and a first counter; The first input terminal of the first OR gate is used to receive the correction clock signal, the second input terminal of the first OR gate is used to receive the counting clock signal, and the output terminal of the first OR gate is coupled to the first input terminal of the first AND gate. The second input terminal of the first AND gate is used to receive the first counting control signal, and the output terminal of the first AND gate is coupled to the input terminal of the first counter; the first counting control signal is high level during the counting period; The output terminal of the first counter serves as the output terminal of the first counting module or is coupled to the output terminal of the first counting module.

4. The duty cycle calibration circuit according to claim 2, characterized in that, The second counting module includes a second AND gate, a second OR gate, and a second counter; The first input of the second AND gate is used to receive the correction clock signal, the second input of the second AND gate is used to receive the counting clock signal, and the output of the second AND gate is coupled to the first input of the second OR gate. The second input terminal of the second OR gate is used to receive the second counting control signal, and the output terminal of the second AND gate is coupled to the input terminal of the second counter; the second counting control signal is low during the counting period; The output terminal of the second counter serves as the output terminal of the second counting module or is coupled to the output terminal of the second counting module.

5. The duty cycle calibration circuit according to claim 1, characterized in that, The control unit is adapted to generate a corresponding buck control signal when it is determined that the duty cycle of the correction clock signal is higher than the target duty cycle; and to generate a corresponding boost control signal when it is determined that the duty cycle of the correction clock signal is lower than the target duty cycle. The duty cycle adjustment unit is adapted to generate multiple levels of adjustment voltage; when receiving the boost control signal, it adjusts the duty cycle of the input clock signal using the next level adjustment voltage which is higher than the current level adjustment voltage; when receiving the buck control signal, it adjusts the duty cycle of the input clock signal using the next level adjustment voltage which is lower than the current level adjustment voltage.

6. The duty cycle calibration circuit according to claim 1 or 5, characterized in that, The control unit includes a finite state machine.

7. The duty cycle calibration circuit according to claim 1, characterized in that, The voltage regulation module includes: The voltage generation submodule is adapted to receive a first power supply voltage and use multiple series-connected voltage divider resistors to divide the first power supply voltage to generate multiple adjustable voltage levels. The output selection submodule is adapted to select and output the next adjustable voltage that is higher than the current adjustable voltage when the boost control signal is received; and to select and output the next adjustable voltage that is lower than the current adjustable voltage when the buck control signal is received.

8. The duty cycle calibration circuit according to claim 7, characterized in that, The voltage generation submodule includes a current source and multiple voltage divider resistors connected in series. The first end of the current source is used to receive the first power supply voltage, and the second end of the current source is grounded through the series-connected multiple voltage divider resistors.

9. The duty cycle calibration circuit according to claim 7, characterized in that, The output selection submodule includes a multiplexer.

10. The duty cycle calibration circuit according to claim 1, characterized in that, In the first inverter, the gate terminal of the first PMOS transistor is coupled to the gate terminal of the first NMOS transistor and serves as the input terminal of the duty cycle shaping module or is coupled to the input terminal of the duty cycle shaping module. The source terminal of the first PMOS transistor is used to receive the second power supply voltage. The drain terminal of the first PMOS transistor is coupled to the drain terminal of the first NMOS transistor and serves as the output terminal of the first inverter or is coupled to the output terminal of the first inverter. The source terminal of the first NMOS transistor is grounded. The duty cycle shaping module further includes a second inverter; the second inverter includes a second PMOS transistor and a second NMOS transistor; the gate terminal of the second PMOS transistor is coupled to the gate terminal of the second NMOS transistor and serves as the input terminal of the second inverter or is coupled to the input terminal of the second inverter; the source terminal of the second PMOS transistor is used to receive the second power supply voltage; the drain terminal of the second PMOS transistor is coupled to the drain terminal of the second NMOS transistor and serves as the output terminal of the duty cycle shaping module or is coupled to the output terminal of the duty cycle shaping module; the source terminal of the second NMOS transistor is grounded.

11. The duty cycle calibration circuit according to claim 10, characterized in that, The duty cycle shaping module also includes: The bias voltage generation submodule is adapted to receive the corresponding level adjustment voltage, and to perform bias processing on the corresponding level adjustment voltage to obtain the corresponding bias voltage.

12. The duty cycle calibration circuit according to claim 11, characterized in that, The bias voltage generation submodule includes a first resistor; The first end of the first resistor is used to receive the voltage of the corresponding gear adjustment, and the second end of the first resistor is coupled to the first inverter.

13. The duty cycle calibration circuit according to claim 10, characterized in that, The duty cycle shaping module also includes: An AC coupling submodule is adapted to receive the input clock signal and perform DC signal isolation processing on the input clock signal.

14. The duty cycle calibration circuit according to claim 13, characterized in that, The AC coupling submodule includes a first capacitor; The first terminal of the first capacitor is used to receive the input clock signal, and the second terminal of the first capacitor is coupled to the first inverter.

15. The duty cycle calibration circuit according to claim 1, characterized in that, The duty cycle shaping module includes: The third inverter is adapted to receive the input clock signal, invert the input clock signal, and obtain an inverted input clock signal. The first selection submodule is adapted to receive a first selection control signal and select the input clock signal or the input inverted clock signal as the selection clock signal according to the first selection control signal; wherein, when the duty cycle of the correction clock signal is higher than the target duty cycle, the first selection control signal is logic 1; when the duty cycle of the correction clock signal is lower than the target duty cycle, the first selection control signal is logic 0. The delay submodule is adapted to receive the selected clock signal and the corresponding gear adjustment voltage, and to use the corresponding gear adjustment voltage to delay the selected clock signal to obtain a delayed clock signal; The third OR gate is adapted to receive the selected clock signal and the delayed clock signal, and to obtain an initial correction clock signal based on the selected clock signal and the delayed clock signal; The second selection submodule is adapted to receive a second selection control signal and select the selection clock signal and the initial correction clock signal as the correction clock signal according to the second selection control signal; wherein, initially, the second selection control signal is logic 0; after obtaining the logic value of the first selection control signal, the second selection control signal is logic 1.

16. The duty cycle calibration circuit according to claim 15, characterized in that, The delay submodule includes (M-1) voltage-controlled capacitors and M series-connected buffers, where M is an integer greater than 1; The first terminal of each voltage-controlled capacitor is used to receive the corresponding level adjustment voltage, and the second terminal of each voltage-controlled capacitor Cxi is coupled to the output terminal of the corresponding buffer.

17. A chip, characterized in that, Includes the duty cycle calibration circuit as described in any one of claims 1-16.

18. An electronic device, characterized in that, Including the chip as described in claim 17.

19. A duty cycle calibration method, characterized in that, include: The number of counting pulses generated by the correction clock signal in the high-level and low-level states within a preset counting period is obtained; the frequency of the counting clock signal that generates the counting pulses is higher than the frequency of the correction clock signal. The current duty cycle information of the correction clock signal is obtained based on the number of counting pulses generated by the correction clock signal in the high-level and low-level states within the preset counting period. The current duty cycle of the correction clock signal is compared with the preset target duty cycle; Based on the comparison result between the duty cycle of the correction clock signal and the target duty cycle, a corresponding control signal is generated; The duty cycle of the input clock signal is adjusted according to the control signal to obtain a corresponding correction clock signal until the duty cycle of the correction clock signal reaches the target duty cycle. Specifically, this includes: receiving a first power supply voltage using an adjustable voltage supply module, and dividing the first power supply voltage using multiple series-connected voltage divider resistors to generate multiple adjustable voltage levels; when a boost control signal is received, selecting and outputting the next adjustable voltage level that is higher than the current adjustable voltage level; when a buck control signal is received, selecting and outputting the next adjustable voltage level that is lower than the current adjustable voltage level; receiving the corresponding adjustable voltage level using a duty cycle shaping module including a first inverter composed of a first PMOS transistor and a first NMOS transistor, and adjusting the conduction time ratio between the first PMOS transistor and the first NMOS transistor using the received corresponding adjustable voltage level, thereby adjusting the duty cycle of the input clock signal.

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