System for executing an add instruction and method for executing an add instruction

Abstract

The present application relates to a system and method for executing a newly added instruction, the method comprising: receiving an instruction; determining whether the received instruction is a newly added instruction; and when the received instruction is a newly added instruction: generating a simulation identifier, wherein the simulation identifier is a first value; issuing a system management interrupt based on the simulation identifier; entering a system management mode in response to the system management interrupt, and simulating execution of the received instruction in the system management mode to generate a simulation execution result; and storing the simulation execution result in a system management memory. Thus, without modifying the micro-architecture of a processor, a newly added instruction supported by a later generation processor can be implemented on a previous generation processor, thereby greatly reducing the workload for design, testing, etc., and thus saving a large amount of cost.

Description

TECHNICAL FIELD

[0001] The present application relates to a method and system for executing instructions, and in particular, to a method for executing new instructions and a system for executing new instructions. BACKGROUND

[0002] With the enhancement of processor functions, the new generation of processors tend to add new instructions on the basis of the previous generation of processors. When implementing the new instructions newly supported by the new generation of processors on the previous generation of processors, the micro-architecture of the previous generation of processors often needs to be modified. The modification of the micro-architecture requires a large amount of design, testing and other work, and thus is extremely costly.

[0003] Therefore, how to implement the instructions newly supported by the new generation of processors on the basis of the previous generation of processors without modifying the micro-architecture of the previous generation of processors has become a problem to be solved in the field. SUMMARY

[0004] In order to solve the above problems, the present application provides a method and system for executing new instructions.

[0005] The present application provides a method for executing new instructions, comprising: receiving an instruction; determining whether the received instruction is a new instruction; and when the received instruction is a new instruction: generating a simulation identifier, wherein the simulation identifier is a first value; issuing a system management interrupt according to the simulation identifier; in response to the system management interrupt, entering a system management mode, and simulating the execution of the received instruction in the system management mode to generate a simulation execution result; and storing the simulation execution result in a system management memory.

[0006] The present application provides a system for executing new instructions, comprising: a system management memory; and an instruction monitor unit (monitor) for determining whether a received instruction is a new instruction; when the received instruction is a new instruction, the system for executing new instructions generates a simulation identifier, issues a system management interrupt according to the simulation identifier; in response to the system management interrupt, enters a system management mode, and simulates the execution of the received instruction in the system management mode to generate a simulation execution result; and stores the simulation execution result in the system management memory, wherein the simulation identifier is a first value.

[0007] Through the method and system for executing new instructions provided by the present application, the instructions newly supported by the new generation of processors can be implemented on the previous generation of processors without modifying the micro-architecture of the processor. Thus, the workload for design, testing and other work is greatly reduced, and therefore a large amount of cost can be saved. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a schematic diagram showing a system for executing a new instruction according to an embodiment of the present application.

[0009] Figure 2A is a structural diagram showing a processor according to a first embodiment of the present application.

[0010] Figure 2B is a structural diagram showing a processor according to a second embodiment of the present application.

[0011] Figure 2B1 is a structural diagram showing an instruction monitoring unit according to a second embodiment of the present application.

[0012] Figure 2C is a structural diagram showing a processor according to a third embodiment of the present application.

[0013] Figure 2D is a structural diagram showing a processor according to a fourth embodiment of the present application.

[0014] Figure 2D1 is a structural diagram showing an instruction monitoring unit according to a fourth embodiment of the present application.

[0015] Figure 3 is a flowchart showing a process of receiving an instruction according to an embodiment of the present application.

[0016] Figure 4 is a flowchart showing an entry into a system management mode according to an embodiment of the present application.

[0017] Figure 5 is a flowchart showing a process of an emulator according to an embodiment of the present application.

[0018] Figure 6 is an example showing an execution of a received instruction in a system management mode according to an embodiment of the present application.

[0019] Figure 7 is a flowchart showing an exit from a system management mode according to an embodiment of the present application.

[0020] Figure 8 is a flowchart showing an execution of a new instruction according to an embodiment of the present application.

[0021] Figure 9 is a flowchart showing an execution of a new instruction according to another embodiment of the present application.

[0022] Figure 10 is a flowchart showing an execution of a new instruction according to another embodiment of the present application.

[0023] Brief description of the symbols in the drawings is as follows:

[0024] 100: system executing the new instruction; 110: processor; 112: instruction monitoring unit; 114: system management mode exit / entry; 1142: system management mode entry; 1144: system management mode exit; 116: dedicated hardware; 120: operating system; 130: application program; 132: new instruction; 142: emulator; 201: instruction bypass translation buffer; 202, 202B, 202D: instruction cache; 203: branch predictor; 204, 204C, 204D: renaming unit; 205: reservation station; 206: execution unit; 207: memory access unit; 210, 210B, 210C, 210D: instruction monitoring unit; 2101B, 2101D: instruction resolution unit; 2102B, 2102D: instruction judgment unit; 211: dedicated register set; 220, 220B, 220D: private register; 221, 221C, 221D: microcode control unit; 230, 230B, 230D: instruction decoding unit; 240, 240C, 240D: reordering buffer; 245, 245C, 245D: instruction commit unit; 260: architectural register; EF, EF1-EN: emulation identifier; S301-S315, S401-S411, S501-S519, S701-S729, S801-S809, S901-S913, S1001-S1009: steps. DETAILED DESCRIPTION

[0025] The following description is a preferred implementation to complete the invention, which is intended to describe the basic spirit of the invention, but is not intended to limit the invention. The actual invention must refer to the scope of the claims.

[0026] It must be understood that the words "include", "including", and the like used in the specification are used to indicate the presence of a specific technical feature, value, method step, operation process, element, and / or component, but do not exclude the addition of more technical features, values, method steps, operation processes, elements, components, or any combination thereof.

[0027] The words such as "first", "second", "third" used in the claims are used to modify the elements in the claims, not to indicate the priority order, precedence, or one element before another element, or the time sequence when the method steps are executed, but only to distinguish elements with the same name.

[0028] In order to better describe the embodiments of the present invention, the following first defines the special terms used in the present invention.

[0029] Old instruction: instructions natively supported by the previous generation processor are referred to as native instructions, also referred to as existing instructions or old instructions.

[0030] Unknown instruction: instructions not natively supported by the previous generation processor.

[0031] New instruction: instructions newly supported by the next generation processor compared with the previous generation processor. The new instruction cannot be recognized by the previous generation processor, and thus is unknown instruction to the previous generation processor.

[0032] New architecture register: architecture registers newly supported by the next generation processor compared with the previous generation processor. The new architecture register does not exist in the previous generation processor, and thus needs to be simulated when the new instruction using the new architecture register is executed on the previous generation processor.

[0033] Unrecognizable instruction: the part of the unknown instruction other than the new instruction. That is, the unrecognizable instruction refers to instructions not natively supported by the next generation processor.

[0034] Model special register: a type of register in the processor, which can be used to complete some specific functions.

[0035] Trap: a trap is generally caused by a software interrupt instruction (such as an INT instruction). When an instruction causes a trap exception, it does not mean that the execution of the instruction itself is incorrect. Therefore, when an instruction causes a trap exception, the processor continues to execute the next instruction of the instruction. For example, when a software developer debugs a software program code, a breakpoint can be set in the program code. When the program code with the set breakpoint is executed on the processor, a trap is generated when the breakpoint is executed, so that the program code is paused at the breakpoint. The software developer can view the values of the architecture registers in the processor or the values of the variables in the program code when the program code is executed to the breakpoint through the microcode processing program of the trap, and determine whether the program code is executed normally when executed to the breakpoint according to the values of the architecture registers or the values of the variables in the program code.

[0036] Figure 1 is a schematic diagram of a system 100 for executing a new instruction according to an embodiment of the present application. As shown in FIG. 1, the system 100 includes a processor 1000 and a memory 2000. The processor 1000 includes a plurality of architecture registers 1010, a plurality of model special registers 1020, and a plurality of unrecognizable instructions 1030. The memory 2000 includes a plurality of old instructions 2010 and a plurality of new instructions 2020. Figure 1As shown, the system 100 executing the new instruction includes a processor 110, an operating system 120, an application 130, and an emulator 142. The operating system 120 runs on the processor 110 for managing the processor 110. The application 130 runs on the operating system 120 and can use various functions provided by the operating system 120 using the processor 110 and other hardware (not shown, such as hard disk, network card, etc.). The emulator 142 runs on the processor 110 in the system management mode (SMM). The operating system 120 or the application 130 cannot perceive the execution process of the emulator 142. That is, all operations performed by the emulator 142 are transparent to the operating system 120 or the application 130.

[0037] When the processor 110 executes a new instruction to the application 130 or the operating system 120, the processor 110 enters the system management mode and sends the new instruction to the emulator 142 for simulating the execution of the new instruction. It is worth noting that the source code of the application 130 or the operating system 120 is generally written in a high-level language (such as C language, C++ language, etc.) and / or a low-level language (such as assembly language, etc.). After the source code is compiled using a compiler, executable code that can be executed by the processor is generated. The executable code is composed of instructions that can be directly executed by the processor. In the present application, the application 130 or the operating system 120 refers to the executable code generated by the compiler after compiling the source code of the application 130 or the operating system 120. In the following, the execution of the new instruction by the processor 110 in the application 130 in Figure 1 The execution process of the system 100 executing the new instruction is described below with reference to the execution of the instruction 118 of the application 130 by the processor 110 in the system 100 in

[0038] As shown in Figure 1 The processor 110 includes an instruction monitoring unit 112 and a system management mode exit / entry 114. The system management mode exit / entry 114 includes a system management mode entry 1142 and a system management mode exit 1144. Figure 1 The solid arrows with numbers indicate the transmission direction of the instruction information, and the dashed arrows with numbers indicate the transmission direction of the instruction simulation execution result. The entire process of the processor 110 simulating the execution of the new instruction 132 is described below.

[0039] First, the processor 110 receives an instruction 118 in the application 130 that completes a specified function (as shown by solid arrow 1). After receiving the instruction 118, the instruction monitoring unit 112 determines whether the instruction 118 is a new instruction 132 and generates an emulation flag (EF). If the instruction 118 is a new instruction 132 (the emulation flag is a first value, in one embodiment, the first value is 1), the processor 110 issues a system management interrupt (#SMI) and sends the instruction information of the new instruction 132 to the system management mode entry / exit 114 (as shown by solid arrow 2). How to issue a system management interrupt is well known to those skilled in the art, and thus will not be described here. Then, the processor 110 enters the system management mode by executing the system management mode entry 1142 and sends the instruction information of the new instruction 132 to the emulator 142 (as shown by solid arrow 3). In the system management mode, the emulator 142 emulates execution of the new instruction 132. After emulating execution of the new instruction 132, the emulator 142 sends the emulation execution result to the system management mode entry / exit 114 (as shown by dashed arrow 4). Then, the processor 110 exits the system management mode by executing the system management mode exit 1144 and sends the emulation execution result to the application 130 (as shown by dashed arrow 5). At this point, the processor 110 has emulated execution of the new instruction 132. In one embodiment, during emulation execution of the new instruction 132 by the emulator 142, intermediate operation results generated during the emulation execution can be stored in the system management RAM (SMRAM).

[0040] In another embodiment, the processor 110 further includes dedicated hardware 116. During emulation execution of the new instruction 132 by the emulator 142, intermediate operation results generated during the emulation execution can be stored in the dedicated hardware 116. In another embodiment, when an operand of the new instruction 132 is a new architectural register (described in detail below), the emulator 142 can use the dedicated hardware 116 to emulate the new architectural register. Since the emulator 142 can access the dedicated hardware 116 at a faster speed than accessing the system management RAM, the speed of the emulation execution can be increased.

[0041] The present application has various embodiments, which are described below through four embodiments. The first embodiment and the second embodiment describe how to pass the emulation flag into the pipeline (i.e., pass the emulation flag into the execution unit 122, the load / store unit 124, the branch unit 126, and the register renaming unit 128, as shown by solid arrow 1 in FIG. 1). The third embodiment describes how to pass the emulation flag into the pipeline by passing the emulation flag into the register renaming unit 128 (as shown by dashed arrow 1 in FIG. 1). The fourth embodiment describes how to pass the emulation flag into the pipeline by passing the emulation flag into the register renaming unit 128 and the load / store unit 124 (as shown by dashed arrow 1 in FIG. 1). Figure 2Athe third embodiment and the fourth embodiment describe the case of entering the system management mode by storing the simulation identification into a private register, in which case the simulation identification does not need to be passed into the pipeline. The instruction monitoring unit in the first embodiment and the third embodiment judges whether the received instruction is the new instruction based on the instruction information of the received instruction from the instruction decoding unit. The instruction monitoring unit in the second embodiment and the fourth embodiment judges whether the received instruction is the new instruction based on the machine code of the received instruction from the instruction cache. The following first describes the first embodiment. Figure 2A and Figures 3-7 The first embodiment is described.

[0042] [First Embodiment]

[0043] Figure 2A is a structural diagram of a processor according to the first embodiment of the present application. Figure 2A As shown, the part on the left of the dotted line is Figure 1 is a structural diagram of the processor 110, and the emulator 142 on the right of the dotted line runs on the processor 110 in the system management mode. The following describes the Figure 1 Figure 2A

[0044] As shown in Figure 2A , the processor 110 includes an instruction translation lookaside buffer (ITLB) 201, an instruction cache 202, and a branch predictor 203. When the processor 110 executes an instruction of the application program 130 or the operating system 120, the instruction translation lookaside buffer 201 of the processor 110 receives the instruction. The branch predictor 203 is used to predict conditional branches and passes the branch prediction result to the instruction cache 202. The instruction cache 202 acquires the received instruction from the instruction translation lookaside buffer 201 according to the branch prediction result, and then the processor 110 further processes the received instruction.

[0045] As shown in Figure 2A ​​As shown, the processor 110 also includes an instruction decode unit 230, an instruction monitoring unit 210, private registers 220, a rename unit 204, a reservation station 205, an execution unit 206, a memory unit 207, a reorder buffer 240, a microcode control unit 221, architected registers 260, and a special register set 211. The instruction decode unit 230 fetches the received instruction from the instruction cache 202 and processes the received instruction to generate a microinstruction. The rename unit 204 receives the microinstruction from the instruction decode unit 230 and performs a renaming process on the received microinstruction. The rename unit 204 then sends the renamed microinstruction to the reservation station 205 and the reorder buffer 240. The reservation station 205 sends the microinstruction to the execution unit 206 or the memory unit 207 for further processing, depending on the type of the microinstruction. The reorder buffer 240 receives the microinstruction and stores it in an instruction entry. The area in the rename unit 204 that stores the microinstruction includes an emulation flag field (e.g., EF in Figure 2A ) that stores an emulation flag in the microinstruction. The reorder buffer 240 includes a plurality of instruction entries, each of which includes an emulation flag field (e.g., EF1, EF2, EFN, etc. in Figure 2A ) that stores an emulation flag in the microinstruction.

[0046] The instruction decode unit 230 decodes the received instruction to obtain decode information of the received instruction. The decode information includes a prefix, an escape code, an opcode, a ModR / M field, and other decode information, etc. The instruction decode unit 230 then generates a microinstruction based on the decode information. In one embodiment, when the received instruction is a new instruction, the generated microinstruction is a no-operation microinstruction (NOP). The instruction decode unit 230 sends the decode information of the received instruction to the instruction monitoring unit 210 to determine whether the received instruction is a new instruction. It is noted that the instruction monitoring unit 210 determines whether the unknown instruction is a new instruction based on the prefix, the escape code, the opcode, the ModR / M field, and other decode information of the received instruction. Those skilled in the art can implement the determination operation by using combinational logic circuits.

[0047] After determining whether the received instruction is a new instruction, the instruction monitoring unit 210 generates a simulation identifier. When the received instruction is a new instruction, the simulation identifier is a first value, indicating that the received instruction is an instruction to be simulated; otherwise, the simulation identifier is a second value, indicating that the received instruction is not an instruction to be simulated. In one embodiment, the first value is 1 and the second value is 0. Then, the instruction monitoring unit 210 sends the simulation identifier to the private register 220 and the renaming unit 204. When the simulation identifier is the first value (indicating that the received instruction is a new instruction), the instruction decoding unit 230 stops fetching instructions from the instruction cache 202 and sends the decoding information to the private register 220. The private register 220 stores the simulation identifier and the decoding information. The renaming unit 204 receives the microinstruction from the instruction decoding unit 230 and receives the simulation identifier from the instruction monitoring unit 210. Then, the renaming unit 204 adds a simulation identifier field EF to the microinstruction to store the simulation identifier. When the aforementioned analog flag is the second value (i.e., the received instruction is not a new instruction), the processor 110 will process the received instruction in a normal manner. How the received instruction is processed normally—for example, if the received instruction is an old instruction, the old instruction is executed normally—is common knowledge to those skilled in the art and will not be elaborated here. It is worth noting that the aforementioned decoding information and analog flag stored in the private register 220 will not be overwritten when the processor 110 performs a context switch. The aforementioned analog flag stored in the private register 220 will only be overwritten when the processor 110 executes another instruction. For example, if the other instruction is an old instruction, the instruction monitoring unit 210 generates an analog flag with a second value and updates the analog flag field of the private register 220; if the other instruction is a new instruction, the instruction monitoring unit 210 generates an analog flag with a first value and the decoding information of the other instruction, and updates the analog flag field and the field storing the decoding information of the received instruction in the private register 220.

[0048] like Figure 2A As shown, in the rearrangement buffer 240, EF1 represents the simulated identifier EF1 in the simulated identifier field of instruction entry 1, EF2 represents the simulated identifier EF2 in the simulated identifier field of instruction entry 2, EFN represents the simulated identifier EFN in the simulated identifier field of instruction entry N, and so on. The rearrangement buffer 240 contains an instruction submission unit 245. When the aforementioned microinstruction is in a await-submit (retire) state and meets the submission conditions, the instruction submission unit 245 will submit the aforementioned microinstruction.

[0049] If the simulation identifier of the micro-instruction is the first value (indicating that the received instruction is a new instruction), the instruction submission unit 245 will issue a system management interrupt (#SMI). In response to the system management interrupt, the processor 110 will enter the system management mode to simulate the execution of the received instruction via the system management mode entry 1142 as shown in Figure 1 During the simulation of the execution of the received instruction, intermediate operation results can be stored in the system management memory or in the special registers of the special register set 211. In one embodiment, the special register set 211 is part of the special hardware 116 as shown in Figure 1

[0050] The following describes in detail how the processor 110 handles the received instruction in the first embodiment with reference to Figure 1 , Figure 2A and Figure 3 .

[0051] Please refer to Figure 1 , Figure 2A and Figure 3 as well. As shown in Figure 3 , the instruction decoding unit 230 receives an instruction (S301) and determines whether the received instruction is a new instruction (S307). If the received instruction is a new instruction, the system 100 that executes the new instruction will simulate the execution of the received instruction (S313). The detailed description is as follows: the instruction decoding unit 230 first performs step S301.

[0052] In step S301, the instruction decoding unit 230 receives an instruction. As described above, the instruction decoding unit 230 receives the instruction from the instruction cache 202. Then, step S307 is performed.

[0053] In step S307, the instruction monitoring unit 210 determines whether the received instruction is a new instruction. Specifically, as shown in Figure 2A ​As shown, the instruction decode unit 230 decodes the received instruction to obtain decode information. The decode information includes a prefix, an escape code, an opcode, a length, a ModR / M, a source operand (register or memory), a destination operand (register or memory), etc. of the received instruction. The instruction pointer (EIP), the escape code, the opcode, the length, and the ModR / M of the received instruction are basic instruction information of the received instruction. The escape code, the opcode, and the ModR / M of the received instruction are basic decode information of the received instruction. Then, the instruction decode unit 230 generates micro-instructions according to the decode information and sends the generated micro-instructions to the rename unit 204. Meanwhile, the instruction decode unit 230 sends the decode information to the instruction monitor unit 210. The instruction monitor unit 210 determines whether the received instruction is a new instruction according to the decode information. For example, the opcodes of the new instructions supported only by the descendant processor of the processor 110 can be stored in a lookup table. The instruction monitor unit 210 can check whether the opcode of the received instruction is stored in the lookup table. If the opcode of the received instruction is stored in the lookup table, it means that the received instruction is a new instruction; otherwise, it means that the received instruction is not a new instruction. In an embodiment, the lookup table is stored in the instruction monitor unit 210. The instruction monitor unit 210 determines whether the received instruction is a new instruction according to the prefix, the escape code, and the opcode of the received instruction. In another embodiment, the instruction monitor unit 210 determines whether the received instruction is a new instruction according to the escape code, the opcode, and the ModR / M of the received instruction.

[0054] If the received instruction is not a new instruction (the result of the determination in step S307 is "No"), the processor 110 performs step S305 to normally process the received instruction. How to normally process the received instruction is common knowledge of those skilled in the art, and thus is not described here. If the received instruction is a new instruction (the result of the determination in step S307 is "Yes"), the processor 110 performs step S309.

[0055] In step S309, the processor 110 sets a simulation identification and prepares information needed for simulating execution of the received instruction. Specifically, after the instruction monitoring unit 210 determines that the received instruction is a new instruction, the instruction monitoring unit 210 generates a simulation identification having a first value and sends the simulation identification to the renaming unit 204 and the private register 220. The private register 220 stores the simulation identification in the simulation identification field thereof. The renaming unit 204, after receiving the simulation identification and the microinstruction, adds a simulation identification field to the microinstruction and stores the simulation identification in the simulation identification field of the microinstruction. In one embodiment, the received instruction is a no-operation microinstruction (NOP).

[0056] In step S309, when the simulation identification generated by the instruction monitoring unit 210 has the first value, the instruction decoding unit 230 also stores the decoding information and the execution environment information of the received instruction in the private register 220. The execution environment information refers to the state information of the processor 110 when the processor 110 executes the received instruction. The execution environment information includes the execution mode of the received instruction (i.e., the execution mode of the processor 110 when the processor 110 executes the received instruction). For example, the execution mode includes a real mode, a protected mode, a virtual 8086 mode (v8086 mode), a compatibility mode, a long mode, etc.

[0057] The renaming unit 204 then sends the microinstruction to the reorder buffer 240. As shown in FIG. 4, assume that the microinstruction is stored in entry 1 of the reorder buffer 240, then the value of EF1 in entry 1 is the first value. In one embodiment, the microinstruction does not need to be executed by the execution unit 206, so it does not need to be sent to the reservation station 205. Figure 2A

[0058] When the instruction commit unit 245 commits the microinstruction, since the value of EF1 in entry 1 storing the microinstruction is the first value, the instruction commit unit 245 issues a system management interrupt (#SMI). The microcode control unit 221 then performs step S311.

[0059] In step S311, the processor 110 enters a system management mode. Specifically, in response to the system management interrupt, the microcode control unit 221 executes the microcode stored in the system management mode entry of the microcode table 222. The microcode stored in the system management mode entry of the microcode table 222 is shown in FIG. 5. Figure 1 ​The system management interrupt entry 1142 (i.e., microcode handler for entering system management interrupt) is shown in FIG. 12. In the system management interrupt entry 1142, the processor 110 stores the emulation identification (value of the first number), the decode information of the received instruction, and the running environment information stored in the private register 220 into the system management memory, and then enters the system management mode (details will be described later in conjunction with Figure 4 FIG. 13).

[0060] Then, the processor 110 performs step S313. In step S313, the processor 110 emulates execution of the received instruction in the system management mode (details will be described later in conjunction with Figure 5 and Figure 6 FIG. 14).

[0061] Finally, the processor 110 performs step S315 to exit the system management mode. Specifically, the microcode control unit 221 executes the system management interrupt exit 1144 (i.e., microcode handler for exiting system management interrupt) as shown in FIG. 15 to exit the system management mode (details will be described later in conjunction with Figure 1 FIG. 16). Figure 7

[0062] It is noted that, in the actual operation of entering the system management mode in step S311 through the system management interrupt entry 1142, one skilled in the art can add some microcode to the microcode for entering the system management mode after issuing the system management interrupt (#SMI) to perform storing of the emulation identification, the decode information of the received instruction, and the running environment information into the system management memory (SMRAM), and ensure that these data / information will not be overwritten due to switching of the processor 110 to the system management mode. Furthermore, because the processor 110 entering the system management mode will access the system management memory in the known art, one skilled in the art can modify the microcode based on this part to achieve the purpose of accessing these data / information. Since these microcodes will be different depending on the processor version, one skilled in the art can write the corresponding microcode according to the actual situation. Similarly, in the actual operation of exiting the system management mode in step S315 through the system management interrupt exit 1144, one skilled in the art can add some microcode to the microcode for exiting the system management mode after calling the instruction for resuming from the system management mode (Resume from System management Mode, RSM) to perform storing of the emulation execution result from the system management memory into the architectural register to pass the emulation execution result to the application 130 or the operating system 120. Since these microcodes will be different depending on the processor version, one skilled in the art can write the corresponding microcode according to the actual situation.

[0063] ​In one embodiment, the processor 110 can only directly access the system management memory but not the memory (i.e., system memory, hereinafter) in the system management mode, and all interrupts are disabled in the system management mode. If the above-mentioned receive instruction needs to access the memory (e.g., when the source operand or the destination operand of the above-mentioned receive instruction is a memory operand), the instruction decode unit 230 decodes the above-mentioned receive instruction as a special microinstruction to check whether the memory accessed by the above-mentioned receive instruction can be accessed before entering the system management mode. Specifically, the instruction decode unit 230 sends the above-mentioned special microinstruction to the renaming unit 204. The renaming unit 204 sends the above-mentioned special microinstruction to the reorder buffer 240 and the reservation station 205. Then, the reservation station 205 sends it to the memory access unit 207. Upon receiving the above-mentioned special microinstruction, the memory access unit 207 does not perform a memory access operation but uses the above-mentioned special microinstruction to perform a permission check on the above-mentioned receive instruction to generate a check result. Specifically, the memory access unit 207 performs the permission check on the above-mentioned receive instruction by executing the above-mentioned special microinstruction to generate the check result. Then, the memory access unit 207 stores the above-mentioned check result in the private register 220. The above-mentioned check result includes a virtual address, a physical address, and an error code. If the above-mentioned memory cannot be accessed, the error code is a code indicating a specific error. For example, when the above-mentioned error code includes an error code indicating a page fault, it indicates that a page fault exception will occur if the above-mentioned memory is accessed. Unlike the previous embodiment, in this embodiment, the microcode control unit 221 also stores the above-mentioned check result saved in the private register 220 in the system management memory in step S311. In this way, after the processor 110 enters the system management mode, it can determine whether the above-mentioned memory can be accessed according to the error code in the above-mentioned check result. If the above-mentioned memory can be accessed, it accesses the above-mentioned memory according to the virtual address and the physical address in the above-mentioned check result to obtain the source operand or the destination operand of the above-mentioned receive instruction. If the above-mentioned memory cannot be accessed, the error code in the above-mentioned check result is written into the system management memory. After exiting the system management mode, the processor 110 enters the corresponding exception handling code according to the above-mentioned error code saved in the system management memory. In one embodiment, the above-mentioned special microinstruction is a memory pre-check microinstruction. The memory pre-check microinstruction is a memory read pre-check microinstruction (ld_tickle, i.e., load tickle) or a memory write pre-check microinstruction (st_tickle, i.e., store tickle).

[0064] In another embodiment, if the access unit 207 fails to access the memory after performing the privilege check on the received instruction using the special microinstruction described above, the processor 110 will directly enter the corresponding exception handling code according to the error code in the check result.

[0065] Figure 4 is a flowchart showing the entering system management mode according to an embodiment of the present application. Figure 4 corresponding to the system management mode entry 1142 shown in Figure 1 corresponding to the system management mode entry 1142 shown in Figure 4 As shown in

[0066] In step S401, the processor 110 disables the interrupt. As is known to those skilled in the art, the interrupt is disabled in the system management mode, and thus the interrupt is disabled in the present application in continuation of the architecture requirement. As to how to disable the interrupt, for example, the processor 110 clears the IF flag to disable the maskable interrupt, clears the TF flag to disable the single-step interrupt, and clears the DR7 to disable the breakpoint interrupt. Then, the processor 110 proceeds to step S403.

[0067] In step S403, the processor 110 judges whether the simulated flag is the first value. Specifically, the processor 110 judges whether the value saved in the simulated flag field of the private register 220 is the first value. If the judgment result is "no", step S405 is performed to execute the normal processing flow of entering the system management mode. As is known to those skilled in the art, the normal processing flow of entering the system management mode is not described here. If the judgment result is "yes", the processor 110 proceeds to step S407.

[0068] In step S407, the processor 110 issues an entering system management mode notification (Assert #smmact) to notify that the processor 110 has entered the system management mode. As to how to issue the entering system management mode notification, it is the common knowledge of those skilled in the art, and thus is not described here. Then, the processor 110 proceeds to step S409.

[0069] In step S409, the processor 110 stores the simulation identification, the decoding information of the received instruction, and the running environment information into the system management memory. Specifically, the processor 110 reads the simulation identification, the decoding information of the received instruction, and the running environment information from the private register 220, and stores the read simulation identification, the decoding information of the received instruction, and the running environment information into the system management memory. At the same time, the contents in the architectural register (i.e. the current state of the processor 110) are also stored into the system management memory. As mentioned above, when the received instruction needs to access the memory, the checking result of the received instruction is also stored in the private register 220. The processor 110 also reads the checking result from the private register 220, and stores the read checking result into the system management memory. The information stored in the system management memory is shown in Table 1 below.

[0070] Table 1

[0071]

[0072] Then, the processor 110 performs step S411, establishes a system management mode execution environment, and enters the system management mode. How to establish a system management mode execution environment and how to enter the system management mode are common knowledge to those skilled in the art, and thus will not be described here.

[0073] Then, the processor 110 simulates the execution of the received instruction in the system management mode (as shown in step S313). This will be described below in connection with Figure 3 Figure 5

[0074] Figure 5 is a flow chart showing the processing procedure of the simulator according to an embodiment of the present application. As mentioned above, the processor 110 runs the simulator 142 in the system management mode. As shown in Figure 5 In the system management mode, the processor 110 establishes a simulation running environment (S501), and then judges whether the simulation identification is the first value (S503). If the result of step S503 is "yes", it is further judged whether the received instruction has decoding abnormality (S507). If the result of step S507 is "no", the processor 110 generates at least one old instruction according to the basic decoding information of the received instruction (S509), and executes the at least one old instruction (S513). The details are described as follows: First, the processor 110 performs step S501.

[0075] ​​In step S501, the processor 110 sets up a simulation environment. Specifically, the processor 110 reads the simulation identification from the system management memory, receives decoding information of the received instruction, receives execution environment information of the received instruction, and receives information of the architectural register. When the received instruction needs to access the memory, the processor 110 further reads the checking result from the system management memory. In the following steps, the received instruction will be simulated using the information read above. Then, the processor 110 proceeds to step S503.

[0076] In step S503, the processor 110 determines whether the simulation identification is the first value. Specifically, the processor 110 determines whether the simulation identification read in step S501 is the first value. If the determination result is "No", the processor 110 proceeds to step S505. In step S505, the processor 110 performs a normal processing flow of the system management mode. The normal processing flow of the system management mode is common knowledge to those skilled in the art, and thus will not be described here. If the determination result of step S503 is "Yes", the processor 110 proceeds to step S507.

[0077] In step S507, the processor 110 determines whether there is a decoding exception. Specifically, the execution environment information of the received instruction read in step S501 includes the execution environment of the processor 110 when the received instruction is executed. The processor 110 determines whether the received instruction can be executed in the execution environment. For example, the execution environment information includes the operation mode of the processor 110. If the received instruction cannot be executed in the real mode when the operation mode is the real mode, the determination result of step S507 is "Yes". If the received instruction can be executed in the real mode, the determination result of step S507 is "No". In an embodiment, the processor 110 can find out in which execution environment the received instruction can be executed according to the operation code of the received instruction through a lookup table.

[0078] In an embodiment, the lookup table is stored in the basic input output system (BIOS). As known to those skilled in the art, the system 100 executing the new instruction is started by executing the basic input output system. The basic input output system includes a code for initializing the system management mode. When the system 100 executing the new instruction executes the code for initializing the system management mode, the lookup table is loaded into the system management memory. Then, the processor 110 can find out in which execution environment the received instruction can be executed according to the operation code of the received instruction through the lookup table.

[0079] When the processor 110 judges that the above-mentioned received instruction has a decoding exception (the result of the judgment in step S507 is "Yes"), step S511 is executed; otherwise, step S509 is executed. The following first describes step S511.

[0080] In step S511, the processor 110 writes an exception into the system management memory. It should be noted that the above-mentioned exception is the result of the simulation execution of the above-mentioned received instruction. Specifically, the processor 110 writes the above-mentioned exception (i.e. the result of the simulation execution) into an exception vector table in the system management memory. The exception vector table is used to save part of the information of the result of the simulation execution. The structure of the exception vector table is shown in Table 2 below. The exception vector table includes two fields: exception identification and exception number. The exception identification is used to save information about whether the simulation execution is successful. When the exception identification is a first exception value, it indicates that there is an exception (i.e. the simulation execution fails); when the exception identification is a second exception value, it indicates that there is no exception (i.e. the simulation execution succeeds). In an embodiment, the first exception value is 1 and the second exception value is 0. When the exception identification is the first exception value, the value of the exception number field is the number of the exception, which is usually represented by an integer value. Through the exception number, the processor 110 can find and execute the microcode processing program of the above-mentioned exception through the microcode control unit 221.

[0081] Table 2

[0082] Abnormality identification Abnormality number … …

[0083] In step S511, when the above-mentioned exception is a trap, the processor 110 updates the value of the instruction pointer of the above-mentioned received instruction saved in the system management memory to EIP+Length, so as to point the instruction pointer of the processor 110 to the next instruction set architecture instruction to be executed, wherein EIP is the value of the above-mentioned instruction pointer before the update, and Length is the length of the above-mentioned received instruction saved in the system management memory. The instruction pointer of the above-mentioned received instruction in the system management memory is the value stored in the storage space corresponding to the architecture register EIP. After step S511 is executed, the processor 110 executes step S519 to execute the exit system management mode instruction to execute the system management mode exit 1144 as shown in Figure 1

[0084] In step S507, when the result of the judgment is that there is no decoding exception (i.e. the result of the judgment in step S507 is "No"), the processor 110 executes step S509.

[0085] ​In step S509, the processor 110 generates at least one old instruction according to the basic decode information of the received instruction. As mentioned above, the basic decode information includes at least the escape code, the operation code, and the operand mode of the received instruction. In one embodiment, the processor 110 stores the at least one old instruction corresponding to the received instruction in a lookup table. Then, the processor 110 obtains the at least one old instruction from the lookup table according to the operation code of the received instruction. In one embodiment, when the received instruction includes an escape code, the processor 110 obtains the at least one old instruction from the lookup table according to the escape code and the operation code of the received instruction. In another embodiment, the processor 110 obtains the at least one old instruction from the lookup table according to the escape code, the operation code, and the operand mode of the received instruction.

[0086] It is worth noting that the at least one old instruction obtained from the lookup table does not include other decode information, such as the source operand and / or the destination operand of the received instruction. Therefore, the other decode information needs to be written into the at least one old instruction so that the at least one old instruction can simulate the execution of the received instruction. For example, the processor 110 writes the specific values of the source operand and / or the destination operand of the received instruction into the corresponding positions of the at least one old instruction. Then, the processor 110 can simulate the execution of the new instruction by executing the at least one old instruction. In one embodiment, the processor 110 writes the other decode information into the at least one old instruction according to the prefix of the received instruction.

[0087] In another embodiment, the at least one old instruction corresponding to the received instruction is stored in the basic input / output system (BIOS). As known to those skilled in the art, the system 100 executes the basic input / output system when it is started. The basic input / output system includes code for initializing the system management mode, and the at least one old instruction is loaded into the system management memory when the system 100 executes the code for initializing the system management mode. Then, the processor 110 can obtain the at least one old instruction from the system management memory according to the operation code of the received instruction.

[0088] Then, the processor 110 performs step S513. In step S513, the processor 110 executes the at least one old instruction. Specifically, the instruction decoding unit 230 decodes the at least one old instruction to obtain at least one micro instruction, and then the processor 110 executes the at least one micro instruction. In the process of executing the at least one old instruction, the processor 110 stores the intermediate operation result in the system management memory. In another embodiment, the processor 110 stores the intermediate operation result in the special register set 211. Since the processor 110 accesses the special register set 211 faster, the execution speed of the at least one old instruction can be accelerated.

[0089] In an embodiment, when the operand of the received instruction contains the new architecture register, the new architecture register is emulated by a special register or a system management memory. For example, when the descendant processor of the processor 110 contains a new architecture register with a bit width of 1024 bits, the processor 110 can emulate the new architecture register by using a continuous 1024-bit memory space in the system management memory. That is, when the received instruction accesses the new architecture register, the processor 110 actually accesses the continuous 1024-bit memory space in the system management memory. In another embodiment, when the descendant processor of the processor 110 contains a new architecture register with a bit width of 1024 bits, the processor 110 can emulate the new architecture register by using a special register with a bit width of 1024 bits in the special register set 211. That is, when the received instruction accesses the new architecture register, the processor 110 actually accesses the special register with a bit width of 1024 bits in the special register set 211. In another embodiment, when the special register set 211 only contains special registers with a bit width of 512 bits, two special registers with a bit width of 512 bits are needed to emulate one new architecture register with a bit width of 1024 bits. In summary, the present application does not limit this, and the processor 110 can use one or more special registers to emulate one new architecture register.

[0090] When the above-mentioned newly added architecture register is a destination operand of the above-mentioned received instruction, after the execution of the above-mentioned at least one old instruction (i.e. after the simulation execution of the above-mentioned received instruction), the processor 110 stores the simulation execution result of the above-mentioned received instruction into the above-mentioned special register or the above-mentioned system management memory. Moreover, the simulation execution result is kept in the above-mentioned special register or the above-mentioned system management memory and will not be overwritten during the process of the processor 110 entering / exiting the system management mode. In this way, when the processor 110 executes another instruction, and the other instruction is also a newly added instruction, and the above-mentioned newly added architecture register is a source operand of the above-mentioned other instruction, the processor 110 directly uses the simulation execution result stored in the above-mentioned special register or the above-mentioned system management memory when simulating the execution of the above-mentioned other instruction. It should be noted that the above-mentioned received instruction and the above-mentioned other instruction can be consecutive or not, and the present application does not limit this.

[0091] In the system management mode, the processor 110 can only access the system management memory, and cannot access the system memory in the normal way of accessing the memory. In an embodiment of the present application, a physical memory direct access interface is provided to realize the operation of accessing the memory in the system management mode. When the above-mentioned received instruction contains a memory operand, the above-mentioned memory operand can be accessed through the above-mentioned physical memory direct access interface. The steps of accessing the memory operand through the above-mentioned physical memory direct access interface are as follows:

[0092] Firstly, the processor 110 converts the virtual address of the above-mentioned memory operand into a physical address. Specifically, the processor 110 converts the virtual address of the above-mentioned memory operand into a physical address by accessing the page table through the above-mentioned physical memory direct access interface. The steps of converting the virtual address into the physical address are as follows: 1. reading out the page table base address saved in the architecture register CR3 from the system management memory; 2. performing page table query according to the page table base address and the virtual address, and obtaining the physical address after simulating the page table query process.

[0093] Secondly, the processor 110 reads the value of the memory operand according to the above-mentioned physical address, wherein the physical address is not in the system management memory. Specifically, the processor 110 reads the value of the memory operand according to the above-mentioned physical address through a model specific register (MSR). The specific steps are as follows:

[0094] Step 1, the processor 110 writes the address of the above-mentioned model specific register into a first register (ECX), and writes the above-mentioned physical address into a second register (EDX:EAX).

[0095] In step 2, the processor 110 executes a write model-specific register instruction (WRMSR) to store the value of the memory operand in the model-specific register. Specifically, after the processor 110 executes the write model-specific register instruction, the physical address is written into the model-specific register. Then, the processor 110 uses the physical address stored in the model-specific register to load the value of the memory operand from the system memory into the model-specific register by executing a load from physical address microinstruction (ld_phys).

[0096] In step 3, the processor 110 executes a read model-specific register instruction (RDMSR) to read the value of the memory operand from the model-specific register and store the value of the memory operand into the second register.

[0097] After step S513 is executed, the processor 110 executes step S515. In step S515, the processor 110 determines whether there is a runtime exception. If a runtime exception is generated during the execution of step S513, the determination result is "yes"; otherwise, the determination result is "no". When the determination result of S515 is "yes", the processor 110 executes step S511. Step S511 has been described above and will not be repeated here. When the determination result of S515 is "no", the processor 110 executes step S517.

[0098] In step S517, processor 110 writes the simulated execution result to system management memory. Specifically, first, processor 110 writes the second exception value (indicating no exception) to the exception identifier field of the exception vector table in system management memory, as shown in Table 2 above. Then, processor 110 writes the simulated execution result of the above-mentioned receive instruction to the area corresponding to the architecture register in system management memory. For example, if the simulated execution result of the above-mentioned receive instruction is to change the value of the architecture register ECX to 10H (hexadecimal number, the same below), then processor 110 writes the value 10H to the storage space corresponding to the architecture register ECX in system management memory. Finally, processor 110 updates the value of the instruction pointer of the above-mentioned receive instruction stored in system management memory to: EIP + Length, so as to point the instruction pointer of processor 110 to the next instruction set architecture instruction to be executed, where EIP is the value of the instruction pointer before the update, and Length is the length of the above-mentioned receive instruction. The instruction pointer of the above-mentioned receive instruction in system management memory is the storage space corresponding to the architecture register EIP. When exiting system management mode, the value in the space corresponding to the architecture register in system management memory will be written into the corresponding architecture register to send the simulated execution result of the new instruction to application 130 or operating system 120, which will be described in detail later.

[0099] Then, processor 110 executes step S519. In step S519, processor 110 executes the Resume from System Management mode instruction. After executing the Resume from System Management mode instruction, processor 110 will execute as follows: Figure 1 The microcode processing program for system management mode exit 1144 shown below will be combined with... Figure 7 It will be explained in detail.

[0100] Figure 6 This is an example illustrating the simulation of receiving instructions in system management mode according to an embodiment of the present invention. Figure 6 It demonstrates how to implement such a thing in the form of pseudocode. Figure 5 The simulated execution of the instruction receiving process shown is a specific implementation of the simulator.

[0101] like Figure 6 As shown, lines 1-20 contain the code for the simulator's main function, `simulator_start`. Lines 21-30 contain the code for the simulation function `Unsupport_X_handle`, which implements the new instruction functionality and includes at least one old instruction corresponding to the received instruction mentioned earlier. The main function `simulator_start` will be described first.

[0102] In the main function `simulator_start`, line 3 of the code is executed first. Line 3 completes. Figure 5 Step S501 involves the processor 110 establishing a simulated runtime environment. In line 3, the processor 110 uses the function `setup_simulator_env` to establish the simulated runtime environment. After executing line 3, the processor 110 saves the simulation flag, decoded instruction information, runtime environment information, architecture register information, and check results read from system management memory into the variable `env`. For example, in line 4, the value of the simulation flag is accessed via `env.emulation_flag`. Line 4 completes... Figure 5 In step S503, the processor 110 determines whether the analog identifier is the first value. If the result of the determination in line 4 is that the analog identifier is not the first value, then line 5 is executed. Line 5 completes. Figure 5 Step S505 functions as follows: processor 110 executes the normal processing flow of system management mode. In line 5, processor 110 enters the normal processing flow of system management mode by executing the function `exit_to_normal_SMM`. If the result of the judgment in line 4 is that the simulation flag is the first value, then lines 7-8 are executed. Lines 7-8 are then completed. Figure 5 The function of step S507 is for processor 110 to determine whether a decoding exception exists. In line 7, processor 110 checks and obtains the decoding exception value decode_excep of the received instruction by executing the function check_decode_excep. In line 8, processor 110 determines whether a decoding exception exists based on the value of decode_excep. If a decoding exception exists, line 9 is executed. Line 9 completes. Figure 5 In step S511, the processor 110 writes the exception to the system-managed memory. In line 9, the processor 110 uses the `set_exception` function to write the exception to the system-managed memory in the format described in Table 2. After executing line 9, the processor executes line 10, then jumps to line 18. In line 10, the processor 110 uses the `goto` instruction to jump to the location of label `out` (i.e., line 18). Then execution continues from line 18. Since line 18 only has label `out` and no code to execute, the processor 110 executes line 19. Line 19 is then completed. Figure 5 The function of step S519 is that processor 110 executes the instruction to exit system management mode. In line 19, processor 110 executes the instruction to exit system management mode through the function execute_rsm. Subsequently, processor 110 will execute as follows:Figure 1 The microcode for system management mode exit 1144 is shown.

[0103] If the result of the conditional statement in line 8 is that no decoding exception exists, then the code in line 12 will be executed. Line 12 completes. Figure 5 The function of step S509 is that the processor 110 generates at least one old instruction based on the basic decoding information of the received instruction. For example... Figure 6 As shown, in line 12, the at least one old instruction is retrieved from the `op_mapping` table using the opcode for receiving the instruction. A pointer `routine` represents this at least one old instruction, and its value is the address of the `Unsupport_X_handle` function. Then, line 13 is executed. Line 13 completes. Figure 5 The function of step S513 is that processor 110 executes at least one legacy instruction. When executing `routine()`, processor 110 actually executes the simulated function `Unsupport_X_handle` (described in detail later). After executing the `routine`, the simulation execution result is stored in `runtime_excep`. Then, the code on line 14 is executed. Line 14 completes. Figure 5 The function of step S515 is for processor 110 to determine whether a runtime exception exists. In line 14, processor 110 determines whether a runtime exception exists based on the value of runtime_excep, the result of the simulated execution. If a runtime exception exists, line 15 is executed. In line 14, processor 110 uses the function set_exception to store the runtime exception in the format described in Table 2 above into system management memory. Then, processor 110 executes line 16, jumping to line 18 via the goto instruction. As mentioned earlier, processor 110 will then execute line 19. The function of line 19 has been described previously and will not be repeated here.

[0104] The following describes the simulation function Unsupport_X_handle.

[0105] In the simulated function `Unsupport_X_handle`, lines 23-24 are executed first. These lines read the operand's value, storing it in the array `op`. In line 24, the processor uses the function `read_op` to read the operand. Specifically, `read_op` retrieves the operand's value from the previously mentioned `env` variable. Line 25 then completes... Figure 5the function of step S513, the processor 110 executes the at least one old instruction, i.e. the processor 110 emulates the execution of the received instruction. In line 25, op represents the operand of the received instruction, and operate with op means that the value of the operand of the received instruction is written into the at least one old instruction, and the at least one old instruction is executed. During the execution of line 25, when a runtime exception occurs, line 26 code completes the function of step S515, i.e. the processor 110 writes the exception into the system management memory; when no runtime exception occurs, line 27 code completes the function of step S517, i.e. the processor 110 writes the result of the emulation into the system management memory. Figure 5 the function of step S511, the processor 110 writes the exception into the system management memory; when no runtime exception occurs, line 26 code completes the function of step S517, i.e. the processor 110 writes the result of the emulation into the system management memory. Figure 5 the function of step S517, the processor 110 writes the result of the emulation into the system management memory. In line 26, the processor 110 stores the result of the emulation into the system management memory in the format of table 2 as described above by the function write_result_to_SMRAM. Line 27 code judges whether a runtime exception occurs during the execution of line 25, if a runtime exception occurs, line 28 code is executed to send the exception information to the main function; otherwise, line 29 code is executed to send the information of correct execution to the main function. In lines 28 and 29, the processor 110 sends the exception information or the information of correct execution to the main function simulator_start by the return instruction.

[0106] Figure 7 is a flow chart showing the exit from the system management mode according to an embodiment of the present application. Figure 7 i.e. the microcode handler corresponding to the system management mode exit 1144 as shown in Figure 1 the system management mode exit 1144 as shown in Figure 7 the system management mode exit 1144 as shown in

[0107] In step S701, the processor 110 judges whether the emulation identifier is the first value. Specifically, the processor 110 reads the emulation identifier from the system management memory, and then judges whether the read emulation identifier is the first value. If the emulation identifier is not the first value, the processor 110 executes step S703. In step S703, the processor 110 executes the normal processing flow of the exit from the system management mode. The normal processing flow of the exit from the system management mode is the common knowledge of those skilled in the art, and thus is not described here. If the emulation identifier is the first value, the processor 110 executes step S705.

[0108] In step S705, the processor 110 determines whether there is an anomaly in the simulation execution result. Specifically, the processor 110 reads the anomaly vector table shown in Table 2 above from the system management memory. If the value of the anomaly identifier field in the anomaly vector table is the first anomaly value, it indicates that there is an anomaly in the simulation execution result, and the judgment result is "yes"; if the value of the anomaly identifier field in the anomaly vector table is the second anomaly value, it indicates that there is no anomaly in the simulation execution result, and the judgment result is "no". If the judgment result is "no", the processor 110 executes step S707.

[0109] In step S707, processor 110 stores the simulated execution results stored in system management memory into the architecture register. As mentioned above, in Figure 5 In step S517, the processor 110 has written the simulated execution result of the aforementioned receive instruction into the area corresponding to the architecture register in the system management memory. In this step, the processor 110 stores the value in the area corresponding to the architecture register in the system management memory into the architecture register. This is equivalent to the processor 110 having completed executing the aforementioned receive instruction.

[0110] If the destination operand of the aforementioned received instruction is a new architecture register, since the processor 110's architecture register does not contain a new architecture register, the processor 110 will not store the simulated execution result from the region in system management memory simulating the new architecture register or the dedicated register simulating the new architecture register into the architecture register. As mentioned earlier, when the processor 110 simulates the execution of another new instruction, and the operand of the other new instruction is also the aforementioned new architecture register, the processor 110 can directly use the value stored in the region in system management memory simulating the aforementioned new architecture register or the value stored in the dedicated register simulating the aforementioned new architecture register to simulate the execution of the other new instruction.

[0111] Then, processor 110 executes step S709. In step S709, processor 110 enables interrupts. For example, processor 110 sets the IF flag to enable maskable interrupts, sets the TF flag to enable single-step interrupts, and sets DR7 to enable breakpoint interrupts. Then, processor 110 executes step S711.

[0112] In step S711, the processor 110 sends an exit system management mode notification (Deassert#smmact) to notify the chipset processor 110 that it has exited system management mode. Then, the processor 110 executes step S713 to exit system management mode.

[0113] When the processor 110 determines that there is an abnormality in the simulation execution result in step S705, it executes step S715.

[0114] In step S715, the processor 110 determines whether the type of the exception is a trap. Specifically, the processor 110 determines whether the exception in the simulation execution result is a trap according to the exception number in the exception vector table read from the system management memory in step S705. For example, when the exception identification is the first exception value and the exception number is 3 (the content in Table 2 is shown in Table 2-1 below), it indicates an overflow exception. The type of the overflow exception is a trap, so the determination result is "Yes". When the exception identification is the first exception value and the exception number is 0 (the content in Table 2 is shown in Table 2-2 below), it indicates a division error exception. The division error exception is a fault, not a trap, so the determination result is "No".

[0115] Table 2-1

[0116] Abnormality identification Abnormality number 1 3

[0117] Table 2-2

[0118] Abnormality identification Abnormality number 1 0

[0119] When the determination result in step S715 is "No", the processor 110 executes steps S717, S719, and S721. Among them, steps S717 and S719 are the same as steps S709 and S711 respectively, and will not be described here. Step S721 is described below.

[0120] In step S721, the processor 110 executes the microcode processing program of the exception. Specifically, the processor 110 determines whether an exception has occurred according to the exception identification in the exception vector table stored in the system management memory. If an exception has occurred, the processor 110 executes the microcode processing program of the exception according to the exception number stored in the above-mentioned exception vector table. That is, the microcode processing program of the exception corresponding to the above-mentioned exception number is executed. For example, when the exception identification in the exception vector table stored in the system management memory is the first exception value, it indicates that there is an exception in the simulation execution result. If the exception number in the exception vector table at this time is 0, it indicates that the above-mentioned exception is a division error, and the processor 110 will execute the microcode processing program of the division error.

[0121] In step S715, when the determination result is "Yes", that is, the type of the exception in the simulation execution result is a trap, the processor 110 executes steps S723, S725, S727, and S729. Among them, steps S723, S725, S727 are the same as steps S707, S709, S711 respectively, and will not be described here. Step S729 is described below.

[0122] In step S729, processor 110 executes the microcode handler for the exception. For example, when an exception occurs in the simulation execution result, and the exception is an overflow exception, processor 110 executes the microcode handler for the overflow exception.

[0123] [Second Embodiment]

[0124] In the second embodiment, the processor 110 passes the emulation identifier to the pipeline, and the instruction monitoring unit determines whether the received instruction is a new instruction based on the machine code of the received instruction from the instruction cache. The following is in conjunction with... Figure 2B , Figure 2B1 and Figures 3-7 The second embodiment is described.

[0125] Figure 2B Chinese numbering and Figure 2A The same module has the same function as Figure 2A The corresponding modules have the same function, so they will not be described again here. The second embodiment is described below. Figure 2B Compared with the first embodiment Figure 2A The differences.

[0126] like Figure 2B As shown, the instruction monitoring unit 210B directly receives instructions from the instruction cache 202B. Then, the instruction monitoring unit 210B decodes the received instructions to generate decoding information. Next, the instruction monitoring unit 210B determines whether the received instruction is a new instruction based on the decoding information and generates a simulated identifier. Then, the instruction monitoring unit 210B sends the simulated identifier to the renaming unit 204 and the private register 220B. When the simulated identifier is the first value, the instruction monitoring unit 210B also stores the decoded information and runtime environment information into the private register 220B. The following is in conjunction with... Figure 2B1 The instruction monitoring unit 210B is described in detail.

[0127] like Figure 2B1 As shown, the instruction monitoring unit 210B includes an instruction parsing unit 2101B and an instruction judgment unit 2102B. The instruction parsing unit 2101B decodes the received instruction from the instruction cache 202B to generate decoding information. Then, the instruction parsing unit 2101B sends the decoded information to the instruction judgment unit 2102B. The instruction judgment unit 2102B determines whether the received instruction is a new instruction based on the decoded information and generates a simulated identifier. Then, the instruction judgment unit 2102B sends the simulated identifier to the private register 220B and the renaming unit 204. The private register 220B stores the simulated identifier. When the simulated identifier is a first value, the private register 220B also stores the decoded information of the received instruction from the instruction parsing unit 2101B.

[0128] In the second embodiment, in Figure 3 In step S307, unlike the first embodiment, the processor 110 directly decodes the received instruction through the instruction monitoring unit 210B and determines whether the received instruction is a new instruction based on the decoding information. In the second embodiment, Figure 3 Other steps and Figures 4-7 The steps in this embodiment are the same as those in the first embodiment, and will not be repeated here.

[0129] In summary, unlike the first embodiment, in this embodiment, the instruction monitoring unit 210B directly reads the machine code of the received instruction from the instruction cache 202B. Then, the instruction monitoring unit 210B parses the read machine code and generates decoding information. Next, the instruction monitoring unit 210B determines whether the received instruction is a new instruction based on the decoding information. When the received instruction is a new instruction, the instruction monitoring unit 210B generates a simulated identifier with a first value. Then, the instruction monitoring unit 210B sends the generated simulated identifier to the renaming unit 204 and sends the decoding information to the private register 220B. Compared to the first embodiment, this embodiment directly parses the machine code from the instruction cache 202B, eliminating the need to modify the instruction decoding unit 230B, thus making it relatively easy to implement.

[0130] [Third Embodiment]

[0131] In the third embodiment, the processor 110 does not pass the analog identifier into the pipeline, and the instruction monitoring unit determines whether the received instruction is a new instruction based on the instruction information of the received instruction from the instruction decoding unit. The following is in conjunction with... Figure 2C as well as Figures 3-7 The third embodiment is described.

[0132] Figure 2C Chinese numbering and Figure 2A The same module has the same function as Figure 2A The corresponding modules have the same function, so they will not be described in detail here. The difference between the third embodiment and the first embodiment is that in the third embodiment, the instruction monitoring unit 210C does not send the emulation identifier to the renaming unit 204C. The third embodiment will now be described in detail. Figure 2C Compared with the first embodiment Figure 2A The differences.

[0133] like Figure 2CAs shown, the instruction monitoring unit 210C judges whether the received instruction is a new instruction, and generates a simulation identification. Then, the instruction monitoring unit 210C stores the simulation identification into the private register 220. When the simulation identification is the first value, the private register 220 also stores the decoding information of the received instruction and the running environment information from the instruction decoding unit 230.

[0134] The instruction decoding unit 230 decodes the received instruction, and generates decoding information. The instruction decoding unit 230 generates a micro instruction according to the decoding information. As known by those skilled in the art, when the received instruction is not an old instruction, the micro instruction contains an unknown instruction identification (UD) with a value of the first value. Then, the renaming unit 204C receives the micro instruction from the instruction decoding unit 230, performs renaming processing on the micro instruction, and sends the micro instruction to the reorder buffer 240C. When the instruction issuing unit 245C issues the micro instruction, if the unknown instruction identification in the micro instruction is the first value, an unknown instruction exception is generated. In response to the unknown instruction exception, the microcode control unit 221C executes a microcode processing program of the unknown instruction exception. In the microcode processing program of the unknown instruction exception, the processor 110 judges whether the simulation identification in the private register 220 is the first value. If the simulation identification in the private register 220 is the first value, the processor 110 issues a system management interrupt. The subsequent processing flow is the same as that of the first embodiment, and thus is not described herein.

[0135] Different from the first embodiment, in the third embodiment, in the steps S307 and S309 of the first embodiment, the instruction monitoring unit 210C does not send the generated simulation identification to the renaming unit 204C. Figure 3 Different from the first embodiment, in the third embodiment, in the steps S307 and S309 of the first embodiment, the instruction monitoring unit 210C does not send the generated simulation identification to the renaming unit 204C. Figure 3 The other steps of the third embodiment and the steps in the first embodiment are the same as those of the first embodiment, and thus are not described herein. Figures 4-7 The other steps of the third embodiment and the steps in the first embodiment are the same as those of the first embodiment, and thus are not described herein.

[0136] In summary, different from the first and second embodiments, in the present embodiment, after the instruction monitoring unit 210C generates the simulation identification, the instruction monitoring unit 210C only sends the simulation identification to the private register 220, and does not send the simulation identification to the renaming unit 204C and the reorder buffer 240C. Since the simulation identification is not contained in the instruction entry of the reorder buffer 240C, the instruction issuing unit 245C can only issue the unknown instruction exception according to the unknown instruction identification. In the microcode processing program of the unknown instruction exception, the processor 110 issues the system management interrupt according to the simulation identification stored in the private register 220. Compared with the first and second embodiments, in the present embodiment, the renaming unit and the reorder buffer do not need to be modified, and thus the present embodiment is relatively easy to implement.

[0137] [Fourth Embodiment]

[0138] In the fourth embodiment, the processor 110 does not pass the analog identifier into the pipeline. The instruction monitoring unit determines whether the received instruction is a new instruction based on the machine code of the received instruction from the instruction cache. The following is in conjunction with... Figure 2D , Figure 2D1 as well as Figures 3-7 The fourth embodiment is described.

[0139] Figure 2D Chinese numbering and Figure 2A The same module has the same function and Figure 2A The corresponding modules have the same function, so they will not be described in detail here. The difference between the fourth embodiment and the third embodiment is that in the fourth embodiment, the instruction monitoring unit 210D directly obtains the received instruction from the instruction cache 202D and determines whether the received instruction is a new instruction. Figure 2D Modules 204D, 240D, 245D, and 221D are respectively with Figure 2C Modules 204C, 240C, 245C, and 221C are the same, and will not be described again here. The fourth embodiment will be described in detail below. Figure 2D Compared with the first embodiment Figure 2C The differences.

[0140] like Figure 2D As shown, the instruction monitoring unit 210D directly receives instructions from the instruction cache 202D. Then, the instruction monitoring unit 210D decodes the received instructions to generate decoding information. Next, the instruction monitoring unit 210D determines whether the received instruction is a new instruction based on the decoding information and generates a simulated identifier. Then, the instruction monitoring unit 210D sends the simulated identifier to the private register 220D. When the simulated identifier is the first value, the instruction monitoring unit 210D also stores the decoding information and runtime environment information into the private register 220D. The following is a combination of... Figure 2D1 The instruction monitoring unit 210D is described in detail.

[0141] like Figure 2D1As shown, the instruction monitoring unit 210D includes an instruction parsing unit 2101D and an instruction judging unit 2102D. The instruction parsing unit 2101D decodes the received instruction from the instruction cache 202D to generate decoding information. Then, the instruction parsing unit 2101D sends the decoding information to the instruction judging unit 2102D. The instruction judging unit 2102D judges whether the received instruction is a new instruction according to the decoding information and generates a simulation mark. Then, the instruction judging unit 2102D sends the simulation mark to the private register 220D. The private register 220D stores the simulation mark. When the simulation mark is the first value, the private register 220D also stores the decoding information of the received instruction from the instruction parsing unit 2101D.

[0142] In the fourth embodiment, in the step S307, unlike the third embodiment, the processor 110 directly decodes the received instruction by the instruction monitoring unit 210D and judges whether the received instruction is a new instruction according to the decoding information. In the fourth embodiment, Figure 3 the other steps of the method 300 and the steps of the method 400 are the same as the third embodiment, and thus are not described here. Figure 3 the other steps of the method 300 and the steps of the method 400 are the same as the third embodiment, and thus are not described here. Figures 4-7 the other steps of the method 300 and the steps of the method 400 are the same as the third embodiment, and thus are not described here.

[0143] In summary, similar to the third embodiment, compared with the first embodiment and the second embodiment, in the present embodiment, the instruction monitoring unit does not need to send the simulation mark to the renaming unit and the reorder buffer, so the renaming unit and the reorder buffer do not need to be modified, and thus the present embodiment is relatively easy to implement. In addition, unlike the third embodiment, in the present embodiment, the instruction monitoring unit 210D directly reads the machine code of the received instruction from the instruction cache 202D. Then, the instruction monitoring unit 210D parses the received machine code to generate decoding information. Then, the instruction monitoring unit 210D judges whether the received instruction is a new instruction according to the decoding information. When the received instruction is a new instruction, the instruction monitoring unit 210D generates a simulation mark with a first value. Then, the instruction monitoring unit 210D sends the decoding information to the private register 220D. Compared with the third embodiment, in the present embodiment, the machine code from the instruction cache 202D is directly parsed, and thus the instruction decoding unit 230D does not need to be modified, and thus the present embodiment is relatively easy to implement.

[0144] It is worth noting that the above four embodiments are all achieved by modifying the existing code for entering and exiting the system management mode to implement the function of entering and exiting the emulator 142. In another embodiment, the system 100 for executing the new instruction can also be added with special code for entering and exiting the system management mode, and a new system management interrupt number can be defined. Then, the newly added special code for entering the system management mode is executed by calling the newly added system management interrupt number. In the newly added special code for entering the system management mode, the processor 110 writes a special entry flag with a first value into the system management memory, and then enters the system management mode. The processor 110 executes the emulator 142 in the system management mode to simulate the execution of the new instruction. After simulating the execution of the new instruction, the emulator 142 determines whether the special entry flag in the system management memory is the first value. If the special entry flag is the first value, the emulator 142 executes the newly added special code for exiting the system management mode. In an embodiment, the emulator 142 executes the newly added special code for exiting the system management mode by calling an instruction (call) or a jump instruction (jump).

[0145] All the functions described in the above first embodiment, second embodiment, third embodiment and fourth embodiment can be implemented based on the above newly added special code for entering and exiting the system management mode. In order to achieve better execution effect, when implementing the functions of the above four embodiments based on the above newly added special code for entering and exiting the system management mode, the steps of determining whether the simulation flag is the first value in Figure 4 and Figure 7 may be deleted. Because in the special code for entering and exiting the system management mode, the normal system management mode processing code does not need to be considered. For example, steps S403 and S405 in Figure 4 may be deleted, and steps S701 and S703 in Figure 7 may be deleted. In addition, step S409 of Figure 4 needs to be modified to "store the simulation flag, the special entry flag, the decoding information of the received instruction and the running environment information into the system management memory". Figure 5 Step S519 of Figure 6 needs to be modified to "execute the newly added special code for exiting the system management mode when the special entry flag is the first value; otherwise, execute the exit system management mode instruction". Figure 6 line 19 needs to be modified to "if (newEntryFlag == 1) execute_newExit(); else execute_rsm();", where newEntryFlag is the special entry flag, and execute_newExit() represents executing the newly added special code for exiting the system management mode.

[0146] According to the above description, the modified Figure 4 is the processing flow of the code for entering the system management mode specially; the modified Figure 7 is the processing flow of the code for exiting the system management mode specially; the modified Figure 5 is the processing flow of the emulator 142 when using the code for entering and exiting the system management mode specially; the modified Figure 6 is an example of emulating the newly added instruction when using the code for entering and exiting the system management mode specially. The modified Figure 4 step S409 and the modified Figure 5 step S519 are described respectively as follows.

[0147] In the modified Figure 4 step S409, the processor 110 stores the emulation identification, the special entry identification, the decoding information of the received instruction and the running environment information into the system management memory. Specifically, the processor 110 generates the emulation identification with the first value and the special entry identification, and writes the generated emulation identification and special entry identification into the system management memory. In addition, the processor 110 reads the decoding information of the received instruction and the running environment information from the private register 220, and writes the read decoding information of the received instruction and the running environment information into the system management memory.

[0148] In the modified Figure 5 step S519, when the special entry identification is the first value, the processor 110 executes the newly added code for exiting the system management mode specially; otherwise, the processor 110 executes the exit system management mode instruction. Specifically, the processor 110 reads the special entry identification from the system management memory, and judges whether the read special entry identification is the first value. When the special entry identification is the first value, the processor 110 executes the newly added code for exiting the system management mode specially; otherwise, the processor 110 executes the exit system management mode instruction. It is worth noting that the function of the modified Figure 6 line 19 is just the function of this step.

[0149] In summary, compared with using the original code for entering and exiting the system management mode, when using the code for entering and exiting the system management mode specially, the skilled person in the art can optimize the code for entering and exiting the system management mode, and thus can achieve higher execution efficiency.

[0150] Figure 8 is a flowchart showing the process of executing the newly added instruction according to an embodiment of the present application. As shown in Figure 8As shown in FIG. 9, the processor 110 receives an instruction (S901), and judges whether the received instruction is a new instruction (S903). When the received instruction is a new instruction, the processor 110 generates a simulation identifier (S905). Then, the processor 110 issues a system management interrupt according to the simulation identifier (S907). In response to the system management interrupt, the processor 110 enters a system management mode (S909), simulates execution of the received instruction in the system management mode, generates a simulation execution result (S911), and stores the simulation execution result in a system management memory (S912).

[0151] In the embodiment, the step S801 is the same as the step S301 of the method shown in FIG. 3; the step S803 is the same as the step S307 of the method shown in FIG. 3; the step S805 is the same as the step S311 of the method shown in FIG. 3; the step S807 is the same as the step S313 of the method shown in FIG. 3; and the step S809 is the same as the step S305 of the method shown in FIG. 3. Therefore, the steps S801, S803, S805, S807 and S809 will not be described herein. Figure 8 Figure 3 In the embodiment, the step S901 is the same as the step S301 of the method shown in FIG. 3; the step S903 is the same as the step S307 of the method shown in FIG. 3; the step S909 is the same as the step S311 of the method shown in FIG. 3; the step S912 is the same as the step S517 of the method shown in FIG. 5; the step S913 is the same as the step S305 of the method shown in FIG. 3. Therefore, the steps S901, S903, S909, S912 and S913 will not be described herein. The steps S905, S907 and S911 will be described below. Figure 3 Figure 3 Figure 3 Figure 3

[0152] Figure 9 As shown in FIG. 9, the processor 110 receives an instruction (S901), and judges whether the received instruction is a new instruction (S903). When the received instruction is a new instruction, the processor 110 generates a simulation identifier (S905). Then, the processor 110 issues a system management interrupt according to the simulation identifier (S907). In response to the system management interrupt, the processor 110 enters a system management mode (S909), simulates execution of the received instruction in the system management mode, generates a simulation execution result (S911), and stores the simulation execution result in a system management memory (S912). Figure 9

[0153] In the embodiment, the step S901 is the same as the step S301 of the method shown in FIG. 3; the step S903 is the same as the step S307 of the method shown in FIG. 3; the step S909 is the same as the step S311 of the method shown in FIG. 3; the step S912 is the same as the step S517 of the method shown in FIG. 5; the step S913 is the same as the step S305 of the method shown in FIG. 3. Therefore, the steps S901, S903, S909, S912 and S913 will not be described herein. The steps S905, S907 and S911 will be described below. Figure 9 Figure 3 Figure 3 Figure 3 Figure 5 Figure 3

[0154] In the step S905, the processor 110 generates a simulation identifier. Specifically, when the instruction monitoring unit 210 judges that the received instruction is a new instruction, the simulation identifier is generated. For details of generating the simulation identifier, please refer to the foregoing description of the step S313 of the method shown in FIG. 3. Figure 2A Figure 2B ​​​​​​​​​​​​​Figure 2C and Figure 2D , and refer to the description of step S309 of Figure 3 above, which will not be repeated here.

[0155] In step S907, the processor 110 issues a system management interrupt according to the simulation identification. For how to issue the system management interrupt according to the simulation identification, refer to the description of steps S403 and S407 above, which will not be repeated here.

[0156] In step S911, the processor 110 simulates the execution of the received instruction in the system management mode to generate a simulation execution result. Specifically, the processor 110 generates at least one old instruction according to the basic decoding information of the received instruction, and then simulates the execution of the received instruction by executing the at least one old instruction to generate a simulation execution result. For more detailed description, refer to the description of steps S509 and S513 of Figure 5 above, which will not be repeated here.

[0157] Figure 10 is a flowchart showing the execution of a newly added instruction according to another embodiment of the present application. As shown in Figure 10 , the processor 110 receives an instruction (S1001), and determines whether the received instruction is a newly added instruction according to the operation code of the received instruction (S1003). When the received instruction is a newly added instruction, the processor 110 stores the basic decoding information of the received instruction in a private register (S1005). Then, the processor 110 enters the system management mode (S1006), and simulates the execution of the received instruction according to the basic decoding information stored in the private register in the system management mode (S1007).

[0158] In Figure 10 , step S1001 is the same as step S301 of Figure 3 ; step S1003 is the same as step S307 of Figure 3 ; step S1006 is the same as step S311 of Figure 3 ; step S1007 is the same as step S313 of Figure 3 ; and step S1009 is the same as step S305 of Figure 3 . Therefore, the above steps will not be repeated here. The following describes step S1005.

[0159] In step S1005, the processor 110 stores the basic decoding information of the received instruction in a private register. For detailed implementation, refer to the description of Figure 2A , Figure 2B ,​Figure 2C and Figure 2D the description of the instruction monitoring units 210, 210B, 210C and 210D in Figure 3 and the description of step S309 of

[0160] The method and system for executing the newly added instruction provided by the present application can implement the instruction newly added by the later generation processor on the former generation processor without modifying the micro-architecture of the processor, thereby greatly reducing the workload for design, test and the like, and saving a large amount of cost.

[0161] The above merely provides the preferred embodiments of the present application, but not for the purpose of limiting the scope of the present application. Any person skilled in the art, without departing from the spirit and scope of the present application, can make further improvements and changes on the basis of the present application. Therefore, the protection scope of the present application shall be subject to the scope defined by the claims of the present application.

Claims

1. A method of executing an add new instruction, the method comprising: Comprising: receiving an instruction; determining whether the received instruction is a new instruction, the new instruction being an instruction that cannot be recognized by a processor and is supported by a descendant processor of the processor; and when the received instruction is the new instruction: generating a simulation identifier with a first value, wherein the simulation identifier with the first value indicates that the received instruction is a to-be-simulated instruction; issuing a system management interrupt according to the simulation identifier with the first value; entering a system management mode in response to the system management interrupt, and simulating execution of the received instruction in the system management mode to generate a simulation execution result; and storing the simulation execution result in a system management memory.

2. The method of claim 1, when the received instruction is the new instruction, further comprising: The received instruction is decoded into microinstructions, wherein the microinstruction including the simulation identifier; and issuing the system management interrupt according to the simulation identifier in the microinstruction.

3. The method of claim 2, when the received instruction is the new instruction, further comprising: when the microinstruction is submitted, initiating the system management interrupt according to the simulation identifier of the microinstruction.

4. The method of claim 2, wherein the new instruction is executed by: when the received instruction is the new instruction, the microinstruction is a no-operation microinstruction.

5. The method of executing a new instruction of claim 2, wherein, when the received instruction is the new instruction and the received instruction needs to access a memory, the microinstruction is a special microinstruction, and the method of executing the new instruction further comprises: when the simulation identifier of the special microinstruction is the first value, performing a permission check on the received instruction using the special microinstruction to generate a check result.

6. The method of claim 5, when the received instruction is the new instruction, further comprising: storing the check result in a private register; and reading the check result from the private register and storing the read check result in the system management memory.

7. The method of executing an add new instruction of claim 5, wherein, the check result includes a virtual address, a physical address, and an error code.

8. The method of claim 1, when the received instruction is the new instruction, further comprising: storing the simulation identifier in a simulation identifier field of a private register; and entering the system management mode according to the simulation identifier in the private register.

9. The method of claim 1, when the received instruction is the new instruction, further comprising: storing basic instruction information and running environment information of the received instruction in the system management memory; and simulating execution of the received instruction according to the basic instruction information and the running environment information stored in the system management memory in the system management mode.

10. The method of claim 9, when the received instruction is the new instruction, further comprising: decoding the received instruction to obtain the basic instruction information of the received instruction; storing the basic instruction information of the received instruction in a private register; and reading the basic instruction information from the private register and storing the read basic instruction information in the system management memory.

11. The method of executing an add new instruction of claim 9, wherein, the basic instruction information includes an instruction pointer, an escape code, an operation code, a length, and an operand mode of the received instruction, and the running environment information includes a running mode.

12. The method of claim 1, when the received instruction is the new instruction, further comprising: exiting the SMM mode according to the simulated execution result in the SMM.

13. The method of executing an add new instruction of claim 12, wherein, The simulated execution result includes an exception identifier, and when the exception identifier is a first exception value, exiting the SMM mode according to the simulated execution result in the SMM further comprises: reading an exception number from the simulated execution result in the SMM; determining an exception type according to the exception number; and when the exception type is a trap, using the simulated execution result stored in the SMM to restore values stored in architectural registers, and executing a microcode handler corresponding to the exception number.

14. The method of executing a new instruction of claim 12, wherein, The simulated execution result includes an exception identifier, and when the exception identifier is a first exception value, exiting the SMM mode according to the simulated execution result in the SMM further comprises: reading an exception number from the simulated execution result in the SMM; determining an exception type according to the exception number; and when the exception type is not a trap, executing a microcode handler corresponding to the exception number.

15. The method of executing a new instruction of claim 12, wherein, The simulated execution result includes an exception identifier, and when the exception identifier is a second exception value, exiting the SMM mode according to the simulated execution result in the SMM comprises: using the simulated execution result stored in the SMM to restore values stored in architectural registers; and exiting the SMM mode.

16. A system that executes an add new instruction, the system comprising: comprising: a SMM; and an instruction monitoring unit, determining whether a received instruction is a new instruction, the new instruction being an instruction that cannot be recognized by a processor and is supported by a descendant processor of the processor, when the received instruction is the new instruction, the system generating a simulated identifier with a first value, issuing a SMI according to the simulated identifier with the first value, in response to the SMI, entering a SMM mode, and simulating execution of the received instruction in the SMM mode to generate a simulated execution result, storing the simulated execution result in the SMM, wherein the simulated identifier with the first value indicates that the received instruction is a to-be-simulated instruction.

17. The system of claim 16, further comprising: an instruction decode unit coupled to the instruction monitoring unit, the instruction decode unit decoding the received instruction into micro-instructions, wherein the microinstruction including the simulated identifier; and an instruction submission unit, issuing the SMI according to the simulated identifier in the microinstruction.

18. The system for executing an add new instruction of claim 17, wherein, when the instruction submission unit submits the microinstruction, the instruction submission unit initiates the SMI according to the simulated identifier in the microinstruction.

19. The system for executing an add new instruction of claim 17, wherein, when the received instruction is the new instruction, the microinstruction is a no-operation microinstruction.

20. The system of claim 17, further comprising: a memory access unit, when the received instruction is the new instruction, if the received instruction needs to access a memory, the microinstruction is a special microinstruction, and when the simulated identifier in the special microinstruction is the first value, the memory access unit performs a permission check on the received instruction using the special microinstruction to generate a check result.

21. The system of claim 20, further comprising: a private register, the access unit stores the check result into the private register; and a microcode control unit, the microcode control unit reads the check result from the private register and stores the read check result into the system management memory.

22. The system for executing an add new instruction of claim 20, wherein, The check result includes a virtual address, a physical address and an error code.

23. The system of claim 16, further comprising: a private register coupled to the instruction monitoring unit, the private register including a simulation identification field; wherein The system of executing new instructions enters the system management mode according to the simulation identification in the private register.

24. The system for executing an add new instruction of claim 16, wherein, When the received instruction is a new instruction, the system of executing new instructions stores the basic instruction information of the received instruction and the running environment information of the received instruction into the system management memory; and in the system management mode, the system of executing new instructions simulates the execution of the received instruction according to the basic instruction information and the running environment information stored in the system management memory.

25. The system of claim 24, further comprising: a private register coupled to the instruction monitoring unit; and a decoding unit coupled to the instruction monitoring unit and the private register, the decoding unit decodes the received instruction to obtain the basic instruction information of the received instruction; the decoding unit stores the basic instruction information of the received instruction into the private register; the system of executing new instructions reads the basic instruction information from the private register and stores the read basic instruction information into the system management memory.

26. The system for executing an add new instruction of claim 24, wherein, The basic instruction information includes an instruction pointer, an escape code, an operation code, a length and an operand mode of the received instruction, and the running environment information includes a running mode.

27. The system for executing an add new instruction of claim 16, wherein, When the received instruction is a new instruction, the system of executing new instructions exits the system management mode according to the simulation execution result in the system management memory.

28. The system for executing an add new instruction of claim 27, wherein, The simulation execution result includes an exception identification, when the exception identification is a first exception value, the system of executing new instructions reads an exception number from the simulation execution result in the system management memory and determines an exception type according to the exception number; when the exception type is a trap, the system of executing new instructions uses the simulation execution result stored in the system management memory to restore values stored in an architectural register and executes a microcode handler corresponding to the exception number.

29. The system for executing an add new instruction of claim 27, wherein, The simulation execution result includes an exception identification, when the exception identification is a first exception value, the system of executing new instructions reads an exception number from the simulation execution result in the system management memory and determines an exception type according to the exception number; When the exception type is not a trap, the system of executing new instructions executes a microcode handler corresponding to the exception number.

30. The system for executing an add new instruction of claim 27, wherein, The simulation execution result includes an exception identification, when the exception identification is a second exception value, the system of executing new instructions uses the simulation execution result stored in the system management memory to restore values stored in an architectural register and exits the system management mode.

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