Memory access method, memory address allocation method and device

Abstract

The present application discloses a memory access method, a memory address allocation method and a device, and belongs to the field of information technology. The method comprises: a computer device obtains a memory access request, the memory access request comprises target memory address information, the target memory address information comprises an address bit and a length bit, wherein the address bit is used to carry the target address of the memory to be accessed, and the length bit is used to carry the length of the memory allowed to be accessed starting from the set address; the computer device accesses the memory based on the memory access request. The present application sets the address bit and the length bit in the target memory address information, so that the computer device can access the memory according to the target address of the memory and the length of the memory, enriches the function of the memory address information, and realizes the full and efficient use of the memory address information.

Description

Technical Field

[0001] The present application relates to the field of information technology, and in particular to a memory access method, a memory address allocation method and a device. Background Art

[0002] Computer equipment generally includes a central processing unit (CPU), memory and software. The CPU can access the memory through the bus.

[0003] When accessing the memory, the CPU sends a memory access request (such as a read request or a write request) to the memory through the bus, and the memory access request includes memory address information. For example, in a computer device that supports the 64-bit instruction set architecture (Architecture64, Arch64), the total length of the memory address information is 64 bits. Due to the need for actual memory space and the limitations of hardware conditions, the lower 48 bits of the 64 bits are usually used to carry the accessed memory address, that is, the lower 48 bits are effective address bits.

[0004] However, in existing memory access methods, the high bits (eg, high 16 bits) of the memory address information are usually idle address bits, resulting in a single function of the memory address information and an inability to fully and efficiently utilize the memory address information. Summary of the invention

[0005] The present application provides a memory access method, a memory address allocation method and a device, which can solve the problems in the related art that the address information has a single function and the memory address information cannot be fully and efficiently utilized.

[0006] In a first aspect, a memory access method is provided for a computer device, the method comprising:

[0007] Obtain a memory access request, which includes target memory address information, and the target memory address information includes address bits and length bits, the address bits are used to carry the target address of the accessed memory, and the length bits are used to carry the length of the memory allowed to be accessed starting from the set address; access the memory based on the memory access request.

[0008] In the present application, by setting the length bit and the address bit in the target memory address information, the computer device can access the memory according to the target address of the memory and the length of the memory, thereby enriching the function of the memory address information and realizing the full and efficient use of the memory address information.

[0009] In a first possible implementation of the first aspect, the length of the address bit is 48 bits, and the length of the length bit is less than or equal to 16 bits; or, the length of the address bit is a first length, and the length of the length bit is a second length, the first length is less than 48 bits, and the sum of the first length and the second length is less than or equal to 64 bits; or, the length of the address bit is 48 bits, and the length of the length bit is greater than 16 bits.

[0010] In the present application, the length of the address bit and the length of the length bit can be flexibly set according to actual needs, which enriches the configuration method of the address bit and the length bit in the memory address information and improves the utilization rate of the memory address information.

[0011] In combination with the first aspect and the first possible implementation of the first aspect, in the second possible implementation of the first aspect, accessing the memory based on the memory access request includes: after determining that the target memory length is less than or equal to the length carried by the length bit, sending a memory access request to the memory, the target memory length is the sum of the length from the set address to the target address and the access length. The access length is the length of the memory actually accessed (also called the length of the memory expected to be accessed). The memory access request can carry the access length, or the computer device can obtain the access length based on a preset rule.

[0012] In combination with the second possible implementation of the first aspect, in a third possible implementation of the first aspect, after determining that the target memory length is greater than the length carried by the length bits, sending a memory access request to the memory is prohibited.

[0013] In combination with the third possible implementation of the first aspect, in a fourth possible implementation of the first aspect, after determining that the target memory length is greater than the length carried by the length bits, an exception message is issued.

[0014] In combination with the first aspect and any possible implementation methods of the first to fourth aspects of the first aspect, in a fifth possible implementation method of the first aspect, obtaining a memory access request includes: generating a memory access request based on a received address setting instruction, the address setting instruction including target memory address information; or, generating a memory access request based on the generated target memory address information; or, receiving a memory access request.

[0015] In a second aspect, a memory address allocation method is provided for a computer device, the method comprising: generating memory address information, the memory address information comprising: an address bit and a length bit, the address bit is used to carry a target address of the memory, and the length bit is used to carry the length of the memory allowed to be accessed starting from a set address; and allocating the memory address information. The setting method of the address bit and the length bit in the target memory address information can refer to the setting method of the address bit and the length bit in the first possible implementation method of the first aspect.

[0016] In a third aspect, a memory access device is provided for use in a computer device, the memory access device having the function of implementing the memory access method behavior in the first aspect. The memory access device includes at least one module, the at least one module being used to implement the memory access method provided in the first aspect.

[0017] In a fourth aspect, a memory address allocation device is provided for use in a computer device, wherein the memory address allocation device has the function of implementing the memory address allocation method described in the second aspect. The memory address allocation device includes at least one module, and the at least one module is used to implement the memory address allocation method described in the second aspect.

[0018] In a fifth aspect, a computer device is provided, comprising: a processor and a memory;

[0019] The memory is used to store a computer program, wherein the computer program includes program instructions;

[0020] The processor is used to call the computer program to implement the memory access method as described in the first aspect, or to implement the memory address allocation method as described in the second aspect. The computer device can be a hardware device inside the CPU, such as a memory controller or a memory management unit, etc., or it can be software running in a CPU, such as a software stub.

[0021] Optionally, the computer device may be a security check device for checking the security of a memory access request by checking whether the target memory length is within a range of memory lengths allowed to be accessed as indicated by the length bits.

[0022] In a sixth aspect, a computer-readable storage medium is provided, which stores a computer program, and the computer program includes at least one code segment, which can be executed by a computer device to control the computer device to execute the memory access method described in the first aspect or the memory address allocation method described in the second aspect.

[0023] In a seventh aspect, a chip is provided, the chip comprising a programmable logic circuit and / or program instructions, and when the chip is running, it implements any method described in the first aspect and its possible implementation methods or in the second aspect.

[0024] The beneficial effects of the technical solution provided by this application include at least:

[0025] By setting the address bit and the length bit in the target memory address information, the computer device can access the memory according to the target address of the memory and the length of the memory. While enriching the function of the memory address information, it also enriches the method for the computer device to access the memory, thereby achieving full and efficient use of the memory address information; and the length of the address bit and the length of the length bit can be flexibly set according to actual needs, thereby enriching the configuration method of the address bit and the length bit in the memory address information; in addition, the computer device can perform an exception check according to the target memory length in the memory access request and the length carried by the length bit in the memory access request, and after the exception check passes, the memory is accessed based on the memory access request. After the exception check fails, the memory access request is prohibited to access the memory, thereby preventing the occurrence of memory access violations, thereby improving the security of memory access. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a structural schematic diagram of a computer device provided in an embodiment of the present application;

[0027] Figure 2 It is a structural schematic diagram of memory address information provided in the related art;

[0028] Figure 3 It is a structural schematic diagram of another memory address information provided in the related art;

[0029] Figure 4 It is a flowchart of a memory access method provided in an embodiment of the present application;

[0030] Figure 5 It is a schematic diagram of the structure of target memory address information provided by an embodiment of the present application;

[0031] Figure 6 is a schematic diagram of the structure of another target memory address information provided in an embodiment of the present application;

[0032] Figure 7 It is a structural diagram of another target memory address information provided in an embodiment of the present application;

[0033] Figure 8 It is a schematic diagram of the structure of another target memory address information provided in an embodiment of the present application;

[0034] Fig. 9 It is a structural diagram of another target memory address information provided by an embodiment of the present application;

[0035] Fig.10 It is a flowchart of a memory address allocation method provided in an embodiment of the present application;

[0036] Fig.11 It is a structural diagram of a memory access device provided in an embodiment of the present application;

[0037] Fig.12 It is a structural schematic diagram of a memory address allocation device provided in an embodiment of the present application;

[0038] Fig.13 It is a block diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0040] Figure 1 Schematic diagram of a computer device provided in an embodiment of the present application. The computer device may be a server, a smart phone, a tablet computer, a laptop computer or a desktop computer. Figure 1 As shown, the computer device includes a central processing unit 101 and a memory 102. The central processing unit 101 and the memory 102 are connected via a bus.

[0041] The CPU 101 is the computing core and control core of the computer device. The CPU 101 is used to execute computer instructions and process data. Specifically, the CPU 101 can read data in the memory 102, and then perform calculations or other processing on the read data, or the CPU 101 can write data to the memory 102.

[0042] The memory 102 is an address space that the CPU 101 can directly address, and is used to store programs or temporarily process data of the CPU 101. The memory 102 can be a random access memory (RAM), a cache, a linear addressable flash memory (Flash), or an input / output (I / O) module.

[0043] The bus is used to transmit data information, memory address information and control information. The bus includes a data bus (DataBus, DB), an address bus (Address Bus, AB) and a control bus (Control Bus, CB). The data bus is a channel for data information transmission between the central processing unit 101 and the memory 102. The data bus width is related to the amount of data that can be transmitted in one data transmission. The address bus is used to transmit memory address information, and the central processing unit 101 can access the specified storage unit in the memory 102 according to the memory address information transmitted in the address bus. The address bus width is related to the size of the address space that the central processing unit 101 can find in the memory 102. For example, if the number of address buses is 32, the address space that the central processing unit 101 can find in the memory 102 is 4 gigabytes (GB). Or for example, if the number of address buses is 64, the address space that the central processing unit 101 can find in the memory 102 is 16384 petabytes (PB). The control bus is used to transmit control information. The control bus width is related to the control capability of the CPU 101 over the memory 102 .

[0044] To facilitate the readers’ understanding, Figure 1 Take as an example to schematically illustrate the data reading and writing process in memory access. When the central processor 101 needs to read data in the memory 102, the central processor 101 generates a read request, which includes: the memory address information of the data and the control signal for the read operation. The central processor 101 sends the memory address information to the memory 102 through the address bus, and sends the control signal for the read operation to the memory 102 through the control bus; based on the memory address information from the central processor 101 and the control signal for the read operation, the memory 102 searches for the data to be read; after finding the data to be read, the memory 102 sends the read data back to the central processor 101 through the data bus. When the central processor 101 needs to write data to the memory 102, the central processor 101 generates a write request, which includes: the data to be written, the memory address information of the data, and the control signal for the write operation. The central processing unit 101 sends the data to be written to the memory 102 through the data bus, sends the memory address information of the data to be written to the memory 102 through the address bus, and sends the control signal for performing a write operation to the memory 102 through the control bus; based on the control signal for performing a write operation from the central processing unit 101, the data to be written and the memory address information of the data, the memory 102 writes the data to be written into the position corresponding to the memory address information.

[0045] At present, in computer devices supporting Arch64, the memory address information transmitted on the address bus carries the memory address of the memory, so the memory in the computer device can read or write data according to the memory address information. Due to the needs of the actual memory space of the computer device and the limitations of hardware conditions, usually not all address bits in the memory address information are used to carry the memory address, but part of the address bits (i.e., the effective address bits) in the 64 bits are used to carry the memory address, and then the remaining address bits (i.e., the free address bits) are fixedly filled, for example, all filled with "0" or all filled with "1". That is, in a computer device supporting Arch64, only part of the address bits can be used to complete the addressing of the address space, and the remaining address bits cannot be used.

[0046] For example, in a computer device supporting Arch64, the total length of memory address information is 64 bits. Figure 2 As shown in FIG. 1 , the memory address information includes 48 bits of effective address bits and 16 bits of free address bits. Alternatively, as Figure 3 As shown, the memory address information includes 39 effective address bits and 25 idle address bits. The effective address bits are used to carry the accessed memory address, and the idle address bits are all filled with "0" or all filled with "1".

[0047] However, in the related art, when memory address information is used to access memory, the high-order address bits (for example, the high 16 bits or the high 25 bits) in the memory address information are usually set as idle address bits, and the low-order address bits (for example, the low 48 bits or the low 39 bits) are set as valid address bits, resulting in a single function of the memory address information, making it impossible to effectively utilize the high-order address bits of the memory address information, resulting in a waste of resources.

[0048] Figure 4 is a flow chart of a memory access method provided by an embodiment of the present application. The method is applied to Figure 1 In the computer device shown. Figure 4 As shown, the method includes:

[0049] Step 401: A computer device obtains a memory access request, which includes target memory address information. Figure 5 As shown, the target memory address information includes an address bit and a length bit, wherein the address bit is used to carry the target address of the memory to be accessed, and the length bit is used to carry the length of the memory allowed to be accessed starting from the set address.

[0050] Among them, the target address is used to indicate the starting position of the memory to be accessed. Its format can be the same as the format of the memory address in the traditional memory address information. The set address is the starting address of the length of the memory allowed to be accessed, and the set address can be a pre-specified address, such as an address assigned by the system by default. The aforementioned target address can be the same as the set address, or it can be different from the set address. The length of the memory allowed to be accessed refers to the size of the memory allowed to be accessed, that is, a length threshold, and the length is usually expressed in a single byte. For example, the length of the memory allowed to be accessed is 16, which means that access to 16 bytes of memory is allowed. The length of the memory allowed to be accessed can also be expressed in multiple bytes, such as 16 bytes. In this case, 16 means that access to 16*16=256 bytes of memory is allowed, and it is described in bytes by default. It should be noted that in the embodiments of the present application, the different lengths carried in the length bit can also represent different meanings. For example, when the length carried by the length bit is 1, the target memory address information is the same as the address indicated by the target address, so the target memory address information is used to represent a specific address; when the length carried by the length bit is greater than 1, the target memory address information is used to represent a continuous storage space starting from the target address; when the length carried by the length bit is 0, since there is no address with a length of 0 in actual implementation, it means that the target address in the target memory address information is an illegal address.

[0051] The length of the address bit and the length of the length bit can be combined in many ways. The embodiments of the present application take the following combinations as examples for illustration:

[0052] In the first combination, the length of the address bit is 48 bits, and the length of the length bit is less than or equal to 16 bits. In this way, the length bit occupies the idle address bits in the traditional memory address information, realizing the effective use of the idle address bits. Figure 6 As shown, Figure 6 This is a schematic structure of a target memory address information provided in an embodiment of the present application. In the target memory address information, the length of the address bit is 48 bits and the length bit is 13 bits.

[0053] In the second combination, the length of the address bit is the first length, the length of the length bit is the second length, the first length is less than 48 bits, and the sum of the first length and the second length is less than or equal to 64 bits. In this way, the length of the address bit can be less than the length of the effective address bit in the traditional memory address information, and the length bit occupies the idle address bits and effective address bits in the traditional memory address information. The length of the address bit and the length of the length bit can be pre-configured according to actual conditions, thereby realizing flexible configuration of the address bit and the length bit, and further realizing effective use of the memory address information. Figure 7 As shown, Figure 7It is a schematic structure of a target memory address information provided in an embodiment of the present application. In the target memory address information, the length of the address bit is 34 bits and the length bit is 24 bits.

[0054] In the third combination, the length of the address bit is 48 bits, and the length of the length bit is greater than 16 bits. In the third combination, for computer devices that support Arch64, since the total length of the address bit and the length bit is greater than 64 bits, it is necessary to configure the extension bit, which is an additional data bit set on the basis of 64 bits. In this way, the length bit occupies the idle address bit in the traditional memory address information, and also occupies the extension bit, thereby realizing the effective use of the idle address bit. Moreover, due to the setting of the extension bit, the length of the length bit can be longer, thereby supporting access to large-capacity memory, and can achieve access to large-capacity memory with one memory access request. Figure 8 As shown, Figure 8 It is a schematic structure of a target memory address information provided in an embodiment of the present application. In the target memory address information, the length of the address bit is 48 bits, the length bit is 80 bits, and the 64th to 127th bits of the length bit are extension bits.

[0055] In the fourth combination, the length of the address bit is the first length, the length of the length bit is the second length, the first length is less than 48 bits, and the sum of the first length and the second length is greater than 64 bits. In this way, the length of the address bit can be less than the length of the effective address bit in the traditional memory address information, while the length bit occupies the free address bits and effective address bits in the traditional memory address information, and also occupies the extension bit. The length of the address bit and the length of the length bit can be pre-configured according to actual conditions, thereby achieving flexible configuration of the address bit and the length bit, and further achieving effective use of the memory address information. Moreover, due to the setting of the extension bit, the length of the length bit can be longer, thereby supporting access to large-capacity memory, and achieving access to large-capacity memory with one memory access request. Fig. 9 As shown, Fig. 9 It is a schematic structure of a target memory address information provided in an embodiment of the present application. In the target memory address information, the length of the address bit is 40 bits, the length of the length bit is 40 bits, and bits 64 to 79 of the length bit are extension bits.

[0056] Among them, the extension bits involved in the third combination mode and the fourth combination mode can be implemented by address object-based extension (AOE). AOE does not change the address bus width of the computer device, but uses the bit extension of the register in the computer device to implement the extension of the length bit in the target memory address information. In addition, for computer devices supporting Arch64, when AOE cannot be used and the required occupied memory length has exceeded the range that the length bit can represent, the length bit can only be filled with "1", which means that the length bit is invalid at this time, and the traditional memory access method can be referred to when accessing the memory. For example, in a computer device supporting Arch64, a memory address exceeding 64 kilobytes (K) can no longer be represented in a 16-bit length bit (in the Arch64 computer device, a single-byte method is used by default to represent the length of the memory address. If a multi-byte method is used to represent the length of the memory address, the length of the memory address can be longer), and the length bit will be filled with "1", and the length bit is invalid at this time. In one achievable manner, when the required memory length is greater than the maximum length that the length bit can carry, the computer device issues a prompt message, where the prompt message is used to prompt the computer device to use AOE to extend the length bit.

[0057] In the embodiments of the present application, the length of the address bit and the length of the length bit can be flexibly set according to actual needs, which enriches the configuration of the address bit and the length bit in the memory address information and improves the utilization rate of the memory address information. For ease of explanation, the subsequent embodiments of the present application are described by taking the length of the address bit as 48 bits as an example.

[0058] There are many ways to obtain the target memory address information in the aforementioned memory access request. The embodiments of the present application take the following ways as examples for explanation:

[0059] The first acquisition method generates a memory access request based on a received address setting instruction, where the address setting instruction includes target memory address information.

[0060] In an optional manner, the address setting instruction is obtained by programming. This method is generally applied to situations where the target address is known. For example, if a programmer needs to access a known target address, the target memory address information can be set in this way. The programmer can use assembly language or C language and other programming languages ​​to write a program to obtain an address setting instruction containing the target memory address information. In another optional manner, the address setting instruction can also be automatically generated from other devices or applications (or clients). For example, the address setting instruction can be generated by a compiler of an application. After the address setting instruction is generated, the computer device receives the address setting instruction accordingly.

[0061] For example, an address setting instruction can be expressed as:

[0062] Long addr = 0x8************ (code 1).

[0063] Among them, long represents a long integer type, addr represents the constructed target memory address information, 0x8 represents the length carried by the length bit in the target memory address information, * represents a hexadecimal number (0-F), and the number of * is 12, indicating that the length of the address bit in the target memory address information in hexadecimal is 48 bits.

[0064] According to code 1, the target address of the accessed memory is 0x************, and the length of the memory allowed to be accessed is 0x8 bytes.

[0065] For another example, the address setting instruction can be expressed as:

[0066] Long double addr = 0x4444444************ (code 2).

[0067] Among them, double long represents a 128-bit extra-long integer type, and 0x4444444 represents the length carried by the length bit in the target memory address information.

[0068] According to code 2, the target address of the memory to be accessed is 0x************, and the length of the memory allowed to be accessed is 0x4444444 bytes. At this time, the length bit in the target memory address information occupies the extension bit, which can be implemented using AOE. For details, please refer to the extension bit in the third combination method or the fourth combination method mentioned above.

[0069] The second acquisition method is to generate a memory access request based on the generated target memory address information. The process of generating a memory access request based on the generated target memory address information by the computer device may include the following steps:

[0070] A1. The computer device generates target memory address information.

[0071] The method of generating the target memory address information includes two methods: directly generating the target memory address information and generating new target memory address information based on known target memory address information. The embodiments of the present application respectively describe the two methods:

[0072] In the first method, assuming that in the target memory address information to be generated, the target address in the address bit is p, the methods for generating the target memory address information may include the following:

[0073] Method 1: The computer device generates the target memory address information by software compilation. For example, the code used to generate the target memory address information during software compilation can be expressed as:

[0074] char p

[20] (code 3).

[0075] Among them, char represents the character data type, and 20 represents the length that the software automatically fills in the length bit in the target memory address information during compilation.

[0076] According to Code 3, Code 3 indicates that a global memory space is generated, and the address space range of the target address in the target memory address information is 0x************-0x#############, where 0x############=0x************+20.

[0077] Method 2: The computer device generates the target memory address information when the software instrumentation code is running. For example, when the software instrumentation code is running, the code for generating the target memory address information can be expressed as:

[0078] char p

[20] (code 4).

[0079] Here, 20 indicates the length that is automatically filled in by the software when the instrumentation code is running.

[0080] According to Code 4, Code 4 indicates that a local temporary memory space is generated, and the address space range of the target address in the target memory address information is 0x************-0x#############, where 0x############=0x************+20.

[0081] It should be noted that the codes of the aforementioned method 1 and method 2 are similar, but the locations are different, which determines that the aforementioned method 1 can be executed by the compiler running in the computer device to perform length bit filling at compile time, and method 2 can be executed by the compiler inserted code at runtime.

[0082] Mode 3: The computer device generates the target memory address information through the system kernel. For example, after receiving the address application request for the address space, the system kernel of the computer device generates the target memory address information in response to the application request. The code used by the system kernel to generate the target memory address information can be expressed as:

[0083] char*p=(char*)malloc(20) (Code 5).

[0084] Among them, char* represents a character pointer, the malloc function is a dynamic memory allocation function, and 20 represents the length of the space requested by the dynamic memory allocation function from the system kernel.

[0085] According to Code 5, the address space range of the target address in the target memory address information is 0x************-0x#############, where 0x############=0x************+20.

[0086] Alternatively, the code used by the system kernel to generate the target memory address information can also be expressed as:

[0087] char*p=new char

[20] (code 6).

[0088] Among them, new char[] means applying for a heap space.

[0089] According to Code 6, the address space range of the target address in the target memory address information is 0x************-0x#############, where 0x############=0x************+20.

[0090] In the above-mentioned method 1, 0x************ is used as an example to illustrate the pre-assigned starting address. For example, the starting address can be a set address corresponding to the length carried by the length bit. The starting address is usually a default address. In actual implementation, the starting address can also be specified by other methods, which is not limited in the embodiment of the present application.

[0091] In an embodiment of the present application, the target memory address information can be generated when the software is compiled, or the target memory address information can be generated when the software instrumentation code is running, or the target memory address information can be generated by the system kernel of the computer device. Since the length of the length bits in the generated target memory address information can be set according to actual needs, and the length bits in the target memory address information can occupy the free address bits in the traditional memory address information or can occupy the extension bits and the free address bits in the traditional memory address information, the memory address information can be effectively utilized while enriching the configuration method of the length bits.

[0092] In the second method, it is assumed that in the known target memory address information, the target address in the address bit is p (in order to distinguish it from the target address p1, it is referred to as the known address p in the following text), the known address p is: 0x************, the type is char*, and the length carried in the length bit is 20; in the new target memory address information, the target address in the address bit is p1. The methods of generating new target memory address information based on the known target memory address information may include the following:

[0093] Method 1: Generate new target memory address information by defining a known address.

[0094] For example, the code that defines the known address to generate new target memory address information can be expressed as:

[0095] char*p1=&p[0](code 7).

[0096] According to code 7, the address of the known address &p[0] is assigned to the target address p1. At this time, the length of the target address p1 is the length 1 of the char type variable, and the target address p1 = 0x1************.

[0097] For another example, the code that defines a known address to generate a new target memory address information can also be expressed as:

[0098] char*p1=p+1(code 8).

[0099] According to code 8, the target address p1 increases by 1 relative to the known address p, which reduces the length of the length bit in the new target memory address information by 1. At this time, the target address p1=0x13############. Among them, 0x############=0x************+1.

[0100] For another example, the code that defines a known address to generate a new target memory address information can also be expressed as:

[0101] long*p1=(long*)p(code 9).

[0102] Among them, long* represents a pointer to a long integer type.

[0103] According to code 9, the target address p1 is the address pointing to a long variable. Assuming sizeof(long) is 8, the length filled with the length bit of the target address p1 should be an integer multiple of 8 and cannot exceed the length carried by the length bit of the known address p. Therefore, the length of the target address p1 is filled with 16, and the target address p1 = 0x10************.

[0104] For another example, suppose the code for defining a new type of target address from a known address is:

[0105] int*p1=&p[0](code 10).

[0106] Among them, int* represents a pointer of integer type.

[0107] According to code 10, the length of &p[0] is 1. Assuming sizeof(int) is 4, since the length 1 of &p[0] is less than sizeof(int), code 10 is wrong.

[0108] Method 2: The central processing unit of the computer device generates new target memory address information when it is running. For example, when the central processing unit of the computer device is running, the code for generating new target memory address information can be expressed as:

[0109] ADD AX0, AX1, #1 (code 11).

[0110] Code 11 is an operation code, AX0 and AX1 represent two address registers, and the code is specifically expressed as: AX0 = AX1 + 1. Assuming that the known address AX1 = 0x14************, according to code 11, the target address AX0 increases by 1 relative to the known address AX1, so that the length bit in the new target memory address information decreases by 1. At this time, the target address AX0 = 0x13#############. Among them, 0x############=0x************+1.

[0111] In the embodiment of the present application, the target memory address information can be generated by defining a known address, or the target memory address information can be generated by the central processing unit of the computer device during operation. Therefore, the methods for generating the memory address information are diverse, making the generation of the memory address information more flexible.

[0112] A2. The computer device generates a memory access request based on the generated target memory address information. The memory access request may be a read request or a write request, and the type of the memory access request is generated according to a specific memory access scenario. In an optional manner, the memory access request also includes: an access length, which is the length of the memory actually accessed (also referred to as the length of the memory expected to be accessed). For example, the memory access request is a write request, and the access length is 4 bytes. Then the memory access request indicates that data with a length of 4 bytes needs to be written starting from the position indicated by the target address. In another optional manner, the computer device can obtain the access length based on a preset rule. For example, for a certain type of memory access request, the default access length for each access is 1 byte.

[0113] The third acquisition method is to receive a memory access request.

[0114] Optionally, the computer device may receive a memory access request from another device or application (or client). The manner in which another device or application generates a memory access request may refer to the first acquisition manner or the second acquisition manner described above.

[0115] In an embodiment of the present application, the target memory address information in the memory access request includes an address bit and a length bit. The address bit is used to carry the target address of the memory to be accessed, and the length bit is used to carry the length of the memory allowed to be accessed starting from the target address. By setting the length bit and the address bit in the memory address information, the computer device can access the memory according to the target address of the memory and the length of the memory, thereby enriching the function of the memory address information and realizing full and efficient utilization of the memory address information.

[0116] Step 402: The computer device accesses the memory based on the memory access request.

[0117] In one implementation, the computer device may directly use a memory access request to access the memory. The access process may refer to the aforementioned Figure 1 The access process. For example, the memory access request is a write request, and the access length is 4 bytes. Then the computer device writes 4-byte data from the position indicated by the target address based on the memory access request; for another example, the memory access request is a read request, and the access length is 5 bytes. Then the computer device reads 5-byte data from the position indicated by the target address based on the memory access request.

[0118] In another implementation, the computer device may perform an exception check on the memory access request, and after the exception check passes, the memory is accessed based on the memory access request. After the exception check fails, the memory access request is prohibited from being used to access the memory. By performing an exception check on the memory access request, the computer device can access the memory after the exception check passes, thereby preventing the occurrence of memory access violations, thereby improving the security of memory access.

[0119] As mentioned above, the memory access request also includes an access length, or the computer can obtain the access length based on a preset rule, and the computer device can determine the target memory length based on the access length, and the target memory length is the sum of the length from the set address to the target address and the access length. The computer device can perform an exception check based on the target memory length. For example, the exception check process includes:

[0120] B1. After the target memory length is less than or equal to the length carried by the length bit, it is determined that the exception check has passed.

[0121] That is, after determining that the target memory length is less than or equal to the length carried by the length bits, a memory access request is sent to the memory.

[0122] In actual implementation, the memory access request carries multiple types of codes, and the computer device can perform an exception check by checking the code corresponding to the target memory address information in the memory access request. There can be multiple codes corresponding to the target memory address information, and the embodiments of this application are described by taking the following as examples:

[0123] In the first method, assuming that the address of the char type is p, the length carried by the length bit in the target memory address information is 20, and the code corresponding to accessing the memory is:

[0124] char c1=p

[10] (code 12).

[0125] According to code 12, p

[10] indicates the 10th byte in the address pointed to by the access address p, that is, the target address is the 10th byte in the address pointed to by the address p. Assuming &p[0] is the set address, that is, the address of the 0th byte in the address pointed to by the address p, the length from the set address to the target address is 10. Assuming that this type of code indicates that the length of the accessed memory is 1 byte, that is, the access length is 1 byte, then the target memory length is 10+1=11. Since the target memory length 11 is less than the length 20 carried by the length bit, it can be determined that the exception check has passed, and the computer device can access the memory based on the memory access request.

[0126] In the second method, assuming that the address of the char type is p1, the length carried by the length bit in the target memory address information is 10, and the code corresponding to accessing the memory is:

[0127] char c1=*(p1+5)(code 13).

[0128] According to code 13, *(p1+5) indicates the 5th byte in the address pointed to by the access address p1, that is, the target address is the 5th byte in the address pointed to by the address p1. Assuming that p1 is a set address, indicating the address of the 0th byte in the address pointed to by the address p1, the length from the set address to the target address is 5. Assuming that this type of code indicates that the length of the accessed memory is 1 byte, that is, the access length is 1 byte, then the target memory length is 5+1=6. Since the target memory length 6 is less than the length 10 carried by the length bit, it can be determined that the exception check has passed, and the computer device can access the memory based on the memory access request.

[0129] In the third method, assuming that the length bit in the target memory address information carries a length of 24, the code corresponding to accessing the memory is:

[0130] LDR AX0,[AX1,#0x10](code 14).

[0131] According to code 14, AXx represents an address register. In Arch64, if AOE is not enabled, it is 64 bits. [AX1,#0x10] means accessing from the 16th byte of the address pointed to by AX1, that is, the target address is the 16th byte in the address pointed to by address AX1. Assuming that the set address is the address of the 0th byte in the address pointed to by AX1, the length from the set address to the target address is 16. The access length is the length of AX (that is, 8 bytes), so the target memory length is 16+8=24, that is, 24. Since the target memory length 24 is equal to the length 24 carried by the length bit, it can be determined that the exception check has passed, and the computer device can access the memory based on the memory access request.

[0132] B2. After the target memory length is greater than the length carried by the length bit corresponding to the target address, it is determined that the exception check has failed.

[0133] That is, after determining that the target memory length is greater than the length carried by the length bits corresponding to the target address, sending a memory access request to the memory is prohibited.

[0134] Similar to B1, the computer device can perform an exception check by checking the code corresponding to the target memory address information in the memory access request. The embodiments of the present application are described by taking the following examples:

[0135] In the first method, assuming that the address of the char type is p, the length carried by the length bit in the target memory address information is 20, and the code corresponding to accessing the memory is:

[0136] char c1=p

[20] (code 15).

[0137] According to code 15, p

[20] indicates the 20th byte in the address pointed to by the access address p, that is, the target address is the 20th byte in the address pointed to by the address p. Assuming &p[0] is the set address, that is, the address of the 0th byte in the address pointed to by the address p, the length from the set address to the target address is 20. Assuming that this type of code indicates that the length of the accessed memory is 1 byte, that is, the access length is 1 byte, then the target memory length is 20+1=21. Since the target memory length 21 is greater than the length 20 carried by the length bit, it can be determined that the exception check has not passed, and the computer device is prohibited from using the memory access request to access the memory.

[0138] In the second method, assuming that the address of the char type is p1, the length carried by the length bit in the target memory address information is 10, and the code corresponding to accessing the memory is:

[0139] char c1=*(p1+11)(code 16).

[0140] According to code 16, *(p1+11) indicates that the 11th byte in the address pointed to by the access address p1 is accessed, that is, the target address is the 11th byte in the address pointed to by the address p1. Assuming that p1 is the set address, that is, the address of the 0th byte in the address pointed to by the address p1, the length from the set address to the target address is 11. Assuming that this type of code indicates that the accessed length is 1 byte, that is, the access length is 1 byte, the target memory length is 11+1=12. Since the target memory length 12 is greater than the length 10 carried by the length bit, it can be determined that the exception check has not passed, and the computer device is prohibited from using the memory access request to access the memory.

[0141] In the third method, assuming that the length bit in the target memory address information carries a length of 24, the code corresponding to accessing the memory is:

[0142] LDR AX0,[AX1,#0x15](code 17).

[0143] According to code 17, [AX1, #0x15] indicates that the access starts from the 21st byte of the address pointed to by AX1, that is, the target address is the 21st byte in the address pointed to by address AX1. Assuming that the set address is the address of the 0th byte in the address pointed to by AX1, the length from the set address to the target address is 21, and the access length is the length of AX (i.e. 8 bytes), then the target memory length is 21+8=29. Since the target memory length 29 is greater than the length 24 carried by the length bit, it can be determined that the abnormality check has not passed, and the computer device is prohibited from using the memory access request to access the memory.

[0144] In one embodiment, after determining that the target memory length is greater than the length carried by the length bit, the computer device issues an exception message. For example, the exception message can be an error message or an alarm message. For example, after determining that the target memory length is greater than the length carried by the length bit, the computer device issues an error message. For example, the error message can be expressed as "ERROR!". For another example, after determining that the target memory length is greater than the length carried by the length bit, the computer device issues an alarm message. For example, the alarm message can be expressed as "ALARM!".

[0145] In an embodiment of the present application, a computer device can access a memory based on a target address of the memory and a target memory length of the memory, which enriches the method of accessing the memory by the computer device compared to the related art; in addition, the computer device can perform an exception check based on the target memory length in the memory access request and the length carried by the length bit in the memory access request, and after the exception check passes, access the memory based on the memory access request, and after the exception check fails, it is prohibited to use the memory access request to access the memory, thereby improving the security of access to the memory.

[0146] The aforementioned memory access method can be executed by the hardware of the computer device, such as the CPU, or by the software in the computer device, or by the hardware in the computer in combination with the software. For example, the aforementioned steps 401 and 402 can be executed by the CPU; can also be executed by a preset application (such as a compiler) or a plug-in; can also be executed partially by the CPU and the other part by the application or plug-in.

[0147] The order of steps of the memory access method provided in the embodiment of the present application can be adjusted appropriately, and the steps can be increased or decreased accordingly. Any technician familiar with the technical field can easily think of a change within the technical scope disclosed in this application, and all of them should be included in the protection scope of this application.

[0148] In summary, in the memory access method provided in the embodiment of the present application, the target memory address information in the memory access request includes an address bit and a length bit, the address bit is used to carry the target address of the memory to be accessed, and the length bit is used to carry the length of the target memory allowed starting from the set address. By setting the address bit and the length bit in the target memory address information, the computer device can access the memory according to the target address of the memory and the length of the memory. While enriching the function of the memory address information, it also enriches the method for the computer device to access the memory, thereby achieving full and efficient utilization of the memory address information; and the length of the address bit and the length of the length bit can be flexibly set according to actual needs, thereby enriching the configuration method of the address bit and the length bit in the memory address information; in addition, the computer device can perform an exception check based on the target memory length in the memory access request and the length carried by the length bit in the memory access request, and after the exception check passes, access the memory based on the memory access request. After the exception check fails, it is prohibited to use the memory access request to access the memory, thereby preventing the occurrence of memory access violations, thereby improving the security of access to the memory.

[0149] In the traditional memory access method, a method for abnormality checking is also proposed, which includes: dividing an independent space in the memory as a shadow memory space, and the shadow memory space has a mapping relationship with other storage spaces in the memory, for example, 16 bytes in the other storage space correspond to 1 byte in the shadow memory space. When a space A in other storage spaces stores data, a tag value will be generated and stored in the corresponding space B of the shadow memory space for the space A, and the tag value is used to indicate the space A. After the computer device receives the memory access request, the memory address information in the memory access request includes a tag value bit and an address bit. The computer device obtains the tag value corresponding to the memory address carried by the address bit in the space B of the shadow memory space, and then compares the tag value with the tag value carried by the tag value bit in the memory access request. If they are consistent, the check is passed, and if they are inconsistent, the check fails. However, this anomaly checking method requires the additional setting of shadow memory space, which occupies memory space; and, since the number of bytes of the shadow memory space and other storage spaces do not correspond one to one, the label value stored in space B of the shadow memory space cannot effectively reflect the actual storage situation of space A, resulting in low anomaly detection accuracy; in addition, since the number of bytes of the shadow memory space and other storage spaces do not correspond one to one, the label values ​​carried by different memory access requests to access different storage spaces may be the same, which makes the reliability of anomaly detection low.

[0150] In the embodiment of the present application, the exception check is implemented by comparing the length carried by the length bit in the memory access request with the target memory length, without the need to set up additional shadow memory space, thus effectively saving memory space. In addition, there is no mapping relationship between the length carried by the length bit and the memory, that is, the bytes of the length carried by the length bit correspond one-to-one to the bytes in the memory, so the exception detection accuracy is high, making the exception detection reliability high.

[0151] Fig.10 is a flow chart of a memory address allocation method provided in an embodiment of the present application. Fig.10 As shown, the method includes:

[0152] Step 1001: A computer device generates memory address information, which includes an address bit and a length bit. The address bit is used to carry a target address of the memory, and the length bit is used to carry the length of the memory allowed to be accessed starting from a set address.

[0153] When a module, program or device at a memory address inside or outside a computer device needs to access the memory of the computer device, an address request can be sent to the computer device, and the address request is used to request allocation of memory address information. After receiving the address request, the computer device can allocate memory address information to the corresponding module, program or device.

[0154] The structure of the memory address information may refer to the structure of the memory address information in the aforementioned step 401. The method of obtaining the memory address information may refer to A1 in the aforementioned step 401. This embodiment of the application will not be elaborated on this.

[0155] Step 1002: The computer device allocates memory address information.

[0156] The computer device sends the address information to the module, program or device that sends the address request to implement the allocation of memory address information.

[0157] In an embodiment of the present application, the memory address information includes address bits and length bits. The address bits are used to carry the target address of the memory, and the length bits are used to carry the length of the memory allowed to be accessed starting from the set address. By setting the address bits and length bits in the memory address information, the length bits in the memory address information can occupy the free address bits in traditional memory address information or can occupy the extension bits and the free address bits in traditional memory address information, thereby enriching the function of the memory address information and realizing full and efficient utilization of the memory address information.

[0158] It should be noted that the memory access method and the memory address allocation method in the aforementioned embodiments are described by taking a computer device supporting Arch64 as an example. In actual implementation, the memory access method and the memory address allocation method can also be applied to a computer device supporting a system less than 64 bits or a system greater than 64 bits, and the embodiments of the present application do not limit this.

[0159] Fig.11 is a schematic diagram of a memory access device provided in an embodiment of the present application, the memory access device can be used for Figure 1 The computer device in the embodiment of the present invention comprises:

[0160] The acquisition module 1101 is used to acquire a memory access request, which includes target memory address information, and the target memory address information includes an address bit and a length bit. The address bit is used to carry the target address of the memory to be accessed, and the length bit is used to carry the length of the memory allowed to be accessed starting from the set address.

[0161] The access module 1102 is used to access the memory based on the memory access request.

[0162] Optionally, the length of the address bit is 48 bits, and the length of the length bit is less than or equal to 16 bits; or, the length of the address bit is a first length, and the length of the length bit is a second length, the first length is less than 48 bits, and the sum of the first length and the second length is less than or equal to 64 bits; or, the length of the address bit is 48 bits, and the length of the length bit is greater than 16 bits.

[0163] Optionally, the access module 1102 is further used to send a memory access request to the memory after determining that the target memory length is less than or equal to the length carried by the length bit, and the target memory length is the sum of the length from the set address to the target address and the access length.

[0164] Optionally, the access module 1102 is further configured to prohibit sending a memory access request to the memory after determining that the target memory length is greater than the length carried by the length bit.

[0165] Optionally, the access module 1102 is further configured to issue an exception message after determining that the target memory length is greater than the length carried by the length bit.

[0166] Optionally, the acquisition module 1101 is further used to generate a memory access request based on the received address setting instruction, where the address setting instruction includes target memory address information. Alternatively, the acquisition module 1101 is further used to generate a memory access request based on the generated target memory address information. Alternatively, the acquisition module 1101 is further used to receive a memory access request.

[0167] To summarize, in the memory access device provided in the embodiment of the present application, by setting the address bit and the length bit in the target memory address information, the access module can access the memory according to the target address of the memory and the length of the memory. While enriching the function of the memory address information, it also enriches the method for the computer device to access the memory, thereby achieving full and efficient utilization of the memory address information; and the length of the address bit and the length of the length bit can be flexibly set according to actual needs, thereby enriching the configuration method of the address bit and the length bit in the memory address information; in addition, the computer device can perform an exception check based on the target memory length in the memory access request and the length carried by the length bit in the memory access request, and after the exception check passes, access the memory based on the memory access request. After the exception check fails, it is prohibited to use the memory access request to access the memory, thereby preventing the occurrence of memory access violations, thereby improving the security of memory access.

[0168] Fig.12 is a schematic diagram of the structure of a memory address allocation device provided in an embodiment of the present application, the memory address allocation device can be used for Figure 1 The computer device in the memory address allocation device 120 includes:

[0169] The generation module 1201 is used to generate memory address information, which includes an address bit and a length bit, wherein the address bit is used to carry the target address of the memory, and the length bit is used to carry the length of the memory allowed to be accessed starting from the set address.

[0170] The allocation module 1202 is used to allocate memory address information.

[0171] To summarize, in the address allocation device provided in the embodiment of the present application, by setting the address bit and the length bit in the memory address information, the length bit in the memory address information can occupy the free address bit in the traditional memory address information or can occupy the extension bit and the free address bit in the traditional memory address information, thereby enriching the function of the memory address information and realizing the full and efficient use of the memory address information.

[0172] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0173] Fig.13 is a block diagram of a computer device provided in an embodiment of the present application. Fig.13 As shown, the computer device 130 includes: a processor 1301 and a memory 1302 .

[0174] A memory 1302, used to store a computer program, wherein the computer program includes program instructions;

[0175] Processor 1301 is used to call a computer program to implement the following Figure 4 The memory access method shown or Fig.10 The memory address allocation method shown.

[0176] Optionally, the computer device 130 further includes a communication bus 1303 and a communication interface 1304 .

[0177] The processor 1301 includes one or more processing cores, and the processor 1301 executes various functional applications and data processing by running computer programs.

[0178] The memory 1302 may be used to store computer programs. Optionally, the memory may store an operating system and an application unit required for at least one function. The operating system may be a real-time operating system (RTX), LINUX, UNIX, WINDOWS, or OSX.

[0179] There may be multiple communication interfaces 1304 , and the communication interfaces 1304 are used to communicate with other devices.

[0180] The memory 1302 and the communication interface 1304 are connected to the processor 1301 via the communication bus 1303 respectively.

[0181] The embodiment of the present application also provides a computer-readable storage medium, which stores a computer program, and the computer program includes at least one code segment, which can be executed by a computer device to control the computer device to execute the following steps: Figure 4 The memory access method shown or Fig.10 The memory address allocation method shown.

[0182] In the embodiments of the present application, the terms “first”, “second” and “third” are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0183] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship. "A refers to B" means that A is the same as B, or A is simply transformed based on B.

[0184] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the concept and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory access method, characterized in that: For use in a computer device, the method comprises: Obtaining a memory access request, the memory access request comprising: target memory address information, the target memory address information comprising: an address bit and a length bit, the address bit being used to carry a target address of a memory to be accessed, the length bit being used to carry a length of the memory allowed to be accessed starting from a set address, wherein the target address is used to indicate a starting position of the memory to be accessed, the set address is a starting address of the length of the memory allowed to be accessed, and the length of the memory allowed to be accessed is a size of the memory allowed to be accessed; After determining that the target memory length is less than or equal to the length carried by the length bit, the memory access request is sent to the memory, and the target memory length is the sum of the length from the set address to the target address and the access length.

2. The method according to claim 1, characterized in that The length of the address bit is 48 bits, and the length bit is less than or equal to 16 bits; Alternatively, the length of the address bit is a first length, the length of the length bit is a second length, the first length is less than 48 bits, and the sum of the first length and the second length is less than or equal to 64 bits; Alternatively, the length of the address bits is 48 bits, and the length of the length bits is greater than 16 bits.

3. The method according to claim 1, characterized in that The method further comprises: After determining that the target memory length is greater than the length carried by the length bits, sending the memory access request to the memory is prohibited.

4. The method according to claim 3, characterized in that: The method further comprises: After determining that the target memory length is greater than the length carried by the length bit, an exception message is issued.

5. The method according to any one of claims 1 to 4, characterized in that: The obtaining of the memory access request comprises: generating the memory access request based on a received address setting instruction, the address setting instruction including the target memory address information; Alternatively, based on the generated target memory address information, the memory access request is generated; Alternatively, the memory access request is received.

6. A memory address allocation method, characterized in that: For use in a computer device, the method comprises: Generate memory address information, the memory address information includes: an address bit and a length bit, the address bit is used to carry the target address of the memory, the length bit is used to carry the length of the memory allowed to be accessed starting from the set address, wherein the target address of the memory is used to indicate the starting position of the memory, the set address is the starting address of the length of the memory allowed to be accessed, and the length of the memory allowed to be accessed is the size of the memory allowed to be accessed; The memory address information is allocated.

7. A memory access device, characterized in that: For use in a computer device, the device comprises: an acquisition module, used for acquiring a memory access request, the memory access request comprising: target memory address information, the target memory address information comprising: an address bit and a length bit, the address bit being used to carry a target address of a memory to be accessed, the length bit being used to carry a length of the memory allowed to be accessed starting from a set address, wherein the target address is used to indicate a starting position of the memory to be accessed, the set address is a starting address of the length of the memory allowed to be accessed, and the length of the memory allowed to be accessed is a size of the memory allowed to be accessed; The access module is used to send the memory access request to the memory after determining that the target memory length is less than or equal to the length carried by the length bit, and the target memory length is the sum of the length from the set address to the target address and the access length.

8. The device according to claim 7, characterized in that The length of the address bit is 48 bits, and the length bit is less than or equal to 16 bits; Alternatively, the length of the address bit is a first length, the length of the length bit is a second length, the first length is less than 48 bits, and the sum of the first length and the second length is less than or equal to 64 bits; Alternatively, the length of the address bits is 48 bits, and the length of the length bits is greater than 16 bits.

9. The device according to claim 7, characterized in that The access module is further configured to prohibit sending the memory access request to the memory after determining that the target memory length is greater than the length carried by the length bit.

10. The device according to claim 9, characterized in that The access module is further configured to issue an exception message after determining that the target memory length is greater than the length carried by the length bit.

11. The device according to any one of claims 7 to 10, characterized in that: The acquisition module is further used to generate the memory access request based on a received address setting instruction, wherein the address setting instruction includes the target memory address information; Alternatively, the acquisition module is further used to generate the memory access request based on the generated target memory address information; Alternatively, the acquisition module is further used to receive the memory access request.

12. A memory address allocation device, characterized in that: For use in a computer device, the device comprises: A generating module, used for generating memory address information, the memory address information comprising: an address bit and a length bit, the address bit is used for carrying a target address of the memory, the length bit is used for carrying a length of the memory allowed to be accessed starting from a set address, wherein the target address of the memory is used for indicating a starting position of the memory, the set address is a starting address of the length of the memory allowed to be accessed, and the length of the memory allowed to be accessed is the size of the memory allowed to be accessed; An allocation module is used to allocate the memory address information.

13. A computer device, characterized in that: include: Processor and memory; The memory is used to store a computer program, wherein the computer program includes program instructions; The processor is used to call the computer program to implement the memory access method as described in any one of claims 1 to 5, or to implement the memory address allocation method as described in claim 6.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes at least one section of code. The at least one section of code can be executed by a computer device to control the computer device to execute the memory access method as described in any one of claims 1 to 5 or the memory address allocation method as described in claim 6.

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