Chip packaging structure and manufacturing method thereof

Abstract

The present invention provides a chip packaging structure and a method for manufacturing the same. The chip packaging structure includes a chip, a reconfiguration circuit layer, solder balls, a packaging colloid, and a stress buffer layer. The chip has an active surface and a back surface opposite to each other, and a surrounding surface connecting the active surface and the back surface. The reconfiguration circuit layer is configured on the active surface of the chip. The solder balls are configured on the reconfiguration circuit layer, and the chip is electrically connected to the solder balls through the reconfiguration circuit layer. The packaging colloid covers the active surface and back surface of the chip, the reconfiguration circuit layer, and part of the solder balls. The stress buffer layer covers at least the surrounding surface of the chip. The outer surface of the stress buffer layer is flush with the side surface of the packaging colloid. The chip packaging structure of the present invention can effectively protect the edge of the chip and increase the overall structural strength and structural reliability.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a chip packaging structure and a manufacturing method thereof. Background Art

[0002] Existing technologies utilize elastic materials, encapsulation materials, or overhanging structures beneath the die as anchors to protect the die edge or enhance the mechanical strength of the encapsulant. Currently, in some products, these elastic materials or encapsulation materials only protect the die back and spherical surface, failing to effectively protect the die edge. Alternatively, in other products, encapsulation materials are used to protect the die edge. While this can prevent chip cracking and failure during reliability testing, the difference in thermal expansion coefficients between the encapsulant and the die shortens reliability testing times and the product's lifespan. Summary of the Invention

[0003] The present invention is directed to a chip packaging structure, which can effectively protect the edge of the chip and increase the overall structural strength and structural reliability.

[0004] The present invention is also directed to a method for manufacturing a chip packaging structure, which is used to manufacture the above-mentioned chip packaging structure.

[0005] According to an embodiment of the present invention, a chip packaging structure includes a chip, a reconfiguration circuit layer, solder balls, an encapsulation resin, and a stress buffer layer. The chip has an active surface and a back surface facing each other, and a surrounding surface connecting the active surface and the back surface. The reconfiguration circuit layer is configured on the active surface of the chip. The solder balls are configured on the reconfiguration circuit layer, and the chip is electrically connected to the solder balls through the reconfiguration circuit layer. The encapsulation resin covers the active surface and back surface of the chip, the reconfiguration circuit layer, and a portion of the solder balls. The stress buffer layer covers at least the surrounding surface of the chip. The outer surface of the stress buffer layer is flush with the side surface of the encapsulation resin.

[0006] In the chip packaging structure according to an embodiment of the present invention, the reconfigured circuit layer includes a circuit layer and at least one conductive via. The conductive via is located between the circuit layer and the active surface of the chip. The chip is electrically connected to the circuit layer through the conductive via.

[0007] In the chip packaging structure according to the embodiment of the present invention, the chip packaging structure further includes a surface treatment layer, which is disposed on the reconfiguration circuit layer and located between the solder balls and the reconfiguration circuit layer.

[0008] In a chip package structure according to an embodiment of the present invention, the encapsulant has an upper surface and a lower surface opposing each other. A side surface connects the upper surface and the lower surface, and the side surface includes a first side surface and a second side surface. The stress buffer layer further extends over the first side surface and the upper surface, and an outer surface of the stress buffer layer is flush with the second side surface.

[0009] In the chip packaging structure according to an embodiment of the present invention, a first vertical distance is defined between the upper surface of the encapsulant and the active surface of the chip, and a second vertical distance is defined between the lower surface of the encapsulant and the back surface of the chip. The first vertical distance is greater than the second vertical distance.

[0010] In the chip packaging structure according to the embodiment of the present invention, the height of the stress buffer layer is equal to or slightly greater than the thickness of the chip.

[0011] In the chip package structure according to an embodiment of the present invention, the material of the stress buffer layer is different from the material of the encapsulation colloid. The material of the stress buffer layer includes silane adhesion promoter polymer, silicone rubber, epoxy resin, or photosensitive dielectric material (such as PI, PBO, BCB, or PID).

[0012] According to an embodiment of the present invention, a method for manufacturing a chip package structure includes the following steps. A semi-finished package is provided. The semi-finished package includes a wafer, a reconfiguration circuit layer, a plurality of solder balls, and an encapsulation resin. The reconfiguration circuit layer is located between the solder balls and the wafer. The encapsulation resin covers the wafer, the reconfiguration circuit layer, and a portion of the solder balls. A plurality of grooves are formed in the encapsulation resin. The grooves crisscross and extend from the upper surface of the encapsulation resin and through the wafer, thereby dividing the wafer into a plurality of chips. Each chip has an active surface and a back surface facing each other, and a surrounding surface connecting the active surface and the back surface. The reconfiguration circuit layer is disposed on the active surface of the chip. Each chip is electrically connected to a corresponding solder ball via the reconfiguration circuit layer. The encapsulation resin covers the active surface and back surface of each chip, the reconfiguration circuit layer, and a corresponding portion of the solder balls. A stress buffer layer is formed on the upper surface of the encapsulation resin and extends into the grooves. The stress buffer layer exposes a portion of the solder balls. A singulation process is performed to cut the stress buffer layer and the encapsulation resin to form a plurality of separated chip package structures. The encapsulant has an upper surface and a lower surface facing each other, and a side surface connecting the upper surface and the lower surface. The side surface includes a first side surface and a second side surface. A stress buffer layer covers the first side surface and the upper surface, and an outer surface of the stress buffer layer is flush with the second side surface.

[0013] In the chip packaging structure manufacturing method according to an embodiment of the present invention, the chip packaging structure manufacturing method further includes providing a carrier before providing the semi-finished package, and placing the semi-finished package on the carrier. Before performing the singulation process, the carrier is removed to expose the lower surface of the encapsulant.

[0014] In a method for manufacturing a chip packaging structure according to an embodiment of the present invention, the reconfigured circuit layer includes a circuit layer and at least one conductive via. The conductive via is located between the circuit layer and the active surface of the chip. The chip is electrically connected to the circuit layer via the conductive via.

[0015] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the aforementioned semi-finished packaging product further includes a surface treatment layer, which is disposed on the reconfiguration circuit layer and located between the solder balls and the reconfiguration circuit layer.

[0016] In the method for fabricating a chip package structure according to an embodiment of the present invention, the step of forming a stress buffer layer includes forming a stress buffer material layer on the upper surface of the encapsulant and extending into the trench, wherein the stress buffer material layer covers the solder balls. A plasma etching process is then performed to remove a portion of the stress buffer material layer, exposing a portion of the solder balls and forming the stress buffer layer.

[0017] In the manufacturing method of the chip packaging structure according to an embodiment of the present invention, there is a first vertical distance between the upper surface of the above-mentioned encapsulant and the active surface of the chip, and there is a second vertical distance between the lower surface of the encapsulant and the back surface of the chip, and the first vertical distance is greater than the second vertical distance.

[0018] In the manufacturing method of the chip packaging structure according to an embodiment of the present invention, the material of the stress buffer layer is different from the material of the encapsulation colloid. The material of the stress buffer layer includes silane coupling agent polymer (Silane Adhesion Promoter), silicone rubber (Silicone Rubber), epoxy resin (Epoxy) or photosensitive dielectric material (such as PI, PBO, BCB or PID).

[0019] According to an embodiment of the present invention, a method for manufacturing a chip packaging structure includes the following steps. A packaging semi-finished product is provided. The packaging semi-finished product includes a plurality of chips, a reconfiguration circuit layer, a plurality of solder balls, an encapsulation colloid, and a stress buffer layer. The chips are separated from each other, and each chip has an active surface and a back surface opposite to each other and a surrounding surface connecting the active surface and the back surface. The reconfiguration circuit layer is configured on the active surface of the chip. Each chip is electrically connected to each corresponding solder ball through the reconfiguration circuit layer. The encapsulation colloid covers the active surface and back surface of each chip, the reconfiguration circuit layer, the corresponding part of the solder balls, and the stress buffer layer. The stress buffer layer covers the surrounding surface of each chip, and the height of the stress buffer layer is equal to or slightly greater than the thickness of each chip. A singulation process is performed to cut the stress buffer layer and the encapsulation colloid to form a plurality of chip packaging structures separated from each other. The side surface of the encapsulation colloid is cut flush with the outer surface of the stress buffer layer.

[0020] In the chip packaging structure manufacturing method according to an embodiment of the present invention, the chip packaging structure manufacturing method further includes providing a carrier before providing the semi-finished package, and placing the semi-finished package on the carrier. After the singulation process, the carrier is removed to expose the lower surface of the encapsulant.

[0021] In the manufacturing method of the chip packaging structure according to an embodiment of the present invention, the reconfigured circuit layer includes a circuit layer and at least one conductive via. The conductive via is located between the circuit layer and the active surface of the chip, and the chip is electrically connected to the circuit layer through the conductive via.

[0022] In the manufacturing method of the chip packaging structure according to the embodiment of the present invention, the aforementioned semi-finished packaging product further includes a surface treatment layer, which is disposed on the reconfiguration circuit layer and located between the solder balls and the reconfiguration circuit layer.

[0023] In a method for manufacturing a chip package structure according to an embodiment of the present invention, the encapsulant has an upper surface and a lower surface opposing each other, and a side surface connecting the upper surface and the lower surface. A first vertical spacing is defined between the upper surface of the encapsulant and the active surface of the chip, and a second vertical spacing is defined between the lower surface of the encapsulant and the back surface of the chip, wherein the first vertical spacing is greater than the second vertical spacing.

[0024] In the manufacturing method of the chip packaging structure according to an embodiment of the present invention, the material of the stress buffer layer is different from the material of the encapsulation colloid. The material of the stress buffer layer includes silane coupling agent polymer (Silane Adhesion Promoter), silicone rubber (Silicone Rubber), epoxy resin (Epoxy) or photosensitive dielectric material (such as PI, PBO, BCB or PID).

[0025] Based on the above, in the chip package structure of the present invention, the encapsulant covers the active and back surfaces of the chip, the reconfigured circuit layer, and a portion of the solder balls, while the stress buffer layer covers at least the peripheral surface of the chip. In other words, the active and back surfaces of the chip are protected by the encapsulant, while the peripheral surface of the chip is protected by the stress buffer layer. This effectively protects the chip edges through the stress buffer layer, while the encapsulant increases the structural strength of the chip package structure, resulting in the chip package structure of the present invention having superior structural reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figures 1A to 1F is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present invention;

[0027] Figure 1G is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention;

[0028] Figures 2A to 2C is a cross-sectional schematic diagram of partial steps of a method for manufacturing a chip packaging structure according to another embodiment of the present invention;

[0029] Figure 2D FIG. 4 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention.

[0030] Description of Reference Numerals

[0031] 10: carrier board;

[0032] 100a, 100b: chip packaging structure;

[0033] 110: chip;

[0034] 112: active side;

[0035] 114: back;

[0036] 116: surrounding surface;

[0037] 120: reconfigure the circuit layer;

[0038] 122: circuit layer;

[0039] 124: conductive through hole;

[0040] 130: solder ball;

[0041] 132: top surface;

[0042] 140, 142: encapsulation colloid;

[0043] 141: upper surface;

[0044] 143: lower surface;

[0045] 145: first side surface;

[0046] 147: second side surface;

[0047] 148: side surface;

[0048] 150: surface treatment layer;

[0049] 162a: stress buffer material layer;

[0050] 160a, 164: stress buffer layer;

[0051] 167, 168: outer surface;

[0052] B: groove;

[0053] FA, FB: packaging semi-finished products;

[0054] W: wafer;

[0055] G1: first vertical spacing;

[0056] G2: Second vertical spacing. DETAILED DESCRIPTION

[0057] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0058] Figures 1A to 1F It is a cross-sectional schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present invention. Figure 1G FIG. 1 is a cross-sectional schematic diagram of a chip packaging structure according to an embodiment of the present invention.

[0059] Regarding the manufacturing method of the chip package structure of this embodiment, first, a carrier 10 and a semi-finished package product FA are provided, wherein the semi-finished package product FA is disposed on the carrier 10. Specifically, the semi-finished package product FA includes a wafer W, a reconfigured circuit layer 120, a plurality of solder balls 130, and an encapsulant 142. The reconfigured circuit layer 120 is located between the solder balls 130 and the wafer W, while the encapsulant 142 covers the wafer W, the reconfigured circuit layer 120, and a portion of the solder balls 130. Specifically, the encapsulant 142 exposes portions of the solder balls 130 to serve as contact points for external electrical connections.

[0060] Furthermore, the reconfiguration circuit layer 120 of the present embodiment includes a circuit layer 122 and at least one conductive via (a plurality of conductive vias 124 are schematically shown), wherein the conductive via 124 is located between the circuit layer 122 and the wafer W, and the circuit layer 122 is embodied as a patterned circuit layer. Furthermore, the semi-finished packaging product FA of the present embodiment also includes a surface treatment layer 150, which is arranged on the reconfiguration circuit layer 120 and is located between the solder balls 130 and the reconfiguration circuit layer 120. Here, the surface treatment layer 150 is, for example, nickel-plated palladium immersion gold (ENEPIG), an organic solderability preservative (OSP) layer, or electroless nickel immersion gold ENIG (ENIG), but is not limited thereto. That is, the semi-finished packaging product FA of the present embodiment is essentially a wafer-level package, and the circuit and ball implantation processes have been completed.

[0061] Next, please also refer to Figure 1A and Figure 1BA plurality of grooves B are formed in the encapsulant 142. The grooves B extend from the upper surface 141 of the encapsulant 142 and pass through the wafer W, thereby dividing the wafer W into a plurality of chips 110. In other words, the wafer W is diced to form separate chips 110. It should be noted that the grooves B, viewed from above, appear to be crisscrossed.

[0062] Here, each chip 110 has an active surface 112 and a back surface 114 facing each other, and a peripheral surface 116 connecting the active surface 112 and the back surface 114. A reconfiguration circuit layer 120 is disposed on the active surface 112 of the chip 110, and each chip 110 is electrically connected to a corresponding solder ball 130 via the reconfiguration circuit layer 120. An encapsulant 142 covers the active surface 112 and back surface 114 of each chip 110, the reconfiguration circuit layer 120, and a portion of the corresponding solder ball 130.

[0063] Next, please refer to Figure 1C A stress buffer material layer 162 a is formed on the upper surface 141 of the encapsulant 142 and extends into and fills the trench B. At this time, the stress buffer material layer 162 a covers the top surface 132 of the solder ball 130 and is spaced apart from the top surface 132 of the solder ball 130 .

[0064] Next, please refer to Figure 1D A plasma etching process is then performed to remove a portion of the stress buffer material layer 162a, exposing the top surface 132 of the solder ball 130 to form a stress buffer layer 164. In particular, the material of the stress buffer layer 164 in this embodiment is different from the material of the encapsulant 142. The material of the stress buffer layer 164 may be, for example, a silane adhesion promoter, silicone rubber, epoxy, or a photosensitive dielectric material (such as PI, PBO, BCB, or PID), but is not limited thereto. Thus, the stress buffer layer 164 is formed on the upper surface 141 of the encapsulant 142 and extends into the trench B, exposing a portion of the solder ball 130.

[0065] Afterwards, please also refer to Figure 1D and Figure 1E , the carrier 10 is removed to expose the lower surface 143 of the encapsulant 142 .

[0066] Finally, please also refer to Figure 1E and Figure 1FA singulation process is then performed to cut the stress buffer layer 164 and the encapsulant 142, thereby forming a plurality of separate chip package structures (four chip package structures 100a are schematically shown). At this point, the cut stress buffer layer 160a covers the first side surface 145 and top surface 141 of the cut encapsulant 140, and the outer surface 167 of the cut stress buffer layer 160a is flush with the second side surface 147 of the cut encapsulant 140. At this point, the chip package structure 100a is completed.

[0067] In terms of structure, please refer to Figure 1G The chip packaging structure 100a of this embodiment includes a chip 110, a reconfiguration circuit layer 120, solder balls 130, a packaging gel 140 and a stress buffer layer 160a. The chip 110 has an active surface 112 and a back surface 114 opposite to each other and a surrounding surface 116 connecting the active surface 112 and the back surface 114. The reconfiguration circuit layer 120 is configured on the active surface 112 of the chip 110, wherein the reconfiguration circuit layer 120 includes a circuit layer 122 and a conductive through-hole 124. The conductive through-hole 124 is located between the circuit layer 122 and the active surface 112 of the chip 110, wherein the chip 110 is electrically connected to the circuit layer 122 through the conductive through-hole 124. The solder ball 130 is configured on the reconfiguration circuit layer 120, and the chip 110 is electrically connected to the solder ball 130 through the reconfiguration circuit layer 120.

[0068] Furthermore, the encapsulant 140 of this embodiment covers the active surface 112 and the back surface 114 of the chip 110, the reconfiguration circuit layer 120, and a portion of the solder balls 130. More specifically, the encapsulant 140 has an upper surface 141 and a lower surface 143 opposite to each other. The side surface connects the upper surface 141 and the lower surface 143, and the side surface includes a first side surface 145 and a second side surface 147. A first vertical spacing G1 is defined between the upper surface 141 of the encapsulant 140 and the active surface 112 of the chip 110, and a second vertical spacing G2 is defined between the lower surface 143 of the encapsulant 140 and the back surface 114 of the chip 110, and the first vertical spacing G1 is greater than the second vertical spacing G2.

[0069] In particular, the stress buffer layer 160a covers the peripheral surface 116 of the chip 110 and extends to cover the first side surface 145 and the top surface 141 of the encapsulant 140. The outer surface 167 of the stress buffer layer 160a is flush with the second side surface 147. Here, the material of the stress buffer layer 160a is different from the material of the encapsulant 140. The material of the stress buffer layer 160a may be, for example, a silane adhesion promoter polymer, silicone rubber, epoxy resin, or a photosensitive dielectric material (such as PI, PBO, BCB, or PID), but is not limited thereto.

[0070] In addition, the chip package structure 100a of this embodiment further includes a surface treatment layer 150 disposed on the reconfiguration circuit layer 120 and located between the solder balls 130 and the reconfiguration circuit layer 120. Here, the surface treatment layer 150 is, for example, nickel-plated palladium immersion gold (ENEPIG), an organic solderability preservative (OSP) layer, or electroless nickel immersion gold (ENIG), but is not limited thereto.

[0071] In this embodiment, the encapsulant 140 covers the active surface 112 and back surface 114 of the chip 110, the reconfigured circuit layer 120, and portions of the solder balls 130, while the stress buffer layer 160a covers at least the peripheral surface 116 of the chip 110 (the stress buffer layer 160a may protrude downward or be flush with the chip 110). In other words, the active surface 112 and back surface 114 of the chip 110 are protected by the encapsulant 140, while the peripheral surface 116 of the chip 110 is protected by the stress buffer layer 160a. In other words, the provision of the stress buffer layer 160a effectively protects the edges of the chip 110, while the provision of the encapsulant 140 increases the structural strength of the chip package structure 100a, thereby providing the chip package structure 100a of this embodiment with improved structural reliability.

[0072] It should be noted that the following embodiments share the same component numbers and some of the contents of the previous embodiments, wherein the same reference numerals are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the previous embodiments, and the following embodiments will not repeat them.

[0073] Figures 2A to 2C It is a cross-sectional schematic diagram of partial steps of a method for manufacturing a chip packaging structure according to another embodiment of the present invention. Figure 2D FIG. 4 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention.

[0074] The manufacturing method of the chip package structure 100b of this embodiment is similar to the manufacturing method of the chip package structure 100a described above. The difference between the two is: Figure 2A , providing a carrier 10 and a semi-finished package product FB, wherein the semi-finished package product FB is disposed on the carrier 10. In detail, the semi-finished package product FB includes a plurality of chips 110, a reconfigured circuit layer 120, a plurality of solder balls 130, an encapsulant 142, and a stress buffer layer 162b. The chips 110 are separated from each other, and each chip 110 has an active surface 112 and a back surface 114 facing each other, and a peripheral surface 116 connecting the active surface 112 and the back surface 114. The reconfigured circuit layer 120 is disposed on the active surface 112 of the chip 110, wherein the reconfigured circuit layer 120 includes a circuit layer 122 and conductive vias 124. The conductive vias 124 are located between the circuit layer 122 and the active surface 112 of the chip 110, and the chip 110 is electrically connected to the circuit layer 122 through the conductive vias 124. Each chip 110 is electrically connected to each corresponding solder ball 130 through the reconfigured circuit layer 120.

[0075] Furthermore, the encapsulant 142 of this embodiment covers the active surface 112 and back surface 114 of each chip 110, the reconfigured circuit layer 120, the corresponding portion of the solder balls 130, and the stress buffer layer 162b. Specifically, in this embodiment, the stress buffer layer 162b covers the peripheral surface 116 of each chip 110, and the height H of the stress buffer layer 162b is equal to or slightly greater than the thickness T of each chip 110. Here, the material of the stress buffer layer 162b is different from that of the encapsulant 142. The material of the stress buffer layer 162b may be, for example, a silane adhesion promoter, silicone rubber, epoxy, or a photosensitive dielectric material (such as PI, PBO, BCB, or PID), but is not limited thereto. Furthermore, the semi-finished package product (FB) of this embodiment further includes a surface treatment layer 150 disposed on the reconfigured circuit layer 120 and located between the solder balls 130 and the reconfigured circuit layer 120. The surface treatment layer 150 is, for example, nickel electroplating palladium immersion gold (ENEPIG), an organic solderability preservatives (OSP) layer, or electroless nickel immersion gold (ENIG), but is not limited thereto.

[0076] In short, the semi-finished package FB of this embodiment is embodied as a fan-out wafer level chip package (Fan out WLCSP) structure, which reorganizes the chip 110 on the carrier 10, utilizes the stress buffer layer 162b to protect the peripheral surface 116 of the chip 110, and completes the circuit and ball planting process.

[0077] Next, please also refer to Figure 2A and Figure 2B , a singulation process is performed to cut the stress buffer layer 162b and the encapsulation glue 142 to form a plurality of chip package structures 100b separated from each other. At this time, the side surface 148 of the encapsulation glue 140 after cutting is aligned with the outer surface 168 of the stress buffer layer 160b. Finally, please refer to Figure 2B and Figure 2C , the carrier 10 is removed to expose the lower surface 143 of the encapsulant 140 , thereby completing the manufacture of the chip package structure 100 b .

[0078] In terms of structure, please also refer to Figure 1G and Figure 2D The chip package structure 100b of this embodiment is similar to the aforementioned chip package structure 100a, with the difference being that the stress buffer layer 160b of this embodiment only covers the peripheral surface 116 of the chip 110, and the height H of the stress buffer layer 160b may be equal to or slightly greater than the thickness T of the chip 110. Here, the material of the stress buffer layer 160b is different from the material of the encapsulant 140. The material of the stress buffer layer 160b may be, for example, a silane adhesion promoter, silicone rubber, epoxy resin, or a photosensitive dielectric material (e.g., PI, PBO, BCB, or PID), but is not limited thereto.

[0079] In this embodiment, encapsulant 140 covers the active surface 112 and back surface 114 of chip 110, while stress buffer layer 160b covers the peripheral surface 116 of chip 110. In other words, the active surface 112 and back surface 114 of chip 110 are protected by encapsulant 140, while the peripheral surface 116 of chip 110 is protected by stress buffer layer 160b. The provision of stress buffer layer 160b effectively protects the edges of chip 110, and the provision of encapsulant 140 increases the structural strength of chip package structure 100b, thereby ensuring that the chip package structure 100b of this embodiment has greater structural reliability.

[0080] In summary, in the chip package structure of the present invention, the active and back surfaces of the chip are protected by an encapsulant, while the peripheral surfaces of the chip are protected by a stress buffer layer. Therefore, the stress buffer layer effectively protects the chip edges, while the encapsulant enhances the structural strength of the chip package, resulting in the chip package structure of the present invention having superior structural reliability.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A chip having an active surface and a back surface facing each other and a peripheral surface connecting the active surface and the back surface; a reconfiguration circuit layer, configured on the active surface of the chip; Solder balls are arranged on the reconfiguration circuit layer, wherein the chip is electrically connected to the solder balls through the reconfiguration circuit layer; A packaging colloid covering the active surface and the back surface of the chip, the reconfiguration circuit layer and part of the solder balls; as well as A stress buffer layer at least covers the peripheral surface of the chip, wherein the outer surface of the stress buffer layer is flush with the side surface of the encapsulation colloid, The encapsulation body has an upper surface and a lower surface opposite to each other, the side surface connects the upper surface and the lower surface, and the side surface includes a first side surface and a second side surface, the stress buffer layer further extends to cover the first side surface and the upper surface, and the outer surface of the stress buffer layer is flush with the second side surface. There is a first vertical distance between the upper surface of the encapsulant and the active surface of the chip, and there is a second vertical distance between the lower surface of the encapsulant and the back surface of the chip, and the first vertical distance is greater than the second vertical distance. The material of the stress buffer layer is different from the material of the packaging colloid, and the material of the stress buffer layer includes silane coupling agent polymer, silicone rubber, epoxy resin or photosensitive dielectric material.

2. The chip packaging structure according to claim 1, wherein: The reconfiguration circuit layer includes a circuit layer and at least one conductive via. The at least one conductive via is located between the circuit layer and the active surface of the chip, and the chip is electrically connected to the circuit layer through the at least one conductive via.

3. The chip packaging structure according to claim 1, wherein: Also includes: The surface treatment layer is configured on the reconfiguration circuit layer and is located between the solder balls and the reconfiguration circuit layer.

4. The chip packaging structure according to claim 1, wherein: The height of the stress buffer layer is equal to or slightly greater than the thickness of the chip.

5. A method for manufacturing a chip packaging structure, characterized in that: include: Providing a semi-finished package product, the semi-finished package product comprising a wafer, a reconfigured circuit layer, a plurality of solder balls, and an encapsulation colloid, wherein the reconfigured circuit layer is located between the plurality of solder balls and the wafer, and the encapsulation colloid covers the wafer, the reconfigured circuit layer, and a portion of the plurality of solder balls; forming a plurality of grooves in the encapsulant, the plurality of grooves crisscrossing each other and extending from the upper surface of the encapsulant and through the wafer, thereby dividing the wafer into a plurality of chips, wherein each of the plurality of chips has an active surface and a back surface opposite to each other, and a surrounding surface connecting the active surface and the back surface, and the reconfiguration circuit layer is disposed on the active surface of the chip, each of the plurality of chips is electrically connected to each of the corresponding plurality of solder balls through the reconfiguration circuit layer, and the encapsulant covers the active surface and the back surface of each of the plurality of chips, the reconfiguration circuit layer, and a corresponding portion of the solder balls; forming a stress buffer layer on the upper surface of the encapsulant and extending into the plurality of grooves, wherein the stress buffer layer exposes a portion of the plurality of solder balls; as well as A singulation process is performed to cut the stress buffer layer and the encapsulant to form a plurality of separated chip package structures, wherein the encapsulant has an upper surface and a lower surface opposite to each other and a side surface connecting the upper surface and the lower surface, the side surface includes a first side surface and a second side surface, the stress buffer layer covers the first side surface and the upper surface, and the outer surface of the stress buffer layer is flush with the second side surface, a first vertical distance is defined between the upper surface of the encapsulant and the active surface of the chip, and a second vertical distance is defined between the lower surface of the encapsulant and the back surface of the chip, and the first vertical distance is greater than the second vertical distance. The material of the stress buffer layer is different from the material of the packaging colloid, and the material of the stress buffer layer includes silane coupling agent polymer, silicone rubber, epoxy resin or photosensitive dielectric material.

6. The method for manufacturing a chip packaging structure according to claim 5, wherein: Also includes: Before providing the semi-finished package product, a carrier is provided, and the semi-finished package product is arranged on the carrier; as well as Before the singulation process is performed, the carrier is removed to expose the lower surface of the encapsulant.

7. The method for manufacturing a chip packaging structure according to claim 5, wherein: The reconfiguration circuit layer includes a circuit layer and at least one conductive via. The at least one conductive via is located between the circuit layer and the active surface of the chip, and the chip is electrically connected to the circuit layer through the at least one conductive via.

8. The method for manufacturing a chip packaging structure according to claim 5, wherein: The semi-finished packaged product further includes: The surface treatment layer is configured on the reconfiguration circuit layer and is located between the plurality of solder balls and the reconfiguration circuit layer.

9. The method for manufacturing a chip packaging structure according to claim 5, wherein: The step of forming the stress buffer layer includes: forming a stress buffer material layer on the upper surface of the encapsulant and extending into the plurality of grooves, wherein the stress buffer material layer covers the plurality of solder balls; and A plasma etching process is performed to remove a portion of the stress buffer material layer, thereby exposing a portion of the plurality of solder balls and forming the stress buffer layer.

10. A method for manufacturing a chip packaging structure, characterized in that: include: A semi-finished package product is provided, comprising a plurality of chips, a reconfiguration circuit layer, a plurality of solder balls, an encapsulant, and a stress buffer layer. The plurality of chips are separated from each other, and each of the plurality of chips has an active surface and a back surface facing each other, and a surrounding surface connecting the active surface and the back surface. The reconfiguration circuit layer is disposed on the active surface of the chip. Each of the plurality of chips is electrically connected to each of the corresponding plurality of solder balls via the reconfiguration circuit layer. The encapsulant covers the active surface and the back surface of each of the plurality of chips, the reconfiguration circuit layer, a corresponding portion of the solder balls, and the stress buffer layer. The stress buffer layer covers the surrounding surface of each of the plurality of chips, and the height of the stress buffer layer is equal to or slightly greater than the thickness of each of the plurality of chips. as well as A singulation process is performed to cut the stress buffer layer and the encapsulant to form a plurality of separated chip package structures, wherein a side surface of the encapsulant is flush with an outer surface of the stress buffer layer, the encapsulant has an upper surface and a lower surface opposite to each other, and a side surface connecting the upper surface and the lower surface, a first vertical distance is defined between the upper surface of the encapsulant and the active surface of the chip, and a second vertical distance is defined between the lower surface of the encapsulant and the back surface of the chip, and the first vertical distance is greater than the second vertical distance. The material of the stress buffer layer is different from the material of the packaging colloid, and the material of the stress buffer layer includes silane coupling agent polymer, silicone rubber, epoxy resin or photosensitive dielectric material.

11. The method for manufacturing a chip packaging structure according to claim 10, wherein: Also includes: Before providing the semi-finished package product, a carrier is provided, and the semi-finished package product is arranged on the carrier; as well as After the singulation process is performed, the carrier is removed to expose the lower surface of the encapsulant.

12. The method for manufacturing a chip packaging structure according to claim 10, wherein: The reconfiguration circuit layer includes a circuit layer and at least one conductive via. The at least one conductive via is located between the circuit layer and the active surface of the chip, and the chip is electrically connected to the circuit layer through the at least one conductive via.

13. The method for manufacturing a chip packaging structure according to claim 10, wherein: The semi-finished packaged product further comprises: The surface treatment layer is configured on the reconfiguration circuit layer and is located between the plurality of solder balls and the reconfiguration circuit layer.

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