Multi-threshold logic power device, preparation method and method for simultaneously reading multiple thresholds
By forming a contact structure array on a semiconductor substrate, the simplified preparation and wide application of multi-threshold logic power devices are achieved, and the complex and cost-effective preparation problems in the prior art are solved, and the ability to store and read multi-bit information is provided.
Patent Information
- Application Number
- CN202011627542.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-12-31
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2040-12-31
AI Technical Summary
The existing multi-threshold logic power devices have complex preparation processes, high costs, and narrow application fields, making them difficult to effectively apply in the power device field.
By forming a contact structure array on the semiconductor substrate and using the contact mask plate design, a multi-threshold logic power device with the same common trench gate structure is prepared. In the contact structure array, the edges of the same group of contact portions and the channel edges have the same lateral spacing, and the edges of the contact portions and the channel edges have different lateral spacings, thereby realizing the multi-threshold logic state.
The preparation process is simplified, the cost is reduced, and the application range is expanded. The threshold voltage number can be flexibly designed, suitable for large current situations, with the ability to store information and can easily read multi-bit information.
Smart Images
Figure CN114695533B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology and relates to a multi-threshold logic power device, a preparation method and a method for simultaneously reading multiple thresholds. Background Art
[0002] Multiple-valued logic (MVL) uses more than two possible thresholds to facilitate logic operations. Its main applications fall into two categories: the first is using MVL to efficiently solve binary problems; the second is designing electronic circuits using more than two discrete-level signals (multi-bit systems), such as multi-valued memories, arithmetic circuits, and field-programmable gate arrays (FPGAs).
[0003] MVL circuits have been implemented in bipolar technologies such as integrated interconnect logic (IIL), emitter-coupled logic (ECL), metal oxide semiconductor (MOS), and charge-coupled devices (CCD). MVL devices manufactured include multi-level transistors (MOSFET, FINFET), multi-threshold memories (Flash, DRAM, NAND, RRAM), single electron transistors (SET), and carbon nanotube transistors (CNTFET).
[0004] In the prior art, see Figure 1 and Figure 2 ,in Figure 2 Indicated Figure 1 A schematic diagram of the circuit connection of a multi-threshold logic transistor in Figure 1. The structure of a multi-threshold logic transistor is actually composed of multiple transistors sharing the same gate. The multi-threshold logic transistor includes a shared gate and three threshold voltages: Vt0, Vt1, and Vt2. This multi-threshold logic transistor can process four levels of logic signals (or two bits): 00, 01, 10, and 11.
[0005] However, while multi-threshold logic transistors are more efficient and faster than binary logic transistors, the process for creating transistors with multiple Vt levels is complex and costly in existing multi-threshold logic transistors. Furthermore, multi-threshold logic transistors with "built-in" multi-levels or multiple Vt levels are currently primarily used in multi-level logic and storage to achieve more efficient data computing and high-density storage. However, the application of "built-in" multi-level transistors in power devices is rarely reported.
[0006] Therefore, it is necessary to provide a multi-threshold logic power device with the ability to store information, a preparation method, and a method for simultaneously reading multiple thresholds. Summary of the Invention
[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a multi-threshold logic power device with the ability to store information, a preparation method and a method for simultaneously reading multiple thresholds, so as to solve the problems in the prior art of complex preparation process, high cost and narrow application field of multi-threshold logic power devices.
[0008] To achieve the above-mentioned and other related objectives, the present invention provides a multi-threshold logic power device capable of storing information, the multi-threshold logic power device comprising:
[0009] a first conductivity type epitaxial layer;
[0010] a second conductivity type well region, wherein the second conductivity type well region is located in the first conductivity type epitaxial layer;
[0011] a first conductive type source region, the first conductive type source region being located in the second conductive type well region;
[0012] a trench gate structure, the trench gate structure comprising a gate dielectric layer and a gate conductive layer, the trench gate structure being located in the first conductivity type epitaxial layer and penetrating the first conductivity type source region and the second conductivity type well region;
[0013] A contact structure, wherein the contact structure passes through the first conductive type source region to contact the second conductive type well region, and the contact structure includes a second conductive type contact portion; wherein the contact structure constitutes a contact structure array, the contact structure array has the same common trench gate structure, and the contact structure array is composed of a plurality of contact structure groups, each of the contact structure groups includes at least two contact structures, and the edges of the second conductive type contacts of the same group in the contact structure array have the same lateral spacing from the edge of the channel, and the edges of the second conductive type contacts of different groups have different lateral spacing from the edge of the channel.
[0014] Optionally, the second conductive type contacts in the same group have the same doping concentration, and the second conductive type contacts in different groups have different doping concentrations.
[0015] Optionally, the doping concentration of the second conductive type contacts in different groups decreases as the lateral spacing increases.
[0016] Optionally, the contact structure includes a second conductive type contact portion located in the second conductive type well region and a metal contact portion penetrating the first conductive type source region and contacting the second conductive type contact portion.
[0017] Optionally, the contact structure has a shape of one or a combination of a rectangle and a square; and the trench gate structure has a shape of one or a combination of a rectangle and a square.
[0018] Optionally, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.
[0019] Optionally, the multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET to store digital information in the threshold of the multi-threshold logic power device.
[0020] The present invention also provides a method for preparing a multi-threshold logic power device capable of storing information, comprising the following steps:
[0021] A semiconductor substrate is provided, comprising a first conductivity type epitaxial layer, a second conductivity type well region, a first conductivity type source region, and a trench gate structure; wherein the second conductivity type well region is located within the first conductivity type epitaxial layer, the first conductivity type source region is located within the second conductivity type well region, and the trench gate structure comprises a gate dielectric layer and a gate conductive layer, the trench gate structure is located within the first conductivity type epitaxial layer and penetrates the first conductivity type source region and the second conductivity type well region;
[0022] A contact mask is formed on the semiconductor substrate, and a contact structure is formed in the semiconductor substrate through the contact mask, wherein the contact structure passes through the first conductive type source region to contact the second conductive type well region, and the contact structure includes a second conductive type contact portion; wherein the formed contact structures constitute a contact structure array, the contact structure array has the same common trench gate structure, and the contact structure array is composed of a plurality of contact structure groups, each of the contact structure groups includes at least two contact structures, and the edges of the second conductive type contacts in the same group in the contact structure array have the same lateral spacing from the channel edge, and the edges of the second conductive type contacts in different groups have different lateral spacing from the channel edge.
[0023] Optionally, in the formed contact structure groups, the second conductive type contact portions in the same group have the same doping concentration, and the second conductive type contact portions in different groups have different doping concentrations.
[0024] Optionally, in the contact structure group, the doping concentration of the second conductive type contact portion formed decreases as the lateral spacing increases.
[0025] Optionally, the step of forming the contact structure includes:
[0026] Etching the first conductive type source region through a contact mask to form a contact trench penetrating the first conductive type source region;
[0027] implanting second conductivity type impurities into the second conductivity type well region through the contact mask to form a second conductivity type contact portion;
[0028] A metal contact portion filling the contact trench is formed through the contact mask, and the metal contact portion is in contact with the second conductive type contact portion.
[0029] Optionally, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.
[0030] Optionally, the prepared multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET to store digital information in the threshold of the multi-threshold logic power device.
[0031] Optionally, the step of preparing the semiconductor substrate includes:
[0032] forming a first conductivity type epitaxial layer;
[0033] forming a trench gate structure in the first conductive type epitaxial layer, wherein the trench gate structure includes a gate dielectric layer and a gate conductive layer;
[0034] forming a second conductivity type well region in the first conductivity type epitaxial layer between the trench gate structures through a well region mask;
[0035] A first conductive type source region is formed in the second conductive type well region through a source region mask.
[0036] The present invention also provides a method for simultaneously reading multiple thresholds of a multi-threshold logic power device capable of storing information, comprising the following steps:
[0037] Provide multi-threshold logic power devices;
[0038] When in saturation mode: Scan the voltage of the common gate V g , voltage V g The scanning range covers all threshold voltages Vt, and each threshold voltage V t When conducting, the corresponding I dwill increase, and the transconductance will show a peak value, representing "1". d When there is no increase and the transconductance does not show a peak, it means it is at "0";
[0039] When in linear mode: Sweep the common gate voltage V g , voltage V g The scanning range covers all threshold voltages Vt, and each threshold voltage V t The corresponding I d The slope will increase and the transconductance will rise, indicating that it is at "1". If the slope does not increase and the transconductance does not rise, it means that it is at "0".
[0040] As described above, the multi-threshold logic power device with information storage capability, the preparation method, and the method for simultaneously reading multiple thresholds of the present invention have the following beneficial effects:
[0041] When preparing the contact structure, a contact structure array having the same common trench gate structure can be formed by patterning the contact mask, wherein the contact structure array is composed of a plurality of contact structure groups, each contact structure group includes at least two contact structures, and in the contact structure array, the edges of the second conductive type contact portions of the same group have the same lateral spacing from the channel edge, while the edges of the second conductive type contact portions of different groups have different lateral spacings from the channel edge, so as to realize multi-threshold logic states, thereby realizing multi-threshold logic states for power devices to store information through external circuits; the present invention can prepare devices with different threshold voltages V without adding any additional process steps. t The multi-threshold logic power device with the ability to store information has a simple preparation process, low cost, and a wide range of applications; the threshold voltage V t The number of can be flexibly designed to store multi-bit digital information or analog information in power devices; built-in multiple threshold voltage V t The power MOSFET and IGBT can be used in high current applications and have the ability to store information; by scanning the voltage V g , and constructing transconductors, which can conveniently and simultaneously read multi-bit information stored in logic power devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] Figure 1 Shown is a schematic structural diagram of a multi-threshold logic transistor in the prior art.
[0043] Figure 2 Display as Figure 1 Schematic diagram of the circuit connection of the multi-threshold logic transistor in .
[0044] Figure 3Shown is a schematic diagram of the process flow for preparing a multi-threshold logic power device in an embodiment of the present invention.
[0045] Figure 4 Shown is a schematic structural diagram of a unit of a multi-threshold logic power device according to an embodiment of the present invention.
[0046] Figure 5 Shown is a partial top view structural diagram of a multi-threshold logic power device according to an embodiment of the present invention.
[0047] Figure 6 It is a schematic diagram of an enlarged structure of the lateral distance between the second conductive type contact portion and the channel edge in an embodiment of the present invention.
[0048] Figure 7 Shown is a circuit connection diagram of a multi-threshold logic power device in an embodiment of the present invention.
[0049] Figure 8 The threshold voltage V is shown in the embodiment of the present invention. t Schematic diagram of the simulation relationship with changes in lateral spacing.
[0050] Figure 9 The V of the multi-threshold logic power device obtained in saturation mode according to an embodiment of the present invention is shown. g -I d Relationship diagram.
[0051] Figure 10 show Figure 9 Transconductance dI d / dV g Schematic diagram of the relationship.
[0052] Figure 11 The V of the multi-threshold logic power device obtained in the linear mode according to the embodiment of the present invention is shown. g -I d Relationship diagram.
[0053] Figure 12 show Figure 11 Transconductance dI d / dV g Schematic diagram of the relationship.
[0054] Component number description
[0055] 101 first conductive type substrate
[0056] 102 first conductivity type epitaxial layer
[0057] 103 Trench Gate Structure
[0058] 1031 gate dielectric layer
[0059] 1032 gate conductive layer
[0060] 104 second conductivity type well region
[0061] 105 first conductivity type source region
[0062] 106 second conductive type contact portion
[0063] 107 Channel
[0064] 108 interlayer dielectric layer
[0065] 1091 Source Metal Layer
[0066] 1092 gate metal layer
[0067] 1093 drain metal layer
[0068] A contact structure array
[0069] a Contact structure group
[0070] D Horizontal spacing DETAILED DESCRIPTION
[0071] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.
[0072] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.
[0073] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may be present. As used herein, "between" is inclusive of both endpoints.
[0074] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.
[0075] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.
[0076] like Figure 3 As shown, this embodiment provides a method for preparing a multi-threshold logic power device with information storage capability, wherein, when preparing the contact structure, a contact structure array having the same common trench gate structure can be formed by patterning the contact mask, the contact structure array being composed of a plurality of contact structure groups, each contact structure group including at least two contact structures, and the edges of the second conductive type contacts of the same group in the contact structure array have the same lateral spacing from the channel edge, while the edges of the second conductive type contacts of different groups have different lateral spacings from the channel edge to achieve multi-threshold logic states, thereby enabling the power device to have multi-threshold logic states to store information through an external circuit; the present invention can prepare devices with different threshold voltages V without adding any additional process steps. t The multi-threshold logic power device has a simple preparation process, low cost, and a wide range of applications; the threshold voltage V t The number of can be flexibly designed and can be used to store multi-bit digital information or analog information in power devices; built-in multi-threshold voltage V t The power MOSFET and IGBT can be used in high current applications and have the ability to store information; by scanning the voltage V g , and constructing transconductors, which can conveniently and simultaneously read multi-bit information stored in logic power devices.
[0077] As an example, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.
[0078] In this embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but it is not limited to this. In another embodiment, the first conductivity type may also be p-type and the second conductivity type may be n-type. There is no excessive restriction here.
[0079] As an example, the prepared multi-threshold logic power device may include a multi-threshold logic MOSFET or a multi-threshold logic IGBT, etc., wherein the multi-threshold logic MOSFET may include a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET, etc., to store digital information in the threshold of the multi-threshold logic power device.
[0080] Specifically, the specific type and structure of the multi-threshold logic power device can be prepared according to the needs of the relevant functional layers, and no excessive restrictions are made here. Figure 4 , further description is given by taking a multi-threshold logic VDMOSFET as an example, but the type of the multi-threshold logic power device is not limited thereto.
[0081] The structure and manufacturing method of the multi-threshold logic power device of this embodiment will be further explained below with reference to the accompanying drawings.
[0082] First, a semiconductor substrate is provided, which includes a first conductive type epitaxial layer 102, a second conductive type well region 104, a first conductive type source region 105 and a trench gate structure 103; wherein, the second conductive type well region 104 is located in the first conductive type epitaxial layer 102, the first conductive type source region 105 is located in the second conductive type well region 104, and the trench gate structure 103 includes a gate dielectric layer 1031 and a gate conductive layer 1032, and the trench gate structure 103 is located in the first conductive type epitaxial layer 102 and penetrates the first conductive type source region 105 and the second conductive type well region 104, thereby forming a vertical double channel 107. It can be understood that Figure 4 Only one device unit of the multi-threshold logic power device is illustrated in the figure. In actual applications, the multi-threshold logic power device may include a plurality of identical or different device units that are repeatedly arranged.
[0083] As an example, the steps of preparing the semiconductor substrate include:
[0084] Providing a first conductive type substrate 101;
[0085] forming a first conductive type epitaxial layer 102 on the first conductive type substrate 101;
[0086] forming a trench gate structure 103 in the first conductivity type epitaxial layer 102 , wherein the trench gate structure 103 includes a gate dielectric layer 1031 and a gate conductive layer 1032 ;
[0087] Forming a second conductivity type well region 104 in the first conductivity type epitaxial layer 102 between the trench gate structures 103 through a well region mask;
[0088] A first conductivity type source region 105 is formed in the second conductivity type well region 104 through a source region mask.
[0089] The above steps and structures for forming the semiconductor substrate can be flexibly changed according to specific needs and are not limited thereto.
[0090] Specifically, first, the first conductive type substrate 101 is provided. The material of the first conductive type substrate 101 can be doped semiconductor materials such as silicon (Si), silicon germanium (SiGe), gallium nitride (GaN) or silicon carbide (SiC), and the specific type is not overly restricted here.
[0091] Next, a first conductive type epitaxial layer 102 is formed on the first conductive type substrate 101 by epitaxial (epi) growth.
[0092] Next, the trench gate structure 103 is formed in the first conductivity type epitaxial layer 102 . The trench gate structure 103 includes a gate dielectric layer 1031 and a gate conductive layer 1032 .
[0093] In this embodiment, the trench gate structure 103 can reduce the unit area of the power device, and the steps of preparing the trench gate structure 103 may include:
[0094] Etching the first conductive type epitaxial layer 102 to form a gate trench;
[0095] Using a thermal oxidation growth process, a gate dielectric layer 1031 is grown on the surface of the gate trench to cover the bottom and sidewalls of the gate trench;
[0096] Polysilicon is deposited in the gate trench to form the gate conductive layer 1032 .
[0097] The method for preparing the trench gate structure 103 is not limited thereto, and a split gate structure may be selected as needed. The specific preparation process and structure are not limited here.
[0098] Then, if Figure 4 and Figure 5 , preparing the contact structure, comprising the following steps:
[0099] A contact mask is formed on the semiconductor substrate, and the contact structure is formed in the semiconductor substrate through the contact mask, wherein the contact structure passes through the first conductive type source region 105 to contact the second conductive type well region 104, and the contact structure includes a second conductive type contact portion 106; wherein the formed contact structure includes a contact structure array A, the contact structure array A has the same common trench gate structure 103, and the contact structure array A is composed of a plurality of contact structure groups a, each of the contact structure group a includes at least two contact structures, and the edges of the second conductive type contact portions 106 of the same group in the contact structure array A have the same lateral spacing D from the edges of the channel 107, and the edges of the second conductive type contact portions 106 of different groups have different lateral spacing D from the edges of the channel 107.
[0100] Specifically, a mask material layer may be deposited on the surface of the semiconductor substrate, wherein the deposition method may include chemical vapor deposition, and the mask material layer may be a silicon dioxide layer, but is not limited thereto.
[0101] Then, a graphic photoresist layer defining the contact structure can be formed on the surface of the mask material layer through a photolithography process, and the mask material layer can be dry-etched using the photoresist layer as an etching mask through a dry etching process to form a contact mask having the contact structure pattern.
[0102] Next, second conductivity type impurities are implanted into the first conductivity type source region 105 through the patterned contact mask to form the contact structure in contact with the second conductivity type well region 104 .
[0103] In this embodiment, the contact structure is formed by injecting second conductivity type impurities into the first conductivity type source region 105 to short-circuit the first conductivity type source region 105. The contact structure thus formed is directly the second conductivity type contact portion 106. However, the type and structure of the contact structure are not limited thereto. For example, the contact structure may also adopt a trench contact structure. The steps of forming the trench contact structure may include:
[0104] Etching the first conductive type source region 105 through the contact mask to form a contact trench penetrating the first conductive type source region 105 ;
[0105] Implanting second conductivity type impurities into the second conductivity type well region 104 through the contact mask to form a second conductivity type contact portion 106;
[0106] A metal contact portion filling the contact trench is formed through the contact mask, and the metal contact portion is in contact with the second conductive type contact portion 106 .
[0107] The trench contact structure can be used to form a second conductivity type contact portion 106 located within the second conductivity type well region 104 and a metal contact portion, such as metal W, that penetrates the first conductivity type source region 105 and contacts the second conductivity type contact portion 106, thereby further reducing on-resistance and reducing the area of a conventional planar contact structure. The specific selection of the contact structure is not overly restrictive.
[0108] like Figure 5 and Figure 6 As shown, in this embodiment, a plurality of contact structure arrays A can be formed by patterning the contact mask, wherein, in the contact structure array A, a plurality of the contact structures have the same common trench gate structure 103, and the contact structure array A is composed of a plurality of contact structure groups a, each of the contact structure groups a including two contact structures, and the edges of the second conductive type contact portions 106 of the same group have the same lateral spacing D from the edges of the channel 107, so as to form a replacement unit by two or more of the contact structures, wherein the number of the contact structures in the contact structure group a is not limited thereto, and may also be 3, 4, etc., and may be specifically set as required. In the contact structure array A, the edges of the second conductive type contact portions 106 of different groups have different lateral spacings D from the edges of the channel 107, so as to realize multi-threshold logic states, such as Figure 6 As shown. Thus, the power device can be made to have multiple threshold logic states to store information through an external circuit. This embodiment can prepare devices with different threshold voltages V without adding any additional process steps. t The multi-threshold logic power device having the ability to store information has a simple preparation process, low cost, and a wide range of applications; and the threshold voltage V t The number of can be flexibly designed to store multi-bit digital information or analog information in the power device; the built-in multi-threshold voltage V t Power MOSFETs and IGBTs can be used in high current applications and have the ability to store information.
[0109] As an example, the second conductive type contacts 106 in the same group have the same doping concentration, and the second conductive type contacts 106 in different groups may have different doping concentrations.
[0110] Specifically, by different doping concentrations, the multi-threshold voltage Vt The specific doping amount is not limited here, wherein the doping element type of the second conductive type contact portion 106 may include B, but is not limited thereto, and can be specifically selected according to the conductive type and requirements.
[0111] As an example, the doping concentration of the second conductive type contact portions 106 in different groups decreases as the lateral distance D increases, so as to further enhance the formation of multiple threshold voltages V t For example, the doping concentration of the second conductive type contact portion 106 may also increase or randomly change as the lateral distance D increases.
[0112] As an example, in the contact structure array A, the distribution of different groups of the second conductive type contact portions 106 may be discrete, that is, randomly distributed as needed, but is not limited thereto.
[0113] As an example, the morphology of the contact structure includes one or a combination of a rectangle and a square; the morphology of the trench gate structure 103 includes one or a combination of a rectangle and a square; the size, morphology, etc. of the contact structure and the trench gate structure 103 are not overly restricted here and can be selected as needed.
[0114] As an example, the lateral distance D between the edge of the second conductive type contact portion 106 and the edge of the channel 107 in the contact structure may range from 0 μm to 3 μm, but is not limited thereto and may be set as needed.
[0115] As an example, the steps of forming an interlayer dielectric layer 108, a source metal layer 1091, a gate metal layer 1092, and a drain metal layer 1093 may also be included to form the multi-threshold logic VDMOSFET. The order of the steps for forming the multi-threshold logic VDMOSFET may be selected based on specific needs and is not excessively limited herein.
[0116] As an example, the method further includes forming a first conductive type buffer layer on the lower surface of the first conductive type epitaxial layer 102 .
[0117] Specifically, the doping concentration of the first conductive type buffer layer can be between the doping concentrations of the first conductive type substrate 101 and the first conductive type epitaxial layer 102, so as to prevent the impurity atoms of the first conductive type substrate 101 from diffusing into the first conductive type epitaxial layer 102 during the high-temperature process in the multi-threshold logic VDMOSFET through the first conductive type buffer layer, thereby avoiding the increase in the doping concentration of the first conductive type epitaxial layer 102 and the resulting decrease in breakdown voltage, and the first conductive type substrate 101 can be used to solve the problem of tail current when the device is turned off.
[0118] This embodiment also provides a method for preparing a multi-threshold logic IGBT. Figure 4 The main difference between the preparation of the multi-threshold logic VDMOSFET in the above method is that an additional second conductivity type injection layer is added between the drain metal layer 1093 and the first conductivity type epitaxial layer 102. Specifically, the first conductivity type substrate 101 can be removed by CMP, and the second conductivity type impurities can be implanted to form the second conductivity type injection layer, but the present invention is not limited to this.
[0119] See Figure 7 , which shows a circuit connection diagram of the multi-threshold logic power device. In this embodiment, the multi-threshold logic power device is tested through simulation. The results are shown in the following table and Figure 8 .
[0120]
[0121]
[0122] It should be noted that, in the above table, negative values represent the values of the lateral spacing D set when the second conductive type contact portion 106 approaches the channel 107 from the reference position, and positive values represent the values of the lateral spacing D set when the second conductive type contact portion 106 moves away from the reference position from the channel 107. Figure 6 Understand. Figure 8 It can be seen that when the lateral distance D is smaller, the threshold voltage V t The higher.
[0123] like Figure 4This embodiment also provides a multi-threshold logic power device with the ability to store information. The multi-threshold logic power device can be prepared using the above-mentioned method, but is not limited to this. The preparation, material, etc. of the multi-threshold logic power device can be set as needed, and no excessive restrictions are made here. The multi-threshold logic power device described in this embodiment is directly prepared using the above-mentioned preparation method. Therefore, the material, preparation process, etc. of the multi-threshold logic power device are not detailed here.
[0124] Specifically, the multi-threshold logic power device includes a first conductive type epitaxial layer 102, a second conductive type well region 104, a first conductive type source region 105, a trench gate structure 103 and a contact structure. The second conductive type well region 104 is located in the first conductive type epitaxial layer 102, the first conductive type source region 105 is located in the second conductive type well region 104, the trench gate structure 103 includes a gate dielectric layer 1031 and a gate conductive layer 1032, the trench gate structure 103 is located in the first conductive type epitaxial layer 102, and penetrates the first conductive type source region 105 and the second conductive type well region 104, the contact structure penetrates the first conductive type source region 105 to contact the second conductive type well region 104, and the contact structure includes The second conductive type contact portion 106 is included; wherein the contact structure formed constitutes a contact structure array A, the contact structure array A has the same common trench gate structure 103, and the contact structure array A is composed of a plurality of contact structure groups a, each of the contact structure group a includes at least two contact structures, and the edges of the second conductive type contact portions 106 in the same group in the contact structure array A have the same lateral spacing D from the edges of the channel 107, and the edges of the second conductive type contact portions 106 in different groups have different lateral spacing D from the edges of the channel 107.
[0125] As an example, the second conductive type contacts 106 in the same group have the same doping concentration, and the second conductive type contacts 106 in different groups have different doping concentrations.
[0126] Specifically, the effect of forming multiple threshold voltages Vt can be further enhanced by different doping concentrations. The specific doping amount is not limited here. The doping element type of the second conductive type contact portion 106 may include B, but is not limited to this. It can be selected according to the conductive type and requirements.
[0127] As an example, in different groups, the doping concentration of the second conductive type contact portion 106 decreases as the lateral distance D increases, so as to further enhance the formation of multiple threshold voltages V tFor example, the doping concentration of the second conductive type contact portion 106 may also increase or randomly change as the lateral distance D increases.
[0128] As an example, in the contact structure array A, the second conductive type contact portions 106 may be distributed discretely, that is, randomly distributed as needed, but the invention is not limited thereto.
[0129] As an example, the morphology of the contact structure includes one or a combination of a rectangle and a square; the morphology of the trench gate structure 103 includes one or a combination of a rectangle and a square; the size, morphology, etc. of the contact structure and the trench gate structure 103 are not overly restricted here and can be selected as needed.
[0130] As an example, the contact structure includes a second conductive type contact portion 106 located in the second conductive type well region 104 and a metal contact portion that penetrates the first conductive type source region 105 and contacts the second conductive type contact portion 106 to provide a trench contact structure, but is not limited thereto.
[0131] As an example, the first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.
[0132] As an example, the multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET to store digital information in the threshold of the multi-threshold logic power device.
[0133] This embodiment also provides a method for simultaneously reading multiple thresholds of a multi-threshold logic power device capable of storing information, comprising the following steps:
[0134] Provide multi-threshold logic power devices;
[0135] When in saturation mode: Scan the common gate voltage V g , voltage V g The scanning range covers all threshold voltages Vt, and each threshold voltage V t When conducting, the corresponding I d will increase, and the transconductance will show a peak value, representing "1". d When there is no increase and the transconductance does not show a peak, it means it is at "0";
[0136] When in linear mode: Sweep the common gate voltage V g , voltage V gThe scanning range covers all threshold voltages Vt, and each threshold voltage V t The corresponding I d The slope will increase and the transconductance will rise, indicating it is at "1". If the slope does not increase and the transconductance does not rise, it indicates it is at "0".
[0137] Specifically, built-in discrete, multi-V t Power MOS or IGBT, etc., can store multiple bits of digital information in the power switch. t The state can be designed by the spacing between the contact structure and the vertical channel.
[0138] The reading methods include:
[0139] 1) Method for reading multiple thresholds simultaneously in saturation mode: bias V d ~10V, scan V g , voltage V g The scan range is large enough to cover all threshold voltages Vt. t Each time it is turned on, I d -V g Middle I d will increase, which means "1", thus V t Each step of conduction, the transconductance dI d / dV g The peak value will be displayed, which means "1". On the contrary, if I d When there is no increase and the transconductance does not show a peak, it means it is at "0". Figure 9 and Figure 10 , which illustrates a relationship diagram obtained by simultaneously reading multiple thresholds of a multi-threshold logic power device in saturation mode.
[0140] 2) Method for reading multiple thresholds simultaneously in linear mode: Make the bias V d ~1V, scan V g , voltage V g The scan range is large enough to cover all threshold voltages Vt. t Each time it is turned on, I d -V g Middle I d The slope will gradually increase, that is, the slope increases, which represents the "1" bit, so each time Vt is turned on, the transconductance dI d / dV g If the display rises, it means "1". If the slope does not increase and the transconductance does not rise, it means it is at "0". Figure 11 and Figure 12 , which illustrates a relationship diagram obtained by simultaneously reading multiple thresholds of a multi-threshold logic power device in saturation mode.
[0141] The multi-threshold logic power device may include the multi-threshold logic power device described above but is not limited thereto, and may also include a multi-threshold logic power device having a FinFET structure.
[0142] In summary, the multi-threshold logic power device with information storage capability, the preparation method, and the method for simultaneously reading multiple thresholds of the present invention, when preparing the contact structure, can form a contact structure array with the same common trench gate structure through the pattern design of the contact mask, wherein the contact structure array is composed of a plurality of contact structure groups, each contact structure group includes at least two contact structures, and the contact structure array is composed of a plurality of contact structure groups, each contact structure group includes at least two contact structures, and the edges of the second conductive type contacts in the same group in the contact structure array have the same lateral spacing from the channel edge, and the edges of the second conductive type contacts in different groups have different lateral spacings from the channel edge to achieve multi-threshold logic states, so that the power device can have multi-threshold logic states to store information through an external circuit; the present invention can prepare devices with different threshold voltages V without adding any additional process steps. t The multi-threshold logic power device has the ability to store information, is simple to prepare, low cost, and has a wide range of applications; the threshold voltage V t The number of can be flexibly designed to store multi-bit digital information or analog information in power devices; built-in multiple threshold voltage V t The power MOSFET and IGBT can be used in high current situations and have the ability to store information; by scanning the voltage V g , and constructing transconductors, which can conveniently and simultaneously read multi-bit information stored in logic power devices.
[0143] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.
Claims
1. A multi-threshold logic power device, characterized in that: The multi-threshold logic power device comprises: a first conductivity type epitaxial layer; a second conductivity type well region, wherein the second conductivity type well region is located in the first conductivity type epitaxial layer; a first conductive type source region, the first conductive type source region being located in the second conductive type well region; a trench gate structure, the trench gate structure comprising a gate dielectric layer and a gate conductive layer, the trench gate structure being located in the first conductivity type epitaxial layer and penetrating the first conductivity type source region and the second conductivity type well region; A contact structure, wherein the contact structure passes through the first conductive type source region to contact the second conductive type well region, and the contact structure includes a second conductive type contact portion; wherein the contact structure constitutes a contact structure array, the contact structure array has the same common trench gate structure, and the contact structure array is composed of a plurality of contact structure groups, each of the contact structure groups includes at least two contact structures, and the edges of the second conductive type contacts in the same group in the contact structure array have the same lateral spacing from the edge of the channel, and the edges of the second conductive type contacts in different groups have different lateral spacing from the edge of the channel, the second conductive type contacts in the same group have the same doping concentration, and the second conductive type contacts in different groups have different doping concentrations.
2. The multi-threshold logic power device according to claim 1, wherein: The doping concentration of the second conductive type contacts in different groups decreases as the lateral distance increases.
3. The multi-threshold logic power device according to claim 1, wherein: The contact structure includes a second conductive type contact portion located in the second conductive type well region and a metal contact portion penetrating the first conductive type source region and contacting the second conductive type contact portion.
4. The multi-threshold logic power device according to claim 1, wherein: The contact structure has a shape of a rectangle and a square or a combination thereof; the trench gate structure has a shape of a rectangle and a square or a combination thereof.
5. The multi-threshold logic power device according to claim 1, wherein: The first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.
6. The multi-threshold logic power device according to claim 1, wherein: The multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET to store digital information in the threshold of the multi-threshold logic power device.
7. A method for preparing a multi-threshold logic power device, characterized in that: The following steps are involved: A semiconductor substrate is provided, comprising a first conductivity type epitaxial layer, a second conductivity type well region, a first conductivity type source region, and a trench gate structure; wherein the second conductivity type well region is located within the first conductivity type epitaxial layer, the first conductivity type source region is located within the second conductivity type well region, and the trench gate structure comprises a gate dielectric layer and a gate conductive layer, the trench gate structure is located within the first conductivity type epitaxial layer and penetrates the first conductivity type source region and the second conductivity type well region; A contact mask is formed on the semiconductor substrate, and a contact structure is formed in the semiconductor substrate through the contact mask, wherein the contact structure passes through the first conductive type source region to contact the second conductive type well region, and the contact structure includes a second conductive type contact portion; wherein the formed contact structures constitute a contact structure array, the contact structure array has the same common trench gate structure, and the contact structure array is composed of a plurality of contact structure groups, each of the contact structure groups includes at least two contact structures, and the edges of the second conductive type contacts in the same group in the contact structure array have the same lateral spacing from the channel edge, and the edges of the second conductive type contacts in different groups have different lateral spacing from the channel edge, and in the formed contact structure groups, the second conductive type contacts in the same group have the same doping concentration, and the second conductive type contacts in different groups have different doping concentrations.
8. The preparation method according to claim 7, characterized in that: In the contact structure group, the doping concentration of the second conductive type contact portion formed decreases as the lateral spacing increases.
9. The preparation method according to claim 7, characterized in that The steps of forming the contact structure include: Etching the first conductive type source region through a contact mask to form a contact trench penetrating the first conductive type source region; implanting second conductivity type impurities into the second conductivity type well region through the contact mask to form a second conductivity type contact portion; A metal contact portion filling the contact trench is formed through the contact mask, and the metal contact portion is in contact with the second conductive type contact portion.
10. The preparation method according to claim 7, characterized in that: The first conductivity type is n-type, and the second conductivity type is p-type; or the first conductivity type is p-type, and the second conductivity type is n-type.
11. The preparation method according to claim 7, characterized in that: The prepared multi-threshold logic power device includes a multi-threshold logic MOSFET or a multi-threshold logic IGBT, wherein the multi-threshold logic MOSFET includes a multi-threshold logic VDMOSFET or a multi-threshold logic LDMOSFET to store digital information in the threshold of the multi-threshold logic power device.
12. The preparation method according to claim 7, characterized in that The steps of preparing the semiconductor substrate include: forming a first conductivity type epitaxial layer; forming a trench gate structure in the first conductive type epitaxial layer, wherein the trench gate structure includes a gate dielectric layer and a gate conductive layer; forming a second conductivity type well region in the first conductivity type epitaxial layer between the trench gate structures through a well region mask; A first conductive type source region is formed in the second conductive type well region through a source region mask.
13. A method for simultaneously reading multiple thresholds of a multi-threshold logic power device, characterized in that: The following steps are involved: Providing a multi-threshold logic power device as claimed in any one of claims 1 to 6; When in saturation mode: Scan the common gate voltage V g , voltage V g The scanning range covers all threshold voltages Vt, and each threshold voltage V t When conducting, the corresponding I d will increase, and the transconductance will show a peak value, representing "1". If I d When there is no increase and the transconductance does not show a peak, it means it is at "0"; When in linear mode: Sweep the common gate voltage V g , voltage V g The scanning range covers all threshold voltages Vt, and each threshold voltage V t The corresponding I d The slope will increase and the transconductance will rise, indicating it is at "1". If the slope does not increase and the transconductance does not rise, it indicates it is at "0".
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