A monitoring circuit, a chip and an electronic device for a clock signal

Abstract

This application relates to a monitoring circuit for a clock signal. The clock signal includes a first clock signal and a second clock signal with opposite phases; the monitoring circuit includes: a charge and discharge module and an output module, where: The charge and discharge module is used to receive the clock signal and perform charge and discharge according to the clock signal to generate a first voltage signal and a second voltage signal; the first voltage signal is generated by the charge and discharge module according to the first clock signal, and the second voltage signal is generated by the charge and discharge module according to the second clock signal; The output module is used to generate a first monitoring result according to the first voltage signal and the second voltage signal. This monitoring circuit mainly uses the charge and discharge module to perform charge and discharge according to the clock signal, thereby bringing about a voltage change, and uses the output module to generate a monitoring result indicating whether the clock signal is abnormal according to this voltage change. The principle and structure of this solution are relatively simple, easy to implement, and can also effectively reduce costs.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a monitoring circuit, a chip, and an electronic device for a clock signal. Background Art

[0002] Clock oscillators are widely used in the electronic design industry and on chip-level systems (System on Chip, SOC). However, due to characteristics such as process and stability, there are risks in the accuracy and reliability of oscillator oscillation. There may be a risk of oscillation stop under extreme external environmental stimuli interference, such as voltage mutation, electrostatic interference, etc. After the oscillator stops oscillating, it will seriously affect the oscillation accuracy and reliability. But most traditional monitoring schemes are too complex. Summary of the Invention

[0003] This application provides a monitoring circuit, a chip, and an electronic device for a clock signal. The monitoring circuit has a simple structure and can effectively monitor the clock signal.

[0004] In a first aspect, this application provides a monitoring circuit for a clock signal. The clock signal includes a first clock signal and a second clock signal, and the phases of the first clock signal and the second clock signal are opposite. The monitoring circuit includes a charge and discharge module and an output module, where: The charge and discharge module is configured to receive the clock signal and perform charge and discharge according to the clock signal to generate a first voltage signal and a second voltage signal. The first voltage signal is generated by the charge and discharge module according to the first clock signal, and the second voltage signal is generated by the charge and discharge module according to the second clock signal. The output module is configured to generate a first monitoring result according to the first voltage signal and the second voltage signal.

[0005] In one embodiment, the charge and discharge module includes: a first charge and discharge unit and a second charge and discharge unit, where: The first charge and discharge unit is connected to the positive power supply terminal, and is configured to receive the first clock signal, perform charge and discharge according to the first clock signal and the electrical energy provided by the positive power supply terminal to obtain the first voltage signal, and send the first voltage signal to the output module. The second charge and discharge unit is connected to the positive power supply terminal, and is configured to receive the second clock signal, perform charge and discharge according to the second clock signal and the electrical energy provided by the positive power supply terminal to obtain the second voltage signal, and send the second voltage signal to the output module.

[0006] In one embodiment, the first charge and discharge unit includes a first series inverse ratio transistor, a first capacitor, and a first MOS transistor; the second charge and discharge unit includes a second series inverse ratio transistor, a second capacitor, and a second MOS transistor;

[0007] The control terminal of the first MOS transistor is the input terminal of the first charge-discharge unit; the first terminal of the first MOS transistor is connected to the positive power supply; the second terminal of the first MOS transistor is respectively connected to the second terminal of the first series inverse ratio transistor, the control terminal of the first series inverse ratio transistor, and the first terminal of the first capacitor, serving as the output terminal of the first charge-discharge unit for outputting a first voltage signal;

[0008] The first terminal of the first series inverse ratio transistor is respectively connected to the negative power supply and the second terminal of the first capacitor;

[0009] The first capacitor is used to store electrical energy according to the first clock signal; the first series inverse ratio transistor is used to discharge the electrical energy stored in the first capacitor according to the first clock signal;

[0010] The control terminal of the second MOS transistor is the input terminal of the second charge-discharge unit; the first terminal of the second MOS transistor is connected to the positive power supply; the second terminal of the second MOS transistor is respectively connected to the second terminal of the second series inverse ratio transistor, the control terminal of the second series inverse ratio transistor, and the first terminal of the second capacitor, serving as the output terminal of the second charge-discharge unit for outputting a second voltage signal;

[0011] The first terminal of the second series inverse ratio transistor is respectively connected to the negative power supply and the second terminal of the second capacitor;

[0012] The second capacitor is used to store electrical energy according to the second clock signal; the second series inverse ratio transistor is used to discharge the electrical energy stored in the second capacitor according to the second clock signal.

[0013] In one embodiment, the monitoring circuit further includes: a first switch unit, connected to the charge-discharge module, for controlling the working state of the charge-discharge module.

[0014] In one embodiment, the first switch unit includes a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor;

[0015] The second terminal of the third MOS transistor is connected to the first terminal of the first series inverse ratio transistor; the first terminal of the third MOS transistor is connected to the negative power supply;

[0016] The second terminal of the fourth MOS transistor is connected to the first terminal of the second series inverse ratio transistor; the first terminal of the fourth MOS transistor is connected to the negative power supply;

[0017] The second terminal of the fifth MOS transistor is connected to the first terminal of the first capacitor; the first terminal of the fifth MOS transistor is connected to the positive power supply;

[0018] The second terminal of the sixth MOS transistor is connected to the first terminal of the second capacitor; the first terminal of the sixth MOS transistor is connected to the positive power supply.

[0019] In one embodiment, the output module includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and a third series inverse ratio transistor;

[0020] The control terminal of the seventh MOS transistor is connected to the output terminal of the first charge and discharge unit for receiving a first voltage signal; the first terminal of the seventh MOS transistor is respectively connected to the first terminal of the eighth MOS transistor, the second terminal of the ninth MOS transistor, the control terminal of the ninth MOS transistor, and the control terminal of the tenth MOS transistor; the second terminal of the seventh MOS transistor is connected to the negative power supply.

[0021] The control terminal of the eighth MOS transistor is connected to the output terminal of the second charge and discharge unit for receiving a second voltage signal; the second terminal of the eighth MOS transistor is connected to the negative power supply.

[0022] The first terminals of the ninth MOS transistor and the tenth MOS transistor are both connected to the positive power supply.

[0023] The second terminal of the tenth MOS transistor is connected to the second terminal of the third series inverse ratio transistor, which is the output terminal of the output module for outputting a first monitoring result.

[0024] The first terminal of the third series inverse ratio transistor is connected to the negative power supply.

[0025] In one embodiment, the monitoring circuit further includes: a second switch unit connected to the output module for controlling the output voltage of the output module, and the output voltage is used to represent the first monitoring result.

[0026] In one embodiment, the second switch unit includes an eleventh MOS transistor, a twelfth MOS transistor, and a thirteenth MOS transistor;

[0027] The first terminal of the eleventh MOS transistor is connected to the positive power supply; the second terminal of the eleventh MOS transistor is connected to the first terminal of the seventh MOS transistor;

[0028] The first terminal of the twelfth MOS transistor is connected to the negative power supply; the second terminal of the twelfth MOS transistor is connected to the second terminal of the seventh MOS transistor;

[0029] The first terminal of the thirteenth MOS transistor is connected to the negative power supply; the second terminal of the thirteenth MOS transistor is connected to the second terminal of the eighth MOS transistor.

[0030] In one embodiment, when both the first voltage signal and the second voltage signal are high level, the first monitoring result is that the clock is normal; when at least one of the first voltage signal and the second voltage signal is low level, the first monitoring result is that the clock is abnormal.

[0031] In one embodiment, the monitoring circuit further includes: a control module, connected to the output module, for receiving the first monitoring result and generating a control signal according to the first monitoring result, where the control signal is used to control the clock signal generating device to operate according to the control signal.

[0032] The delay unit is connected to the output end of the output module, for receiving the first monitoring result and performing a delay process on the first monitoring result to obtain a second monitoring result;

[0033] The logic operation unit is respectively connected to the output end of the output module and the output end of the delay unit, for receiving the first monitoring result and the second monitoring result and performing a logic operation on the first monitoring result and the second monitoring result to obtain a control signal.

[0034] In one embodiment, the control signal includes a reset signal and / or a restart signal; the first monitoring result includes that the clock signal is normal and the clock signal is abnormal;

[0035] The reset signal is used to control the control module to reset the clock signal generating device when the clock signal is abnormal;

[0036] The restart signal is used to control the control module to restart the clock signal generating device when the clock signal is abnormal.

[0037] In one embodiment, the monitoring circuit further includes: a filtering module, for receiving the first monitoring result, filtering the first monitoring result to obtain a filtered first monitoring result, and sending the filtered first monitoring result to the control module; the input end of the filtering module is connected to the output end of the output module; the output end of the filtering module is connected to the input end of the control module.

[0038] In a second aspect, the present application provides a chip, which includes the monitoring circuit of the first aspect and any one of its implementation manners.

[0039] In a third aspect, the present application provides an electronic device, which includes an oscillator and the monitoring circuit of the first aspect and any one of its implementation manners, where the oscillator is a clock signal generating device, and the monitoring circuit is used to monitor the oscillator.

[0040] The above-mentioned monitoring circuit for the clock signal, where the clock signal includes a first clock signal and a second clock signal, and the phases of the first clock signal and the second clock signal are opposite; the monitoring circuit includes a charge and discharge module and an output module, where: The charge and discharge module is used to receive the clock signal and perform charge and discharge according to the clock signal to generate a first voltage signal and a second voltage signal; the first voltage signal is generated by the charge and discharge module according to the first clock signal, and the second voltage signal is generated by the charge and discharge module according to the second clock signal; the output module is used to generate a first monitoring result according to the first voltage signal and the second voltage signal. It mainly uses the charge and discharge module to perform charge and discharge according to the clock signal, thereby bringing about a voltage change, and uses the output module to generate a monitoring result indicating whether the clock signal is abnormal according to this voltage change. The principle and structure of this solution are relatively simple, easy to implement, and can also effectively reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0042] Figure 1 It is a schematic diagram of a monitoring circuit for a clock signal according to an embodiment of the present application.

[0043] Figure 2 It is a schematic diagram of the charge and discharge module according to an embodiment of the present application.

[0044] Figure 3 It is a schematic diagram of an example of the monitoring circuit according to an embodiment of the present application.

[0045] Figure 4 It is a schematic diagram of the control module according to an embodiment of the present application.

[0046] Figure 5 It is a schematic diagram of another example of the monitoring circuit according to an embodiment of the present application.

[0047] Figure 6 is Figure 5 a schematic diagram of the equivalent circuit of the shown circuit.

[0048] Figure 7 It is a schematic diagram of the clock change of the logical operation of the control module according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application in this specification are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0051] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first resistor may be referred to as the second resistor, and similarly, the second resistor may be referred to as the first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0052] It can be understood that in the following embodiments, "connection", if there is a transfer of electrical signals or data between the connected circuits, modules, units, etc., should be understood as "electrical connection", "communication connection", etc.

[0053] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising", "including" or "having", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.

[0054] Figure 1 is a schematic diagram of a monitoring circuit for a clock signal according to an embodiment of the present application. As Figure 1 shown, the monitoring circuit 100 includes a charge and discharge module 110 and an output module 120, and the output end of the charge and discharge module 110 is connected to the input end of the output module 120.

[0055] The charge and discharge module 110 is used to receive a clock signal, receive the clock signal, and perform charge and discharge according to the clock signal to generate a first voltage signal and a second voltage signal. In the embodiment of the present application, the clock signal includes a first clock signal and a second clock signal, and the phases of the first clock signal and the second clock signal are opposite. The clock signal can be generated by an oscillator, that is, the generating device of the clock signal can be an oscillator. The first voltage signal is generated by the charge and discharge module according to the first clock signal, and the second voltage signal is generated by the charge and discharge module according to the second clock signal.

[0056] The output module 120 is used to generate a first monitoring result according to the first voltage signal and the second voltage signal.

[0057] When the first voltage signal and the second voltage signal act on the circuit of the output module 120, the output voltage of the output module can be changed, and this output voltage can be used as the first monitoring result.

[0058] When the clock signal is normal, both the first clock signal and the second clock signal are periodic electrical signals with alternating high and low levels and the same period. When the clock signal is abnormal, the first clock signal and the second clock signal stay at a high level or a low level, that is, the first clock signal is at a high level and the second clock signal is at a low level; or, the first clock signal is at a low level and the second clock signal is at a high level.

[0059] The above-mentioned monitoring circuit of the clock signal mainly uses the charge and discharge module to perform charge and discharge according to the clock signal, thereby bringing about a voltage change, and uses the output module to generate a monitoring result indicating whether the clock signal is abnormal according to this voltage change. The principle and structure of this solution are relatively simple, easy to implement, and can also effectively reduce costs.

[0060] In one embodiment, as Figure 2 shown, the charge and discharge module 110 includes a first charge and discharge unit 111 and a second charge and discharge unit 112.

[0061] The first charge and discharge unit 111 is connected to the positive pole of the power supply, and is used to receive the first clock signal, perform charge and discharge according to the first clock signal and the electric energy provided by the positive pole of the power supply to obtain a first voltage signal, and send the first voltage signal to the output module 120.

[0062] The second charge and discharge unit 112 is connected to the positive pole of the power supply, and is used to receive the second clock signal, perform charge and discharge according to the second clock signal and the electric energy provided by the positive pole of the power supply to obtain a second voltage signal, and send the second voltage signal to the output module 120.

[0063] It can be seen that the first charge and discharge unit 111 and the second charge and discharge unit 112 are in a parallel relationship, and process the first clock signal and the second clock signal respectively.

[0064] In one embodiment, when both the first voltage signal and the second voltage signal are at a high level, the first monitoring result is that the clock is normal; when at least one of the first voltage signal and the second voltage signal is at a low level, the first monitoring result is that the clock is abnormal.

[0065] Figure 3 It is a schematic diagram of an example of the monitoring circuit according to the embodiments of the present application. Figure 3 can be used as Figure 1 a specific example of. As Figure 3 shown, the monitoring circuit 100 includes a charge and discharge module 110 and an output module 120. The charge and discharge module 110 and the output module 120 can refer to Figure 1 the relevant introduction.

[0066] In one embodiment, the monitoring circuit 100 may further include a switch module 130, and the switch module 130 is used to control the charge and discharge module 110 and / or the output module 120.

[0067] In one embodiment, the switch module 130 includes a first switch unit 131.

[0068] The first switch unit 131 is connected to the charge and discharge module 110 and is used to control the working state of the charge and discharge module 110, and the working state includes charging and discharging. The first switch unit 131 is used to control the charge and discharge module 110 to charge or discharge, so as to change the voltage values of the first voltage signal and the second voltage signal.

[0069] In one embodiment, the switch module 130 further includes a second switch unit 132.

[0070] The second switch unit 133 is connected to the output module 120 and is used to control the output voltage of the output module 120. The output voltage is used to represent the first monitoring result. Specifically, the second switch unit 133 is used to control the on / off of each circuit branch in the output module 120, so as to control the voltage value of the output voltage.

[0071] It should be understood that the second switch unit 133 is equivalent to making the output voltage can only be at a high level or a low level. When it is at a high level, the voltage value is as close as possible to the voltage of the positive power supply terminal, and when it is at a low level, the voltage value is as close as possible to the voltage of the negative power supply terminal (ground voltage). In the absence of the second switch unit 133, the output module 120 can still work, but the voltage value of the output voltage may not be able to be as high or as low as possible, and the voltage value shows a high level or a low level within a certain floating range. That is to say, the second switch unit 133 makes the first monitoring result more accurate.

[0072] In one embodiment, as Figure 3As shown, the monitoring circuit 100 further includes a control module 140. The input end of the control module 140 is connected to the output end of the output module 120. The output end of the control module 140 is used to output a control signal. The control module 140 is configured to receive the first monitoring result and generate a control signal according to the first monitoring result. The control signal is used to control the clock signal generating device to operate according to the control signal.

[0073] In some implementation manners, the control signal includes a reset signal and / or a restart signal; the first monitoring result includes that the clock signal is normal and the clock signal is abnormal; the reset signal is used to control the control module to reset the clock signal generating device when the clock signal is abnormal; the restart signal is used to control the control module to restart the clock signal generating device when the clock signal is abnormal.

[0074] In some implementation manners, as Figure 4 shown, the control module 140 includes a delay unit 141 and a logic operation unit 142. Among them, the delay unit 141 is connected to the output end of the output module 120, and is configured to receive the first monitoring result and perform a delay process on the first monitoring result to obtain a second monitoring result.

[0075] The logic operation unit 142 is respectively connected to the output end of the output module 120 and the output end of the delay unit 141, and is configured to receive the first monitoring result and the second monitoring result, and perform a logic operation on the first monitoring result and the second monitoring result to obtain a control signal.

[0076] In one embodiment, as Figure 3 shown, the monitoring circuit 100 further includes a filtering module 160. The filtering module 160 is configured to receive the first monitoring result, filter the first monitoring result to obtain a filtered first monitoring result, and send the filtered first monitoring result to the control module 140; the input end of the filtering module 150 is connected to the output end of the output module 120; the output end of the filtering module 150 is connected to the input end of the control module 140.

[0077] Figure 5 is a schematic diagram of another example of the monitoring circuit of the embodiment of the present application. Figure 5 can be used as Figure 1 or Figure 3 a specific example of. As Figure 5 shown, the circuit includes MOS transistors PM1-PM9, MOS transistors NM1-NM7, and capacitors C1, C2. Among them, NM1, NM2, and NM7 are series inverse ratio transistors, NM3-NM6 are N-type MOS transistors, and PM1-PM9 are P-type MOS transistors.

[0078] In Figure 5 CLK is the first clock signal, and CLKB is the second clock signal.

[0079] It should be noted that in the following examples, the control terminal of each MOS transistor is the gate of the MOS transistor, the first terminal of each MOS transistor is the source of the MOS transistor, and the second terminal of each MOS transistor is the drain of the MOS transistor.

[0080] It should also be understood that in actual use, those skilled in the art can choose either PMOS transistors or NMOS transistors to achieve the same function. Therefore, Figure 5 the selection of the MOS transistors shown indicates an example, and other selections can also be made. Even a bipolar transistor can be used instead of the MOS transistor.

[0081] In one embodiment, the first charge and discharge unit 111 includes a first series inverse ratio transistor NM1, a first capacitor C1, and a first MOS transistor PM1; the second charge and discharge unit 112 includes a second series inverse ratio transistor NM2, a second capacitor C2, and a second MOS transistor PM2.

[0082] The control terminal (gate) of PM1 is the input terminal of the first charge and discharge unit 111; the first terminal (source) of PM1 is connected to the positive power supply; the second terminal (drain) of PM1 is respectively connected to the drain of NM1, the gate of NM1, and the first terminal of C1, which is the output terminal of the first charge and discharge unit 111 and is used to output the first voltage signal V1; the source of NM1 is respectively connected to the negative power supply and the second terminal of C1; C1 is used to store electrical energy according to CLK, that is, to charge C1 according to CLK; NM1 is used to discharge the electrical energy stored in C1 according to CLK; the gate of PM2 is the input terminal of the second charge and discharge unit 112; the source of PM2 is connected to the positive power supply; the drain of PM2 is respectively connected to the drain of NM2, the gate of NM2, and the first terminal of C2, which is the output terminal of the second charge and discharge unit 112 and is used to output the second voltage signal V2; the source of NM2 is respectively connected to the negative power supply and the second terminal of C2; C2 is used to store electrical energy according to CLKB, that is, to charge C2 according to CLKB; NM2 is used to discharge the electrical energy stored in C2 according to CLKB.

[0083] In one embodiment, the first switch unit 131 includes a third MOS transistor NM3, a fourth MOS transistor NM4, a fifth MOS transistor PM5, and a sixth MOS transistor PM6.

[0084] The drain of NM3 is connected to the source of NM1; the source of NM3 is connected to the negative power supply; the drain of NM4 is connected to the source of NM2; the source of NM4 is connected to the negative power supply; the drain of PM5 is connected to the source of C1; the source of PM5 is connected to the positive power supply; the drain of PM6 is connected to the source of C2; the source of PM6 is connected to the positive power supply.

[0085] In one embodiment, the output module 120 includes a seventh MOS transistor PM3, an eighth MOS transistor PM4, a ninth MOS transistor PM8, a tenth MOS transistor PM9, and a third series inverse ratio transistor NM7. The gate of the PM3 transistor is connected to the output terminal of the first charge and discharge unit 111 for receiving V1; the source of the PM3 is respectively connected to the source of the PM4, the drain of the PM8, the gate of the PM8, and the gate of the PM9; the drain of the PM3 is connected to the negative power supply; the gate of the PM4 is connected to the output terminal of the second charge and discharge unit 112 for receiving V2; the drain of the PM4 is connected to the negative power supply; the sources of the PM8 and PM9 are both connected to the positive power supply; the drain of the PM9 is connected to the drain of the NM7, which is the output terminal of the output module 120 for outputting the first monitoring result (V4); the source of the NM7 is connected to the negative power supply. The PM8 and PM9 form a current mirror.

[0086] In one embodiment, the second switch unit 132 includes an eleventh MOS transistor PM7, a twelfth MOS transistor NM5, and a thirteenth MOS transistor NM6. The source of the PM7 is connected to the positive power supply; the drain of the PM7 is connected to the source of the PM3; the source of the NM5 is connected to the negative power supply; the drain of the NM5 is connected to the drain of the PM3; the source of the NM6 is connected to the negative power supply; the drain of the NM6 is connected to the drain of the PM4.

[0087] In one embodiment, the filtering module 150 includes a Schmitt trigger Schmitter and an inverter 1Inv1. The control module 140 includes a delay unit 141D1 and a logic operation unit 142CT1. The CT1 includes an inverter 2Inv2 and a NAND gate. The input terminal of the Schmitt trigger is connected to the drain of the PM9 and the drain of the NM7 for receiving V4. The output terminal of the Schmitt trigger is connected to the input terminal of the Inv1. The output terminal of the Inv1 is connected to the input terminal of the D1 and the second input terminal of the NAND gate. The output terminal of the D1 is connected to the input terminal of the Inv2. The output terminal of the Inv2 is connected to the first input terminal of the NAND gate. The output terminal of the NAND gate is used to output the control signal V7. As Figure 5 shown, the first monitoring result V4 is filtered by the filtering module 150 to obtain the filtered first monitoring result V5. After the delay processing of the D1, the second monitoring result V6 is obtained. After the V6 and V5 are processed by the CT1, the control signal V7 is obtained.

[0088] In Figure 5 it, PM5, PM6, PM7 and NM3, NM4, NM5, NM6 are switching transistors. When a low level is applied to their gates, the NM3, NM4, NM5, and NM6 switches are not turned on, and the PM5, PM6, and PM7 are turned on. NM3, NM4, PM5, and PM6 are used to control the charge and discharge module 110. Specifically, NM3 and PM5 are used to control Figure 5NM1, C1, and PM1 therein, NM4 and PM6 are used to control Figure 5 NM2, C2, and PM2 therein. NM5, NM6, and PM7 are used to control the output module 120. Specifically, they are used to control Figure 5 PM3, PM4, PM8, PM9, and NM7 therein.

[0089] By applying high and low levels to the control terminal (gate) of the switching transistor, the on and off states of the switching transistor can be controlled, thereby controlling the circuit branch it is connected to. When the switching transistor is not conducting, it can disconnect the branch it is in, thus preventing the branch from forming a current loop and generating leakage current. When the switching transistor is conducting, it can connect the branch it is in, especially connect the circuit to the positive power supply and / or the negative power supply, so that the branch where the switching transistor is located has a sufficiently high operating voltage.

[0090] The conduction of PM5 and PM6 ensures the prevention of false alarm spikes that may be triggered during startup due to the slow startup speed of the clock and the long time for V1 / V2 to charge from the initial low level to the high level. The disconnection of NM3 and NM4 causes the current to flow to C1 instead of NM1 during the charging process.

[0091] The conduction of PM7 ensures that PM8 and PM9 are not conducting, then V3 is initially set to a low potential. The location of V3 can correspond to a normal clock signal. During normal operation, a high level is applied to the gate of PM7.

[0092] When NM3, NM4, NM5, and NM6 are conducting and PM5, PM6, and PM7 are not conducting, Figure 5 the circuit shown can be equivalent to Figure 6 shown. Figure 6 It is Figure 5 a schematic diagram of the equivalent circuit of the charge and discharge module 110 and the output module 120 in the circuit shown. The conduction of NM3, NM4, NM5, and NM6 and the non - conduction of PM5, PM6, and PM7 have been equivalent in Figure 6 already. Figure 6 The equivalent circuit shown is the equivalent circuit when the clock signal is normal.

[0093] When the clock oscillator oscillates, it will be an alternating high and low potential signal with a high level in one half-cycle and a low level in the other half-cycle. By using this alternating high and low level that each occupies half a cycle to control a MOS transistor, the PMOS will conduct in the half-cycle when the clock is at a low level; and turn off in the half-cycle when the clock is at a high level. The NMOS is the same as the PMOS. The NMOS conducts at a high level and turns off at a low level. The phases are opposite, but the principle is the same. In this application, the PMOS is taken as an example for introduction. Based on this basic principle, a clock signal is used to control a PMOS transistor (such as PM1) to charge a capacitor (such as C1). Then, during the process of clock oscillation, the PMOS transistor will be in the conducting state for half of the cycle. Then the capacitor voltage (such as V1) will gradually be charged up to the power supply voltage. Assuming that the clock is abnormal and the phase of the clock (such as CLK) controlling the gate of the PMOS transistor stops at a high level (here it is assumed to stop at a high level to explain the principle), then the PMOS transistor is in the off state and no longer charges the capacitor. At this time, a leakage (discharging) circuit is added to the capacitor, such as Figure 5 The series inverse ratio transistors NM1, NM2, and NM7 shown are all components used for discharging. The discharge current of the series inverse ratio transistor is very small (how small the specific current is determines the alarm delay after the clock stops oscillating, which can be adjusted according to system requirements). Then, after the clock stops oscillating, the PMOS turns off, and the voltage charged on the capacitor will gradually become low due to the leakage of the series inverse ratio transistor. In addition, since the design ensures that the discharge current of the series inverse ratio transistor is of an order of magnitude smaller than the charging current of the PMOS transistor, when the clock is working normally, even if the PMOS conducts only for half of the cycle, the pull-up ability of the PMOS is much greater than the discharge ability of the series inverse ratio transistor, and the node voltage (such as V1) on the capacitor will also be pulled up to the power supply voltage.

[0094] At this time, the node voltage can output a high and low level (such as the first voltage signal and the second voltage signal in this application) that changes according to whether the clock is normal or not. By further processing this voltage signal (such as the processing of the first voltage signal and the second voltage signal by the output module 120 in this application), the monitoring result of whether the clock signal is abnormal (such as the first monitoring result) can be obtained.

[0095] In Figure 5When the clock oscillates normally, CLK / CLKB are high and low level periodic signals with opposite phases and a duty cycle of 50%. PM1 and PM2 are turned on during the half cycle when CLK and CLKB are at low levels respectively, and charge capacitors C1 and C2 respectively. Then the voltages V1 / V2 on the upper plates of C1 and C2 will both be pulled up to the high level equal to the power supply voltage when the clock is working normally (the pulling-up capabilities of PM1 and PM2 are much greater than the discharging capabilities of the series inverse ratio transistors NM1 and NM2). Continue to use V1 and V2 to control PM3 and PM4 respectively. At this time, since both V1 and V2 are at the high level equal to the power supply voltage, PM3 and PM4 are both in the non-conducting cut-off state. Then V3 is pulled to the high level by the connection of PM8, and PM9 is also in the non-conducting cut-off state. NM7 is a series inverse ratio transistor with its gate connected to a bias voltage (the specific bias voltage of the gate can be provided externally or directly connected to the power supply). When NM7 is conducting, it will pull V4 down to the low level. V4 passes through the Schmitt trigger Schmitter and the inverter Inv1 to output V5. The Schmitt trigger can prevent the intermediate level from being output by V4 and filter out potential glitches generated due to the jitter of V4. Both V4 and V5 can be used as monitoring results. The low level 0 indicates that the clock is normal, and the high level 1 indicates that the clock is abnormal.

[0096] In Figure 5 When the clock is abnormal, CLK and CLKB will randomly stop at a high level and a low level (because CLK and CLKB are two signals with opposite phases of the same-source clock). Assume that CLK is at the high level 1 and CLKB is at the low level 0 (similarly for the reverse case). Then PM1 controlled by CLK will be in the cut-off state. Since the diode connection of NM1 will slowly discharge the charge on capacitor C1, V1 will slowly drop to the low potential 0; PM2 controlled by CLKB remains conducting. Since the pulling-up capability of PM2 is guaranteed to be much greater than the discharging capability of NM2 by design, V2 will be maintained at the high level 1. At this time, V1 is at the low level 0 and V2 is at the high level 1. PM3 is in the conducting state and PM4 is cut off. However, due to the parallel relationship between PM3 and PM4, PM8 will form a path of power supply - PM8 - PM3 - NM5 - ground through the conduction of PM3. After the diode connection of PM8 conducts, the voltage V3 will be lower than the power supply voltage to form a self-bias voltage V3, and then PM9 will also conduct. PM9 and PM8 form a current mirror relationship. The design ensures that the mirror current formed by PM9 at this time is much greater than the leakage / discharging current of NM7. Then PM9 will pull V4 up to the high level. V4 passes through the Schmitt trigger Schmitter and the inverter Inv1 to output V5, and V5 is at the high level.

[0097] V6 is generated after V5 is delayed by D1. The specific delay time of D1 determines the pulse width time of the clock reset, and the parameters can be determined according to the system requirements. Through the digital logic within the block CT1, a low-level pulse signal V7 with a certain pulse width is generated.

[0098] Figure 7 It is a schematic diagram of the clock change of the logic operation of the control module in the embodiment of the present application. As Figure 7 shown, V7 is 0 only during the period when both V5 and V6 are high level 1. V7 can be used as a control signal to control the clock signal generating device to work according to the control signal. For example, V7 can be logically combined with the total control signal of the generating device (a simple "AND" is sufficient, and the specific design logic and timing are designed according to the system requirements if there are other system requirements), to reset or restart the generating device.

[0099] The above circuit can be applied to, for example, chips, integrated circuits, or electronic devices, that is, any chip, circuit, or device with a clock signal.

[0100] The present application also provides a chip, which may include any one of the above monitoring circuits. This monitoring circuit can effectively monitor whether the clock signal of the chip's clock oscillator is abnormal, thereby monitoring whether the chip can work properly.

[0101] The present application also provides an electronic device, which may include an oscillator and any one of the above monitoring circuits. The oscillator is the clock signal generating device, and the monitoring circuit is used to monitor the oscillator. This electronic device can effectively monitor whether the oscillator is normal.

[0102] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0103] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0104] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A monitoring circuit for a clock signal, characterized in that, The clock signal includes a first clock signal and a second clock signal, and the phases of the first clock signal and the second clock signal are opposite to each other; the monitoring circuit includes: A first charge and discharge unit, which includes a first series inverse ratio transistor, a first capacitor, and a first MOS transistor. The control end of the first MOS transistor is the input end of the first charge and discharge unit; the first end of the first MOS transistor is connected to the positive power supply; the second end of the first MOS transistor is respectively connected to the second end of the first series inverse ratio transistor, the control end of the first series inverse ratio transistor, and the first end of the first capacitor, serving as the output end of the first charge and discharge unit for outputting a first voltage signal; the first end of the first series inverse ratio transistor is respectively connected to the negative power supply and the second end of the first capacitor; the first capacitor is used to store electrical energy according to the first clock signal; the first series inverse ratio transistor is used to discharge the electrical energy stored in the first capacitor according to the first clock signal; A second charge and discharge unit, which includes a second series inverse ratio transistor, a second capacitor, and a second MOS transistor; the first end of the first series inverse ratio transistor is respectively connected to the negative power supply and the second end of the first capacitor; the first capacitor is used to store electrical energy according to the first clock signal; the first series inverse ratio transistor is used to discharge the electrical energy stored in the first capacitor according to the first clock signal; the control end of the second MOS transistor is the input end of the second charge and discharge unit; the first end of the second MOS transistor is connected to the positive power supply; the second end of the second MOS transistor is respectively connected to the second end of the second series inverse ratio transistor, the control end of the second series inverse ratio transistor, and the first end of the second capacitor, serving as the output end of the second charge and discharge unit for outputting a second voltage signal; the first end of the second series inverse ratio transistor is respectively connected to the negative power supply and the second end of the second capacitor; the second capacitor is used to store electrical energy according to the second clock signal; the second series inverse ratio transistor is used to discharge the electrical energy stored in the second capacitor according to the second clock signal; An output module, which is used to generate a first monitoring result according to the first voltage signal and the second voltage signal.

2. The monitoring circuit according to claim 1, wherein The output module includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, and a third series inverse ratio transistor; The control end of the seventh MOS transistor is connected to the output end of the first charge and discharge unit for receiving the first voltage signal; the first end of the seventh MOS transistor is respectively connected to the first end of the eighth MOS transistor, the second end of the ninth MOS transistor, the control end of the ninth MOS transistor, and the control end of the tenth MOS transistor; the second end of the seventh MOS transistor is connected to the negative power supply; The control end of the eighth MOS transistor is connected to the output end of the second charge and discharge unit for receiving the second voltage signal; the second end of the eighth MOS transistor is connected to the negative power supply; The first ends of the ninth MOS transistor and the tenth MOS transistor are both connected to the positive power supply; The second terminal of the tenth MOS transistor is connected to the second terminal of the third series inverse ratio transistor, which is the output terminal of the output module for outputting the first monitoring result; The first terminal of the third series inverse ratio transistor is connected to the negative power supply.

3. The monitoring circuit according to claim 1, characterized in that The monitoring circuit further includes: A first switch unit, connected to the first charge-discharge unit and the second charge-discharge unit, for controlling the working states of the first charge-discharge unit and the second charge-discharge unit; A second switch unit, connected to the output module, for controlling the voltage value of the first monitoring result.

4. The monitoring circuit according to claim 1, characterized in that When both the first voltage signal and the second voltage signal are at high level, the first monitoring result indicates that the clock is normal; when at least one of the first voltage signal and the second voltage signal is at low level, the first monitoring result indicates that the clock is abnormal.

5. The monitoring circuit according to claim 1, characterized in that, The monitoring circuit further includes: A control module, connected to the output module, for receiving the first monitoring result and generating a control signal according to the first monitoring result, where the control signal is used to control the clock signal generating device to operate according to the control signal.

6. The monitoring circuit according to claim 5, wherein The control module includes: A delay unit, connected to the output terminal of the output module, for receiving the first monitoring result and performing a delay process on the first monitoring result to obtain a second monitoring result; A logic operation unit, respectively connected to the output terminal of the output module and the output terminal of the delay unit, for receiving the first monitoring result and the second monitoring result and performing a logic operation on the first monitoring result and the second monitoring result to obtain the control signal.

7. The monitoring circuit according to claim 6, wherein The control signal includes a reset signal and / or a restart signal; the first monitoring result includes that the clock signal is normal and that the clock signal is abnormal; The reset signal is used for the control module to control the clock signal generating device to reset when the clock signal is abnormal; The restart signal is used for the control module to control the clock signal generating device to restart when the clock signal is abnormal.

8. The monitoring circuit according to any one of claims 5-7, characterized in that The monitoring circuit further includes: A filtering module, for receiving the first monitoring result, filtering the first monitoring result to obtain a filtered first monitoring result, and sending the filtered first monitoring result to the control module; The input terminal of the filtering module is connected to the output terminal of the output module; the output terminal of the filtering module is connected to the input terminal of the control module.

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