Method and system for improving optical near correction technology

Abstract

Embodiments of the present invention relate to methods and systems for improving optical proximity correction techniques. A method and system for improving a layout are disclosed. A method includes receiving a design layout; determining a first subset of photoresist correction items of a first optical model and a photoresist model; performing model-based optical proximity correction (MOPC) according to the first subset of the first optical model and the photoresist model and updating the design layout to obtain a first updated design layout; determining a second subset of photoresist correction items of a second optical model and the photoresist model; performing MOPC according to the second subset of the second optical model and the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask according to the second updated layout.

Description

Technical Field

[0001] The present invention relates to a method and system for improving optical near-end correction technology. Background Technology

[0002] In advanced semiconductor technology, the ever-shrinking device size and increasingly complex circuit layouts make the design and fabrication of integrated circuits (ICs) more challenging and costly. Before circuits are delivered for mass production, it is essential to verify that the circuit design meets design specifications and manufacturing guidelines to improve manufacturing yield. To detect design errors or defects as early as possible, circuit designers utilize widely used computer-aided circuit design tools to help identify potential design flaws. However, with the increasing complexity and device density of circuits, the time and computational resources consumed by the software processes involved in circuit design and verification are becoming increasingly enormous. Therefore, there is a need to improve the circuit design flow to reduce design time while maintaining the quality of the circuit design. Summary of the Invention

[0003] This document discloses an embodiment of a method for improving a layout, comprising: receiving a design layout; determining a first subset of photoresist correction items for a first optical model and a photoresist model; performing model-based optical near-end correction (MOPC) based on the first optical model and the first subset of the photoresist model and updating the design layout to obtain a first updated design layout; determining a second subset of photoresist correction items for a second optical model and the photoresist model; performing MOPC based on the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask based on the second updated layout.

[0004] This document discloses a method for improving a layout, comprising: receiving a design layout; determining an initial subset of photoresist correction items as a new subset; determining a photoresist model based on the new subset; determining an optical model; performing model-based optical near-end correction (MOPC) based on the optical model and the photoresist model and updating the design layout to a second updated layout; determining whether the second design layout conforms to design specifications; and, in response to the second design layout not conforming to design specifications, performing the following steps: updating the new subset by maintaining the original photoresist correction items or incorporating more photoresist correction items; and performing MOPC on the second design layout based on the updated subset and updating the second design layout to obtain a third design layout.

[0005] Embodiments of this document disclose a design layout system comprising one or more processors and one or more programs storing instructions that, when executed by the one or more processors, cause the system to perform the following steps: receiving a design layout; determining a first subset of photoresist correction items for a first optical model and a photoresist model; performing model-based optical near-end correction (MOPC) based on the first optical model and the first subset of the photoresist model and updating the design layout to obtain a first updated design layout; determining a second subset of photoresist correction items for a second optical model and the photoresist model; performing MOPC based on the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask based on the second updated layout.

[0006] Various objects, features, aspects and advantages of the embodiments of the present invention will become more apparent from the detailed description of the preferred embodiments of the invention, together with the accompanying drawings, in which the same reference numerals represent similar components. Attached Figure Description

[0007] From the following detailed description, together with the accompanying drawings, aspects of the embodiments of the present invention will become more apparent. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 This is a schematic diagram of an integrated circuit (IC) manufacturing system according to some embodiments.

[0009] Figure 2 This is a schematic diagram of a subsystem fabricated according to a photomask layout of some embodiments.

[0010] Figures 3A to 3C This is a schematic diagram of the design layout according to an embodiment of the present invention.

[0011] Figure 4 This is a schematic diagram of a model optical near-end correction module according to an embodiment of the present invention.

[0012] Figure 5A and 5B This is a schematic diagram of an optical model based on some embodiments.

[0013] Figure 6 This is a flowchart of a method for training a photoresist model based on some embodiments.

[0014] Figure 7 This is a schematic diagram illustrating the iterative complexity of optical near-end correction methods according to some embodiments.

[0015] Figure 8This is a flowchart of an optical near-end correction method according to some embodiments.

[0016] Figure 9 This is a flowchart of an optical near-end correction method according to some embodiments.

[0017] Figure 10 This is a schematic diagram of a system for implementing an optical near-end correction method according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify the embodiments of the invention, specific examples of components and arrangements are described below. Of course, these are merely examples and are not limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments where the first and second features are formed in direct contact, and also includes embodiments where an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples of the embodiments of the invention. This repetition is for the purpose of simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or arrangements described.

[0019] Furthermore, the spatial relative terms used in this specification, such as "below," "below," "lower than," "above," and "above," are for ease of description regarding the relationship of one element or feature to another as shown in the figures. The spatial relative terms are intended to cover different orientations of the device in use or operation other than those described in the figures. The device may be in other orientations (rotated 90 degrees or other angular orientations), and the spatial relative terms used in this specification shall therefore be interpreted in the same manner.

[0020] While the numerical ranges and parameters described in the embodiments of the invention are approximate, the values ​​presented in specific examples are offered as precisely as possible. However, any numerical value inherently includes some error due to deviations that are typically found in various test measurements. Also, as used herein, the terms “about,” “approximately,” and “generally” generally mean within 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, when considered by one of ordinary skill in the art, the terms “about,” “approximately,” and “generally” mean within an acceptable standard error of the average. Except in operational / working examples, or unless expressly stated otherwise, all numerical ranges, quantities, values, and percentages (e.g., material quantity, duration, temperature, operating conditions, quantity ratios, etc.) disclosed herein should in any case be understood to be modified by the terms “about,” “approximately,” or “generally.” Therefore, unless taught to the contrary, the numerical parameters set forth in the embodiments of the invention and the appended claims are approximate values ​​that may vary as needed. At a minimum, each numerical parameter should be interpreted based on the number of significant figures presented and by applying ordinary rounding techniques. The scope in this specification may be expressed as from one endpoint to another or between the two endpoints. Unless otherwise stated, all scopes disclosed in this specification include the endpoints.

[0021] The terms "layout," "design layout," and "photomask layout" used in this article refer to the geometric pattern of an integrated circuit (IC) corresponding to the components of the IC, such as the metal layers, dielectric layers, or semiconductor layers that make up the IC assembly. In some instances, these terms also include related data files that can be converted into machine-readable code or text strings that can be translated into geometric patterns. Furthermore, design layout files may contain additional information (such as IC-related parameters converted from the geometric patterns) to improve IC design and manufacturing processes.

[0022] In this article, the terms "optical lithography" and "lithography" refer to the process of transferring circuit-related geometric patterns from a photomask onto a substrate. The geometric patterns on the photomask are defined by its design layout. Optical lithography, or lithography, typically uses light of a specific wavelength as a light source, which, after being adjusted and transmitted by an optical system, illuminates the photomask. The photomask can be transmissive or reflective, depending on the nature of the incident light source. In some cases, due to the interaction between the light source (along with the optical system) and the substrate (or its photoresist), errors occur between the geometric patterns transferred onto the substrate and the ideal pattern on the photomask layout, thus reducing the performance of the manufactured semiconductor device. Therefore, lithography improvement engineering is usually required to modify the geometric patterns on the photomask to ensure that the final geometric patterns transferred onto the substrate meet the design specifications in terms of error value compared to the original photomask design layout.

[0023] Furthermore, for photolithography using extreme ultraviolet (EUV) light as the light source (EUV lithography, EUVL), the process of improving the lithography can be more complex because the various optical effects caused by EUVL (such as diffraction and interference) have a more significant impact on lithographic performance than with other longer wavelength light sources. When considering improvements to EUVL lithography, it is also necessary to keep costs and time within acceptable limits.

[0024] This paper proposes a simplified improvement process for existing photolithography techniques. Improvements to existing photolithography techniques include optical proximity correction (OPC), which iteratively corrects the photomask layout pattern so that the pattern transferred onto the substrate by the updated photomask layout gradually approximates the original ideal pattern. Currently, during the iteration process of OPC, the parameter complexity of the optical model and photoresist model used in each round is fixed at the highest level to meet the correction requirements of the most complex polygons in the layout pattern. The improvement method proposed in this paper uses different combinations of parameter complexities for the optical model or photoresist model in different iterations of OPC. For example, in the initial OPC iterations, a less complex optical model or photoresist model can be used to achieve preliminary correction. In the final OPC iterations, the most complete optical model or photoresist model can be reverted to for correction. The aforementioned OPC improvement method, employing different model complexities in different rounds, allows for two main advantages. Firstly, simpler models in the initial OPC rounds can be used to correct simpler layouts, resulting in lower computational costs and minimal reduction in correction accuracy. Secondly, more complex models can be used in the final OPC rounds to correct more complex layouts, ensuring that the accuracy of corrections for complex patterns is not sacrificed. This approach reduces overall computational costs while still achieving the desired layout improvement, thus accelerating overall design and manufacturing efficiency.

[0025] Figure 1 This is a schematic diagram illustrating an IC manufacturing system 100 according to some embodiments. The IC manufacturing system 100 is configured to manufacture integrated circuit (IC) devices (hereinafter referred to as IC devices) 160 by multiple units, such as a design company 120, a photomask factory 130, and an IC manufacturer (wafer fab or foundry) 150. The different units in the IC manufacturing system 100 can be connected via communication channels (e.g., wired or wireless channels) and interact with each other via a network (e.g., an intranet or the Internet). In one embodiment, the design company 120, the photomask factory 130, and the IC manufacturer 150 may belong to the same unit or operate independently.

[0026] Design company (or design team) 120 is responsible for generating design layout 122 during the IC design phase for manufacturing IC device 160. Design layout 122 includes various geometric patterns that perform predetermined performance of the IC device and comply with manufacturing constraints. The geometric patterns in design layout 122 represent circuit components of various IC components in the manufactured IC device 160, such as metal layers, dielectric layers, or semiconductor layers, to form, for example, active regions, gate electrodes, source and drain electrodes, and metal lines, vias, or insulating layers in interlayer interconnects. In one embodiment, design company 120 performs a circuit design process to generate design layout 122. The circuit design process may include, but is not limited to, logic design, physical circuit design, pre-layout simulation, wire routing, timing analysis, parameter extraction, design rule checking, and post-layout simulation. Design layout 122 can be converted from a text-based document into a visual graphic to fully display the physical layout to be represented, such as the size, shape, and position of the depicted patterns. In one embodiment, design layout 122 can be represented in GDSII, DFII, or OASIS file format.

[0027] Photomask factory 130 receives design layout 122 from design company 120 and manufactures one or more photomasks according to design layout 122. In one embodiment, photomask factory 130 includes a photomask layout preparation subsystem 132, a photomask fabrication subsystem 144, and a photomask inspection subsystem 146. Photomask layout preparation subsystem 132 modifies design layout 122 so that the updated design layout 134 can be easily rewritten by a photomask writer as needed. When photomask fabrication is complete, the photomask can be used to repeatedly transfer patterns from the photomask to different cells in a semiconductor wafer. In each exposure process, the photomask projects a patterned light source onto an exposure area of ​​a predetermined size for pattern transfer. Additionally, cleavage regions may exist between different cells of the semiconductor wafer, and test structures can be formed within the space of these cleavage regions.

[0028] A photomask fabrication subsystem 144 is configured to process a photomask substrate according to a design layout 134 to form a photomask. In an optical lithography process, a photolithography light source projects patterned light onto a photoresist after being projected onto the pattern of the design layout 134, followed by etching to leave a pattern identical to the design layout on the photomask substrate. In one embodiment, the photomask fabrication subsystem 144 incorporates an inspection process to ensure that the layout pattern meets the requirements of the photomask writer or photomask manufacturer and that the layout pattern can be used to generate a photomask as needed. The layout pattern transfer process during photomask fabrication can be performed using an electron beam (e-beam) device. Furthermore, various other techniques can be used to fabricate photomasks. In one embodiment, a binary technique is used to fabricate the photomask, wherein the binary photomask comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the photomask. In another example, a phase-shifting technique (e.g., a phase-shifted photomask (PSM)) is used to fabricate the photomask.

[0029] After the photomask is fabricated, the photomask inspection subsystem 146 inspects the fabricated photomask to determine if there are any defects in the fabricated photomask, such as full-height and non-full-height defects. If any defects are detected, then the photomask is considered for abandonment or modification of the design layout in the photomask.

[0030] IC manufacturer 150 manufactures various IC products and may include multiple manufacturing facilities. IC manufacturer 150 uses photomasks fabricated by photomask factory 130 to fabricate semiconductor wafers 152, wherein semiconductor wafers 152 contain multiple IC devices 160. Semiconductor wafers 152 may be silicon substrates or other suitable substrates, and various layers may be present on semiconductor wafers 152 to form various photomask patterns. In one embodiment, IC manufacturer 150 includes a wafer testing subsystem 154 configured to test semiconductor wafers 152 such that IC devices 160 meet physical manufacturing specifications and mechanical and / or electrical performance specifications. In some embodiments, test structures formed on semiconductor wafers 152 may be used to generate test data as quality indicators. After semiconductor wafers 152 pass through the testing process performed by wafer testing subsystem 154, semiconductor wafers 152 may be diced along dicing lines to form individual IC devices 160. The dicing process may be accomplished by cutting and monolithization, and may be performed by means of a mechanical saw or laser cutting.

[0031] Figure 2 According to some embodiments Figure 1A schematic diagram of the photomask layout fabrication subsystem 132 in the IC manufacturing system 100. The photomask layout fabrication subsystem 132 includes a rule-based optical near-end correction (ROPC) module (hereinafter referred to as ROPC module) 210, a boundary dissection (BD) module 220, a model-based OPC (MOPC) module (hereinafter referred to as MOPC module) 230, and a lithography process check (LPC) module (hereinafter referred to as LPC module) 240.

[0032] ROPC module 210 is configured to examine design layout 122 in order to modify it according to predetermined photomask manufacturing rules. ROPC module 210 receives a rule table consisting of manufacturing specifications from various manufacturers to examine design layout 122. If design layout 122 does not conform to the rule table of ROPC module 210, then ROPC module 210 will modify design layout 122 accordingly until the modified design layout 122 conforms to the rules. The rule table may contain design specifications for the geometry of patterns in design layout 122, such as minimum pattern length, minimum spacing, maximum number, etc.

[0033] Figure 3A This is a schematic diagram of the design layout 300A according to an embodiment of the present invention. (Refer to...) Figure 2 as well as Figure 3A Design layout 300A may be a part of design layout 122, which includes an exemplary pattern 302, wherein pattern 302 may be a pattern that has been checked and corrected by ROPC module 210 and thus conforms to the design specifications in the rule table of ROPC module 210.

[0034] Rereference Figure 2 The design layout 122 is edge-segmented via BD module 220. (Refer to...) Figure 2 as well as Figure 3BIn pattern 300B, the edge 302B used to define pattern 302 is divided into multiple edge segments 302S, such as edge segments 302S from label (1) to label (5). The segmented design layout then becomes the updated design layout 202. Each edge segment 302S of pattern 302 is the smallest unit for the photolithography correction step. Each edge segment 302S can be individually corrected in the photolithography improvement method so that the updated pattern 302 can obtain a better photolithography effect. The length of edge segment 302S can be adjusted as needed. The smaller the length of edge segment 302S, the more accurate the correction result of the updated pattern 302 obtained by the photolithography improvement method can be. However, it may also lead to an increase in the total number of edge segments 302S of pattern 302, requiring more computational resources.

[0035] In one embodiment, the BD module 220 classifies each edge segment 302S while performing edge segmentation on the design layout 300A. In one embodiment, the classification of edge segments 302S is determined based on their complexity, classifying them as one-dimensional or two-dimensional graphics. For example, edge segments 302S numbered (1) and (2) are classified as one-dimensional graphics because they are straight lines with low complexity and do not approach the corners or ends of pattern 302. Edge segments 302S numbered (3), (4), and (5) are classified as two-dimensional graphics because they are close to the corners or ends of pattern 302 and have higher complexity. The above classification method is only an example. The BD module 220 can also classify edge segments based on other features. For example, edge segments 302S classified as one-dimensional graphics can be further classified as sparse one-dimensional graphics and dense one-dimensional graphics based on the distance between pattern 302 and other neighboring patterns. Furthermore, the edge segment 302S in the two-dimensional graphic can be further classified into sparse two-dimensional graphics and dense two-dimensional graphics based on the distance between pattern 302 and other neighboring patterns or the width of pattern 302 in the edge segment 302S.

[0036] In another embodiment, the edge segments 302S can be classified according to the pattern 302 itself or the critical dimension (CD) of the pattern 302 in the edge segments 302S. Since the optical model and photoresist model of the OPC produce different correction effects for patterns with different critical dimensions, classifying the edge segments 302S corresponding to the critical dimensions of the design layout 300B will help simplify the OPC correction process and improve correction performance. In one embodiment, the edge segments 302S can be classified into different categories such as small size, medium size, and large size. In one embodiment, the BD module 220 can perform multiple classifications of the edge segments 302S, for example, simultaneously performing more detailed classifications based on one-dimensional / two-dimensional graphic characteristics and critical dimensions.

[0037] After edge segmentation and classification, the lithography improvement method presented herein uses a MOPC module 230 to perform model-based optical near-end correction (MOPC) on the designed layout 300B. In some embodiments, the MOPC module 230 is used to apply a predetermined optical model and photoresist model, and simulate the optical path of the lithography light source and various optical effects to design the layout pattern (e.g., ...). Figure 3A The simulated pattern image is obtained by exposing the light intensity distribution values ​​of the pattern 302 to the semiconductor substrate. In one embodiment, the MOPC module 230 can collect the imaging error between the simulated pattern image and the ideal pattern, such as due to optical diffraction, interference or other effects, or effects related to the photoresist composition or process effects.

[0038] In some embodiments, the MOPC module 230 incorporates glare or slit effects caused by defects in the optical elements of the lithography system into its correction considerations. In one embodiment, glare typically refers to the combined effect of stray light incident on the photomask caused by non-ideal reflection or scattering from optical elements. In one embodiment, the slit effect is used to simulate the effect of an arc-shaped exposure slit, where the azimuth of incident light passing through the slit is unevenly distributed from the center to the end of the slit. Variations in the azimuth can lead to inhomogeneities in the intensity, phase, and polarization of the light passing through the slit, thus causing imaging errors.

[0039] In one embodiment, the MOPC module 230 may further compensate for the collected imaging error data using photolithographic improvement techniques, i.e., perform optical near-end correction. In one embodiment, improvement features or patterns (e.g., scattering stripes, serifs, and / or hammers) are added to or removed from the design layout 122 according to the established optical model or rules. For example, the MOPC module 230 may perform correction in any of the following ways: redefine the boundaries of the original pattern; attach a sub-resolution auxiliary feature to the original pattern; or add a scattering stripe to the original design layout.

[0040] In one embodiment, the above-described process of simulating the exposure intensity distribution of the design layout pattern and correcting the pattern 302 of the design layout 300B can be performed on the pattern 302 as a whole or on each edge segment 302S individually. Figure 3CThis is a schematic diagram of a design layout 300C according to an embodiment of the present invention. Design layout 300C includes a pattern 304, which represents an updated pattern generated after the correction process of pattern 302 by the MOPC module 230. The edges 304B of pattern 304 are indicated by dashed lines, wherein a portion of edge segments 304S of edge 304B overlaps with the original edge 302S, indicating that these edge segments do not need to be repositioned after the correction process by the MOPC module 230. On the other hand, another portion of edge segments 304S of edge 304B is separated from the original edge 302S by a distance, indicating that these edge segments need to be translated after the correction process by the MOPC module 230 to obtain a better photolithography effect.

[0041] In one embodiment, the edge segments 304S of the pattern 304 in the above-described design layout 300C need to be obtained through multiple iterations. In each iteration, it is calculated whether translation is required or not, and the translation distance. After multiple rounds of correction and convergence, each edge segment 304S will converge to the ideal position.

[0042] Rereference Figure 2 The LPC module 240 is used to simulate the manufacturing process implemented by the IC manufacturer 150, and the simulated scope may cover all or part of the design layout (e.g., layout 202). In this embodiment, the LPC module 240 simulates the design layout 300C obtained after the design layout 202 has been improved by the MOPC module 230. In some embodiments, the LPC module 240 is configured to examine the final design layout 300C to determine if there are any problematic areas (also referred to as "hot spots"). The term "hot spot" can be used to represent an area or feature in the IC device 160 that negatively affects performance. Hot spots may be caused by improper circuit design and / or process control, and the symptoms exhibited by hot spots include feature compression / necking, bridging (short circuit), dents, corrosion, RC delay, line thickness variation, etch residue, and other possible aspects.

[0043] Once the final design layout 300C passes the inspection of the LPC module, design layout 134 is generated, which, as mentioned above, can be used by the photomask fabrication subsystem 144 to manufacture photomasks.

[0044] Figure 4This is a schematic diagram of a Model-Based Optical Near-End Correction (MOPC) module 230 according to an embodiment of the present invention. The MOPC module 230 includes a fragment selection module 410, an optical model module 420, a photoresist model module 430, and a fragment correction module 440. In one embodiment, the MOPC module 230 can perform multiple iterations to correct the pattern in the design layout 202. The correction process consisting of the fragment selection module 410, the optical model module 420, the photoresist model module 430, and the fragment correction module 440 can be repeatedly modified to gradually converge the correction results. Furthermore, each component module of the MOPC module 230 can use different computational parameters for different iterations to save computation time and improve the correction effect; details will be described in the following paragraphs.

[0045] In one embodiment, the fragment selection module 410 receives the design layout 202 and selects the fragment category of the pattern edges. As mentioned earlier, the pattern edges in the design layout 202 are also classified after being segmented into edge fragments 302S by the BD module 220, for example, into different categories such as one-dimensional graphics and two-dimensional graphics. In one embodiment, the fragment selection module 410, based on the classification of the edge fragments 302S, will only select a portion of the pattern fragments of the design layout 202 (e.g., one-dimensional graphics) for correction in the first few rounds of correction by the MOPC module 230, while leaving the unselected portions (e.g., two-dimensional graphics) unprocessed. In one embodiment, in the later rounds of iteration by the MOPC module 230, the fragment selection module 410 selects the uncorrected portions of the pattern fragments of the design layout 202 (e.g., two-dimensional graphics) for correction. In another embodiment, in the later rounds of iteration by the MOPC module 230, the fragment selection module 410 corrects all pattern fragments of the design layout 202 regardless of their classification. The number of iterations in the aforementioned iterative MOPC can be determined according to requirements, and is not necessarily fixed.

[0046] In one embodiment, the design layout 202, after selecting edge segments 302S, enters the optical model module 420. The optical model module 420 provides a model of the optical projection path to simulate the exposure intensity distribution at each location on the design layout 202 under illumination by a light source. In one embodiment, the design layout 202 is set as an initial pattern without MOPC processing. This initial pattern is represented by a matrix H, which consists of matrix elements in P columns and Q rows, where P and Q are positive integers, and the (p,q)th element is represented as... Next, design the matrix elements of layout 202. Perform a binary classification. For example, matrix elements that overlap with the selected edge segment 302S. Set to "1", while other matrix elements that do not overlap with the selected edge segment 302S Set to "0".

[0047] In one embodiment, the optical model selected by the optical model module 420 is... The light intensity received by the initial pattern is obtained by performing interactive operations on matrix H. In one embodiment, for the matrix elements... A certain edge segment on the matrix can be used to extract matrix elements. A local area nearby is defined as the computation region, and matrix elements are processed within this computation region. With optical model Perform convolution to obtain the light intensity matrix received by the initial pattern. , as shown in the following formula.

[0048]

[0049] Among them, operands Represents convolution operation, function Representative optical model The i Each component function, weight value Representative composition function Weight value.

[0050] In one embodiment, the MOPC module 230 further includes an optical database 402 containing different optical models. Types and related parameters. Optical models. Different types can be selected from optical database 402 to obtain the light intensity matrix as needed. Different optical models The physical meanings of their parameters and the complexity of their models differ. For example, referencing... Figure 5A Optical model This can be a normal incidence (NI) model, which assumes that all light rays 504 incident on the target object 502 (e.g., photoresist) are perpendicularly incident on the surface of the target object 502. In another embodiment, refer to... Figure 5B Optical model This can be an off-axis illuminance (OAI) model, which assumes that the light ray 506 incident on the target object 502 (photoresist or photomask) can have different angles between it and the surface of the target object 502, such as perpendicular and oblique incidence. Generally speaking, the perpendicular incidence model has lower computational requirements and can be used for lithography improvement projects with lower graphic complexity; on the other hand, the off-axis illumination model can be used to simulate more complex (e.g., 2D graphics) lithography improvement projects, but it must also withstand higher computational requirements.

[0051] In one embodiment, the optical database 402 also includes three-dimensional distribution information of the surface topography of the photoresist, which can simulate the change in exposure intensity caused by the non-ideal plane of the photoresist surface when the photoresist material is exposed to the photolithography process.

[0052] In one embodiment, the initial pattern, after being processed by the optical model module 420, enters the photoresist model module 430 to simulate the photochemical reaction between the photoresist material and light, the baking process after photolithography, and the development process to predict the resulting photoresist pattern. In one embodiment, the MOPC module 230 includes a photoresist database 404, which contains correction items for photoresist or other photolithography materials, their models, and related parameters. For example, the photoresist correction items in the photoresist database 404 may include photoresist material, type of etching chemical, acid concentration distribution value, alkali concentration distribution value, photoacid diffusion, binary mask-related derived values ​​(e.g., density difference), curvature tangent vector, positive curvature vector, etc.

[0053] In one embodiment, the photoresist model selected by the photoresist model module 430 is... The light intensity matrix of optical model module 420 The light intensity matrix J of the photoresist pattern is obtained through calculation. In one embodiment, the intensity matrix J is calculated for the elements located in the matrix. The edge segments on the surface, within the aforementioned computational region, can be used to process the light intensity matrix. With photoresist model Perform convolution to obtain the light intensity matrix , as shown in the following formula.

[0054]

[0055] in Representative photoresist model No. i The function and weight values ​​for each photoresist correction item. Representative function The weights assigned, where N represents the photoresist model. The total number of constituent functions.

[0056] In one embodiment, to simulate a developing or etching process, the light intensity matrix is... In general, if the light intensity of an element is greater than the development threshold T, then the position represented by that element will leave a pattern after the development process. Conversely, if the light intensity of an element is less than the development threshold T, then the position represented by that element will be removed after the development process. This calculation yields the predicted photoresist pattern outline, expressed as a matrix. It is indicated that the element values ​​are represented as binary values, which can be obtained by the following formula.

[0057]

[0058] In one embodiment, the fragment correction module 440 compares the photoresist pattern contour K with... Figure 1 The design layout 122 is the pattern outline, and how to correct the edge segments 302S of the pattern in the design layout 122 or 202 is determined, thus obtaining Figure 3C The updated design layout 300C. In another embodiment, the fragment correction module 440 adjusts the light intensity matrix of the photoresist pattern. The difference from the development threshold T was compared. Figure 1 The design layout 122 is the pattern outline, and how to correct the edge segments 302S of the pattern in the design layout 202 is determined, thus determining how to correct the edge segments 302S of the pattern in the design layout 202 to obtain Figure 3C The updated design layout of 300C.

[0059] In one embodiment, before moving one or more edge segments 302S of the design layout 300C, the segment correction module 440 needs to calculate whether the previous round of movement has reached the optimal position. In other words, the segment selection module 410, the optical model module 420, the photoresist model module 430, and the segment correction module 440 need to perform multiple rounds of iterative calculations to make the final photoresist pattern contour K converge, i.e., the error value between the photoresist pattern contour K and the pattern contour of the design layout 122 is lower than the design specification. During each round of calculation, the segment correction module 440 may consider that some edge segments 302S have not yet converged and move them, while other edge segments 302S will not be moved if they have converged.

[0060] In one embodiment, during each round of calculation, each edge segment 302S, regardless of whether it needs to be moved again, still needs to undergo calculations by the optical model module 420 and the photoresist model module 430. This is because the optical model module 420 and the photoresist model module 430 calculate the predicted photoresist pattern contour. The computational resources consumed account for a significant proportion of the overall MOPC. Therefore, to mitigate the drawback of excessive computational demands in existing technologies, different optical models can be employed in different iterations. Or photoresist model Furthermore, by appropriately arranging the optical models in different rounds... Or photoresist model The complexity, i.e., the direction from low to high complexity, can have the advantage of saving computational load, while also maintaining the outline of the photoresist pattern. The correction effect remains unchanged.

[0061] In one embodiment, photoresist models of varying complexity The total number N of photoresist correction items used is different. It is worth noting that in the photoresist model... Each photoresist correction item function in The corresponding weight value This may be related to other photoresist correction function projects. And this changes. Therefore, when different photoresist correction items are determined, photoresist models of varying complexity are formed. At that time, its optimal weight value They also need to be retrained to achieve this. Figure 6 This is a flowchart of a photoresist model training method according to some embodiments. Figure 6 Additional steps may be provided before, during, and after the steps shown, and some steps described in method 600 may be removed or replaced by other steps in some embodiments. In some embodiments, the order of steps in method 600 may be changed.

[0062] In step 602, the photoresist model is received. First photoresist correction project function and the corresponding first weight value In one embodiment, a photoresist model It is the unsimplified photoresist model, while the first photoresist correction term function The total number is A. In step 604, the number of subset functions B is determined as the photoresist model. Second photoresist correction item function Total, of which .

[0063] In step 606, according to the first weight value Size selection B first photoresist correction item function As a model of photoresist Second photoresist correction item function The second photoresist correction item function It has a corresponding first weight value In one embodiment, the second photoresist correction item function It is the first photoresist correction project function A subset of B. In one embodiment, B maximum weight values ​​are selected. First photoresist correction project function As the second photoresist correction item function In one embodiment, B first photoresist correction term functions are selected based on the characteristics of the photomask process. As the second photoresist correction item function .

[0064] In step 608, determine whether to retrain the second photoresist correction item function. First weight value If it is determined that retraining is not required, then method 600 proceeds to step 610, based on the photoresist model. The second photoresist project function and the first weight value conduct Figure 4 MOPC (e.g., performing calculations in the photoresist model module 430).

[0065] If it is determined that the first weight value needs to be retrained Then, method 600 proceeds to step 612, where a photoresist model is trained using a known photomask pattern. Second photoresist correction item function And thus obtain the corresponding second weight value. It replaces the original first weight value In one embodiment, a second weight value is obtained by regression using a known photomask pattern. In one embodiment, the second weight value With the first weight value They are not the same. In one embodiment, a second photoresist project function is trained using a circuit pattern of a known semiconductor device. And thus obtain the second weight value. In step 614, according to the photoresist model... The second photoresist project function and the second weight value conduct Figure 4 MOPC (e.g., performing calculations in the photoresist model module 430).

[0066] The above photoresist model Since the number of functions A > B, the first photoresist correction term function is applied. The model complexity is greater than that of applying the second photoresist correction function. The model complexity is similar, yet all can be used in the photoresist model module 430 provided herein. In one embodiment, although the second photoresist correction term function is used... The calculations are performed using the photoresist model module 430, thus saving computational resources; however, if the second weight value is used... Because it has been optimized through retraining, its performance is better than using the first weight value. Second photoresist correction item function .

[0067] As mentioned earlier, the MOPC method proposed in this paper performs progressive design layout pattern correction in an iterative manner, and each iteration can select edge fragment sets and optical models of different complexities. Or photoresist model . Figure 7 This is a schematic diagram 700 illustrating the iterative complexity of the MOPC method according to some embodiments. Schematic diagram 700 shows 16 bars representing 16 iteration rounds (N=16) of the MOPC, ending at the 16th round (n=16). Each bar consists of three short bars, representing the set of edge segments, the optical model, etc., used in that iteration round. and photoresist model Different short bar patterns represent different levels of complexity. In one embodiment, the MOPC method proposed herein employs an unsimplified set of edge fragments, as well as an unsimplified optical model and photoresist model, at least once in the last round (n=16). In one embodiment, the sets or models employed by the fragment selection module 410, the optical model module 420, and / or the photoresist model module 430 have the same or lower complexity in the early rounds (i.e., when n is small) compared to the later rounds (i.e., when n is large).

[0068] For example, the fragment selection module 410 uses the first edge fragment set in iteration rounds n=1~5, the second edge fragment set in iteration rounds n=6~10, and the third edge fragment set in iteration rounds n=11~16. The first edge fragment set can be a small-sized one-dimensional graphic, the second edge fragment set can be a one-dimensional graphic of all sizes, and the third edge fragment set can be a graphic of all sizes (including one-dimensional and two-dimensional graphics).

[0069] In another embodiment, the optical model module 420 uses a first optical model during iteration rounds n=1~8, and a second optical model during iteration rounds n=8~16. The first optical model can be a perpendicular incidence model, while the second optical model can be an off-axis illumination model. In one embodiment, the complexity of the second optical model is greater than that of the first optical model.

[0070] In another embodiment, the photoresist model module 430 employs N1 photoresist correction item functions in iteration rounds n=1~4, N2 photoresist correction item functions in iteration rounds n=5~8, N3 photoresist correction item functions in iteration rounds n=9~12, and N4 photoresist correction item functions in iteration rounds n=13~16. In one embodiment, N4 represents the total number of all photoresist correction item functions in the photoresist model.

[0071] Figure 8 This is a flowchart of an optical near-end correction method 800 according to some embodiments. The method 800 provided herein, in... Figure 8 Additional steps may be provided before, during, and after the steps shown, and some steps described in method 800 may be removed or replaced by other steps in some embodiments. In some embodiments, the order of steps in method 800 may be changed.

[0072] In step 802, a design layout is received. In step 804, ROPC is performed on the design layout. In step 806, a first subset of photoresist correction items for the first optical model and the photoresist model is determined. In one embodiment, the first subset is the photoresist model in method 600. Second photoresist correction item function In step 808, the number of first iterations is determined. In step 810, based on the first optical model and the photoresist model... The first subset is subjected to the first number of MOPC iterations, and the design layout is updated to obtain the first updated design layout.

[0073] In step 812, a second subset of the photoresist correction items for the second optical model and the photoresist model is determined. In one embodiment, the second subset is the photoresist model in method 600. First photoresist correction project function In step 814, the number of second iterations is determined. In step 816, based on the second optical model and the photoresist model... The second subset is subjected to the second number of MOPC iterations, and the first design layout is updated to obtain a second updated design layout. In step 818, a photomask is fabricated according to the second updated layout. In step 820, a semiconductor device is fabricated according to the photomask.

[0074] Figure 9This is a flowchart of an optical near-end correction method 900 according to some embodiments. The method 900 provided herein, in… Figure 9 Additional steps may be provided before, during, and after the steps shown, and some steps described in method 900 may be removed or replaced by other steps in some embodiments. In some embodiments, the order of steps in method 900 may be changed.

[0075] In step 902, a design layout is received. In step 904, ROPC is performed on the design layout. In step 906, an initial subset of photoresist correction items in the photoresist model is determined as a new subset. In step 908, the photoresist model is determined based on the new subset. In one embodiment, weight values ​​corresponding to the initial subset of photoresist correction items in the photoresist model are received or determined based on the initial subset.

[0076] In step 910, an optical model is determined. In step 912, a model-based OPC is performed based on the optical model and the photoresist model, and the design layout is updated. In step 914, it is determined whether the updated design layout conforms to the design specifications. In one embodiment, conformity to the design specifications is determined by whether the error of the updated design layout is less than a default value.

[0077] If the updated design layout is determined to meet the design specifications in terms of error, then in step 916, a photomask is manufactured based on the updated layout. If the updated design layout is determined to not meet the design specifications in terms of error, then in step 918, a new subset is formed by maintaining the original photoresist correction items or incorporating more photoresist correction items, and method 900 returns to step 908 to continue until the updated design layout is determined to meet the design specifications in terms of error, or method 900 has reached the default number of iterations, at which point method 900 stops.

[0078] Figure 10 This is a schematic diagram of a system 1000 implementing an optical near-end correction method according to some embodiments. System 1000 includes a processor 1001, a network interface 1003, an input / output (I / O) device 1005, a storage device 1007, a memory 1009, and a bus 1008. The bus 1008 connects the network interface 1003, I / O device 1005, storage device 1007, memory 1009, and processor 1001 to each other.

[0079] The processor 1001 is configured to execute program instructions, including tool instructions, configured to perform methods as described and illustrated herein. Therefore, the tool is configured to perform steps such as providing design specifications, generating design layout data, performing OPC steps, performing LPC steps, extracting layout dependency parameters, performing model training, and correcting the design layout pattern.

[0080] Network interface 1003 is configured to access program instructions and data, wherein the data can be remotely stored via a network (not shown) and accessed by program instructions.

[0081] I / O device 1005 includes input and output devices configured to enable a user to interact with system 1000. In some embodiments, input devices include, for example, a keyboard, a mouse, and other devices. Output devices include, for example, a display, a printer, and other devices.

[0082] Storage device 1007 is configured to store program instructions and data accessed by the program instructions. In some embodiments, storage device 1007 includes non-transitory computer-readable storage media, such as magnetic disks and optical disks.

[0083] The memory 1009 is configured to store program instructions executed by the processor 1001 and data accessed by the program instructions. In some embodiments, the memory 1009 includes any combination of random access memory (RAM), other volatile storage devices, read-only memory (ROM), and other non-volatile storage devices.

[0084] This document discloses an embodiment of a method for improving a layout, comprising: receiving a design layout; determining a first subset of photoresist correction items for a first optical model and a photoresist model; performing model-based optical near-end correction (MOPC) based on the first optical model and the first subset of the photoresist model and updating the design layout to obtain a first updated design layout; determining a second subset of photoresist correction items for a second optical model and the photoresist model; performing MOPC based on the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask based on the second updated layout.

[0085] This document discloses a method for improving a layout, comprising: receiving a design layout; determining an initial subset of photoresist correction items as a new subset; determining a photoresist model based on the new subset; determining an optical model; performing model-based optical near-end correction (MOPC) based on the optical model and the photoresist model and updating the design layout to a second updated layout; determining whether the second design layout conforms to design specifications; and, in response to the second design layout not conforming to design specifications, performing the following steps: updating the new subset by maintaining the original photoresist correction items or incorporating more photoresist correction items; and performing MOPC on the second design layout based on the updated subset and updating the second design layout to obtain a third design layout.

[0086] Embodiments of this document disclose a design layout system comprising one or more processors and one or more programs storing instructions that, when executed by the one or more processors, cause the system to perform the following steps: receiving a design layout; determining a first subset of photoresist correction items for a first optical model and a photoresist model; performing model-based optical near-end correction (MOPC) based on the first optical model and the first subset of the photoresist model and updating the design layout to obtain a first updated design layout; determining a second subset of photoresist correction items for a second optical model and the photoresist model; performing MOPC based on the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask based on the second updated layout.

[0087] The foregoing description of several embodiments will enable those skilled in the art to better understand aspects of the embodiments of the present invention. Those skilled in the art should understand that they can directly use the embodiments of the present invention as the basis for designing or modifying other processes or structures to achieve the same purpose and / or the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent architectures do not depart from the spirit and scope of the embodiments of the present invention, and that various changes, substitutions, and alternatives can be made to these embodiments without departing from the spirit and scope of the embodiments of the present invention.

[0088] Symbol Explanation

[0089] 100 Integrated Circuit (IC) Manufacturing Systems

[0090] 120 Design Company

[0091] 122 Design Layout

[0092] 130 Photomask Factory

[0093] 132 Photomask Layout Fabrication Subsystem

[0094] 134 Design Layout

[0095] 144 Photomask Fabrication Subsystem

[0096] 146 Photomask Inspection Subsystem

[0097] 150 Integrated Circuit Manufacturers

[0098] 152 Semiconductor wafers

[0099] 154-chip testing subsystem

[0100] 160 Integrated Circuit (IC) Devices

[0101] 202 Design Layout

[0102] 210 Regular Optical Proximity Correction (ROPC) Module

[0103] 220 Edge Segmentation Module

[0104] 230 Model-based Optical Proximity Correction (MOPC) Module

[0105] 240 Lithography Process Inspection (LPC) Module

[0106] 302 pattern

[0107] 302S edge fragment

[0108] 402 Optical Database

[0109] 404 Photoresist Database

[0110] 410 Segment Selection Module

[0111] 420 Optical Model Module

[0112] 430 Photoresist Model Module

[0113] 440 Fragment Correction Module

[0114] 502 Target Object

[0115] 504 Light

[0116] 600 methods

[0117] Step 602

[0118] 604 Steps

[0119] 606 steps

[0120] 608 steps

[0121] Step 610

[0122] 612 steps

[0123] Step 614

[0124] Diagram of 700 iteration complexity

[0125] 800 methods

[0126] Step 802

[0127] 804 Steps

[0128] Step 806

[0129] 808 steps

[0130] Step 810

[0131] 812 steps

[0132] Step 814

[0133] Step 816

[0134] 818 steps

[0135] 820 steps

[0136] 900 methods

[0137] 902 Steps

[0138] 904 Steps

[0139] 906 steps

[0140] 908 steps

[0141] 910 steps

[0142] 912 steps

[0143] 914 Steps

[0144] 916 steps

[0145] 918 steps

[0146] 1001 processor

[0147] 1003 Network Interface

[0148] 1005 Input / Output (I / O) Devices

[0149] 1007 Storage Device

[0150] 1008 bus

[0151] 1009 Memory

[0152] n iterations.

Claims

1. A method for improving layout, comprising: Receive design layout; Determine the first optical model and determine the first subset of photoresist correction items for the photoresist model; Based on the first optical model and the first subset of the photoresist model, a model-based optical near-end correction (MOPC) is performed and the design layout is updated to obtain a first updated design layout. Determine a second optical model and determine a second subset of the photoresist correction items of the photoresist model, wherein the second optical model is different from the first optical model, or the second subset is different from the first subset; MOPC is performed based on the second optical model and the second subset of the photoresist model, and the first updated design layout is updated to obtain the second updated design layout; and The photomask is manufactured according to the second updated design layout.

2. The method of claim 1, further comprising manufacturing a semiconductor device according to the photomask.

3. The method according to claim 1, further comprising: Retraining the photoresist model to obtain the corresponding weight values ​​of the first subset, wherein performing MOPC based on the first optical model and the first subset of the photoresist model includes performing MOPC based on the corresponding weight values ​​of the first subset.

4. The method of claim 1, wherein the second subset comprises the first subset.

5. The method according to claim 1, wherein the first optical model is a vertical incident model and the second optical model is an off-axis illumination model.

6. The method according to claim 1, further comprising dividing the pattern edge of the design layout into a plurality of edge segments, and classifying the edge segments into at least a first set of edge segments and a second set of edge segments, wherein the step of performing MOPC on the design layout according to the first optical model and the first subset of the photoresist model includes performing MOPC only on the first set of edge segments, wherein performing MOPC according to the second optical model and the second subset of the photoresist model includes performing MOPC on both the first set of edge segments and the second set of edge segments.

7. The method of claim 6, wherein classifying the edge segments into at least a first set of edge segments and a second set of edge segments comprises classifying the one-dimensional and two-dimensional graphics in the edge segments into the first set of edge segments and the second set of edge segments, respectively.

8. A method for improving layout, comprising: Receive design layout; An initial subset of photoresist correction items in the original photoresist model is determined as a new subset, wherein the number of photoresist correction items in the initial subset is less than the number of photoresist correction items in the original photoresist model. Determine the photoresist model based on the new subset; Determine the optical model; Based on the optical model and the photoresist model, a model-based optical near-end correction (MOPC) is performed, and the design layout is updated to a second design layout. Determine whether the second design layout conforms to the design specifications; and Since the second design layout does not conform to the design specifications, the following steps are performed: The new subset is updated by incorporating more photoresist correction items; and The second design layout is then subjected to MOPC based on the updated subset, and the second design layout is updated to obtain the third design layout.

9. The method of claim 8, further comprising dividing the pattern edge of the design layout into a plurality of edge segments, and classifying the edge segments into at least a first-size edge segment set and a second-size edge segment set according to the critical dimensions of the pattern edge, wherein the step of performing model-based optical near-end correction (MOPC) based on the optical model and the photoresist model includes performing MOPC only on the first-size edge segment set.

10. A design layout system comprising one or more processors and one or more programs storing instructions, said instructions, when executed by said one or more processors, causing the system to perform the following steps: Receive design layout; Determine the first optical model and determine the first subset of photoresist correction items for the photoresist model; Based on the first optical model and the first subset of the photoresist model, a model-based optical near-end correction (MOPC) is performed and the design layout is updated to obtain a first updated design layout. Determine a second optical model and determine a second subset of the photoresist correction items of the photoresist model, wherein the second optical model is different from the first optical model, or the second subset is different from the first subset; MOPC is performed based on the second optical model and the second subset of the photoresist model, and the first updated design layout is updated to obtain the second updated design layout; and The photomask is manufactured according to the second updated design layout.

Images