A signal conversion system

Abstract

The present application provides a signal conversion system, characterized in that it includes: a conversion chip, the conversion chip includes: a signal conversion module, which is used to convert clock and data into a signal in a high-definition multimedia interface format. An audio clock regeneration module, which is used to transmit clock frequency parameters and periodic timestamp values ​​to a signal sending module. The signal sending module is used to package the clock frequency parameters and periodic timestamp values ​​into an audio clock regeneration package of a signal in a high-definition multimedia interface format as a packaged signal, and output the packaged signal. That is, one chip can be used to convert an embedded display interface signal to a signal in a high-definition multimedia interface format, and the audio bus signal built into the integrated circuit is embedded into the signal in a high-definition multimedia interface format through the audio clock regeneration module, thereby achieving synchronous output of audio and video while reducing power consumption and cost, effectively reducing the difficulty of design and debugging, and enhancing the stability and reliability of the solution.

Description

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 30, 2021, with application number 202123448593.2 and application name “A Signal Conversion System”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of signal processing, and in particular to a signal conversion system. Background Art

[0003] With the trend of increasing data transmission speed, multi-channel transmission, and high-resolution display, most display devices have been designed with high-resolution and high-transmission speed video interfaces, gradually eliminating old low-resolution video interfaces.

[0004] HDMI (High Definition Multimedia Interface) occupies about 95% of the market, which means that basically all new devices will be equipped with HDMI high-definition display interface. According to the latest HDMI2.1 standard, the resolution of HDMI interface can be as high as 8K. On the other hand, CPU also uses some high-definition digital interfaces to output higher-definition video signals to meet people's demand for high-definition display. According to Vesa's eDP1.4b protocol, the highest resolution can also reach 8K.

[0005] Nowadays, people's lives are inseparable from high-definition video display, so some differentiated solution designs need to convert eDP (embedded DisplayPort) into HDMI interface to output to TV and monitor. HDMI signal output needs to have audio experience to be good, but eDP signal does not have audio data packets. In order to solve this problem, I2S (Inter-IC Sound) audio signal needs to be embedded in HDMI video signal and output simultaneously.

[0006] The traditional eDP to HDMI with audio output solution usually converts the eDP signal into an internal video interface signal such as the MIPI (Mobile Industry Processor Interface) / LVDS (Low-Voltage Differential Signaling) interface, and then converts the MIPI / LVDS to HDMI. The I2S signal is input to the MIPI / LVDS to HDMI chip, and the conversion chip embeds the audio into the HDMI video signal, so that the HDMI output signal has sound.

[0007] However, the traditional conversion solution requires the use of multiple chips, and at least two chips are needed to build the eDP to HDMI function, resulting in relatively high power consumption and cost, complex solutions, and difficulty in debugging. Summary of the invention

[0008] In view of this, the purpose of this application is to provide a signal conversion system that reduces power consumption and cost, effectively reduces the difficulty of design and debugging, and enhances the stability and reliability of the solution.

[0009] To achieve the above purpose, this application has the following technical solutions:

[0010] The embodiment of the present application provides a signal conversion system, including: a conversion chip;

[0011] The conversion chip comprises:

[0012] A signal receiving module, used for receiving an embedded display interface signal, performing equalization processing, and transmitting the embedded display interface signal after equalization processing to a data recovery module;

[0013] One end of the data recovery module is connected to the signal receiving module, and the other end is connected to the signal conversion module, and is used to recover the clock and data from the embedded display interface signal after equalization processing, and transmit the clock and data to the signal conversion module;

[0014] The signal conversion module is also connected to the signal sending module, and is used to convert the clock and data into a signal in a high-definition multimedia interface format, and transmit the signal in the high-definition multimedia interface format to the signal sending module;

[0015] An audio clock regeneration module, connected to the signal sending module, for calculating the clock frequency parameter and the periodic timestamp value of the audio sampling rate according to the built-in audio bus signal of the integrated circuit, and transmitting the clock frequency parameter and the periodic timestamp value to the signal sending module;

[0016] The signal sending module is used to pack the clock frequency parameter and the periodic timestamp value into the audio clock regeneration package of the signal in the high-definition multimedia interface format as a packed signal, and output the packed signal.

[0017] In a possible implementation, the signal sending module is connected to a display, and the conversion chip further includes:

[0018] an auxiliary signal processing module, connected to the embedded display interface signal source and the signal sending module, for acquiring extended display identification data and display port configuration data, and sending the extended display identification data and the display port configuration data to the embedded display interface signal source;

[0019] The embedded display interface signal source determines the resolution of the embedded display interface signal according to the extended display identification data; the embedded display interface signal source determines the rate and the number of signal lines used by the embedded display interface signal according to the display port configuration data.

[0020] In a possible implementation, the system further includes a high-definition multimedia signal output interface, one end of which is connected to the signal sending module, and the other end of which is used to connect to the display;

[0021] Outputting the packaged signal includes:

[0022] The packaged signal is output to the high-definition multimedia signal output interface through a minimized transmission differential signal.

[0023] In a possible implementation, the system further includes a display data channel, one end of which is connected to the signal sending module and the other end of which is connected to the high-definition multimedia signal output interface;

[0024] The step of obtaining the extended display identification data includes:

[0025] The extended display identification data is acquired through the display data channel.

[0026] In a possible implementation, the system further includes:

[0027] Embedded display interface signal input interface and integrated circuit built-in audio bus signal input interface;

[0028] One end of the embedded display interface signal input interface is connected to the embedded display interface signal source, and the other end is connected to the signal receiving module, for transmitting the embedded display interface signal into the conversion chip;

[0029] One end of the integrated circuit built-in audio bus signal input interface is connected to the integrated circuit built-in audio bus signal source, and the other end is connected to the audio clock regeneration module, which is used to transmit the integrated circuit built-in audio bus signal into the conversion chip.

[0030] In a possible implementation, the system further includes:

[0031] A power supply module, one end of which is connected to a power supply, and the other end of which is connected to the power supply module of the conversion chip, is used to convert the voltage output by the power supply into a voltage corresponding to the conversion chip.

[0032] In a possible implementation, the embedded display interface signal input interface and the signal receiving module are connected via four pairs of differential signal lines.

[0033] In a possible implementation manner, the minimized transmission differential signal includes four pairs of differential signals.

[0034] In a possible implementation, the voltages corresponding to the conversion chip are 1.2V and 3.3V.

[0035] In a possible implementation, the conversion chip includes an ASIC chip or an FPGA chip.

[0036] The embodiment of the present application provides a signal conversion system, characterized in that it includes: a conversion chip, the conversion chip includes: a signal receiving module, which is used to receive an embedded display interface signal, perform equalization processing, and transmit the embedded display interface signal after equalization processing to a data recovery module, one end of the data recovery module is connected to the signal receiving module, and the other end is connected to the signal conversion module, which is used to recover the clock and data from the embedded display interface signal after equalization processing, and transmit the clock and data to the signal conversion module, the signal conversion module is also connected to the signal sending module, which is used to convert the clock and data into a signal in a high-definition multimedia interface format, and transmit the signal in the high-definition multimedia interface format to the signal sending module. An audio clock regeneration module is connected to the signal sending module, which is used to calculate the clock frequency parameters and cycle timestamp values ​​of the audio sampling rate according to the audio bus signal built into the integrated circuit, and transmit the clock frequency parameters and cycle timestamp values ​​to the signal sending module. The signal sending module is used to package the clock frequency parameters and cycle timestamp values ​​into the audio clock regeneration package of the signal in the high-definition multimedia interface format as a packaged signal, and output the packaged signal. That is, one chip can be used to convert embedded display interface signals into high-definition multimedia interface format signals, and the integrated circuit's built-in audio bus signal can be embedded into the high-definition multimedia interface format signal through the audio clock regeneration module, thereby achieving synchronous output of audio and video while reducing power consumption and cost, effectively reducing the difficulty of design and debugging, and enhancing the stability and reliability of the solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 A schematic diagram of a conventional signal conversion system is shown;

[0039] Figure 2 A schematic diagram of a signal conversion system provided by an embodiment of the present application is shown;

[0040] Figure 3 A schematic diagram of another signal conversion system provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

[0042] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0043] As described in the background technology, with the trend of increasing data transmission speed, multi-channel transmission, and high-resolution display, most display devices have been designed with high-resolution and high-transmission speed video interfaces, gradually eliminating old low-resolution video interfaces.

[0044] HDMI (High Definition Multimedia Interface) occupies about 95% of the market, which means that basically all new devices will be equipped with HDMI high-definition display interface. According to the latest HDMI2.1 standard, the resolution of HDMI interface can be as high as 8K. On the other hand, CPU also uses some high-definition digital interfaces to output higher-definition video signals to meet people's demand for high-definition display. According to Vesa's eDP1.4b protocol, the highest resolution can also reach 8K.

[0045] Nowadays, people's lives are inseparable from high-definition video display, so some differentiated solution designs need to convert eDP (embedded DisplayPort) into HDMI interface to output to TV and monitor. HDMI signal output needs to have audio experience to be good, but eDP signal does not have audio data packets. In order to solve this problem, I2S (Inter-IC Sound) audio signal needs to be embedded in HDMI video signal and output simultaneously.

[0046] The traditional eDP to HDMI with audio output solution usually converts the eDP signal into an internal video interface signal such as the MIPI (Mobile Industry Processor Interface) / LVDS (Low-Voltage Differential Signaling) interface, and then converts the MIPI / LVDS to HDMI. The I2S signal is input to the MIPI / LVDS to HDMI chip, and the conversion chip embeds the audio into the HDMI video signal, so that the HDMI output signal has sound.

[0047] However, the traditional conversion solution requires the use of multiple chips, and at least two chips are needed to build the eDP to HDMI function, resulting in relatively high power consumption and cost, complex solutions, and difficulty in debugging.

[0048] See also Figure 1 As shown, it is a schematic diagram of a traditional signal conversion system. The eDP signal is input to the eDP to MIPI / LVDS chip 3 via the eDP interface 2, and the I2S signal is input to the MIPI / LVDS to HDMI chip 4 via the I2S bus 1. The MIPI / LVDS to HDMI chip 4 will embed the audio into the HDMI video signal, so that the HDMI output signal has sound, and then it is output through the HDMI interface. This traditional solution has high power consumption, high cost, complex solution, and great debugging difficulty.

[0049] Specifically, this combination solution uses multiple chips, and at least two chips are needed to realize the eDP to HDMI function, resulting in relatively high power consumption and cost. MIPI / LVDS has strict timing requirements and is difficult to debug. Moreover, after multiple levels of conversion, stability cannot be guaranteed and is easily interfered by external factors.

[0050] In order to solve the above technical problems, the embodiment of the present application provides a signal conversion system, characterized in that it includes: a conversion chip, the conversion chip includes: a signal receiving module, which is used to receive the embedded display interface signal, perform equalization processing, and transmit the embedded display interface signal after equalization processing to the data recovery module, one end of the data recovery module is connected to the signal receiving module, and the other end is connected to the signal conversion module, which is used to recover the clock and data from the embedded display interface signal after equalization processing, and transmit the clock and data to the signal conversion module, the signal conversion module is also connected to the signal sending module, which is used to convert the clock and data into a signal in a high-definition multimedia interface format, and transmit the signal in the high-definition multimedia interface format to the signal sending module. An audio clock regeneration module is connected to the signal sending module, which is used to calculate the clock frequency parameters and cycle timestamp values ​​of the audio sampling rate according to the built-in audio bus signal of the integrated circuit, and transmit the clock frequency parameters and cycle timestamp values ​​to the signal sending module. The signal sending module is used to package the clock frequency parameters and cycle timestamp values ​​into the audio clock regeneration package of the signal in the high-definition multimedia interface format as a packaged signal, and output the packaged signal. That is, one chip can be used to convert embedded display interface signals into high-definition multimedia interface format signals, and the integrated circuit's built-in audio bus signal can be embedded into the high-definition multimedia interface format signal through the audio clock regeneration module, thereby achieving synchronous output of audio and video while reducing power consumption and cost, effectively reducing the difficulty of design and debugging, and enhancing the stability and reliability of the solution.

[0051] In order to better understand the technical solution and technical effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0052] Exemplary Systems

[0053] See also Figure 2 , which is a schematic diagram of a signal conversion system provided by an embodiment of the present application, includes: a conversion chip 5;

[0054] The conversion chip 5 includes:

[0055] The signal receiving module 51 is used for receiving the embedded display interface signal, performing equalization processing, and transmitting the embedded display interface signal after the equalization processing to the data recovery module.

[0056] One end of the data recovery module 52 is connected to the signal receiving module 51 , and the other end is connected to the signal conversion module 53 , and is used to recover the clock and data from the embedded display interface signal after equalization processing, and transmit the clock and data to the signal conversion module 53 .

[0057] The signal conversion module 53 is also connected to the signal sending module 55 , and is used for converting the clock and data into a signal in the high-definition multimedia interface format, and transmitting the signal in the high-definition multimedia interface format to the signal sending module 55 .

[0058] The audio clock regeneration (ACR) module 54 is connected to the signal sending module 55, and is used to calculate the clock frequency parameters and cycle timestamp value (N / CTS value, N / Cycle Time Stamp) of the audio sampling rate according to the built-in audio bus signal of the integrated circuit, and transmit the clock frequency parameters and cycle timestamp value to the signal sending module 55.

[0059] The signal sending module 55 is used to package the clock frequency parameter and the periodic timestamp value into the audio clock regeneration packet of the signal in the high-definition multimedia interface format as a packaged signal, and output the packaged signal.

[0060] Since the signal in the High Definition Multimedia Interface format has embedded audio signals, after being transmitted to the display device, the display device will recover the audio signals from the signal in the High Definition Multimedia Interface format according to the algorithm, and output them to the speakers after digital-to-analog conversion. In this way, the eDP to HDMI with audio solution can be realized.

[0061] It should be noted that the clock frequency parameter N is a value related to the clock frequency, and can be specifically calculated based on the sampling frequency and the TMDS (Transition Minimized Differential Signaling) clock frequency.

[0062] In one possible implementation, see Figure 3 As shown, the signal sending module 55 is connected to the display, and the conversion chip 5 also includes:

[0063] an auxiliary signal processing module 56, connected to the embedded display interface signal source and the signal sending module 55, for obtaining extended display identification data (EDID, Extended display identification data) and display port configuration data (DPCD, DisplayPort Configuration Data) and sending the extended display identification data and the display port configuration data to the embedded display interface signal source;

[0064] The embedded display interface signal source determines the resolution of the embedded display interface signal according to the extended display identification data; and determines the rate and the number of signal lines used by the embedded display interface signal according to the display port configuration data.

[0065] That is, in the embodiment of the present application, the auxiliary signal processing module 56 is used to process the AUX (Auxiliary, auxiliary signal) of the embedded display interface signal. More specifically, the embedded display interface signal source obtains the EDID through the auxiliary signal processing module 56, and after analyzing the DPCD information, it will generate a video signal of the corresponding resolution and give it to the conversion chip 5, thereby achieving better compatibility.

[0066] In one possible implementation, see Figure 3 As shown, the system also includes a high-definition multimedia signal output interface (HDMI output interface) 9, one end of which is connected to the signal sending module 55, and the other end is used to connect to the display.

[0067] Output the packaged signal, including:

[0068] The packaged signal is output to the high-definition multimedia signal output interface 9 through the minimized transmission differential signal TMDS58. Optionally, the TMDS signal is composed of 4 pairs of differential signals, which are used to transmit the HDMI signal to a TV, a monitor and other devices for video output. The HDMI output port 9 can be connected to any HDMI display device. The form of the HDMI output port 9 is not limited in the application, and it can be a male connector or a female connector.

[0069] In a possible implementation, the system further includes a display data channel 59 (DDC), one end of which is connected to the signal sending module 55 , and the other end of which is connected to the high-definition multimedia signal output interface 9 .

[0070] Get extended display identification data, including:

[0071] The extended display identification data is acquired through the display data channel 59 , and after the extended display identification data is acquired, it is transmitted to the auxiliary signal processing module 56 .

[0072] In a possible implementation, the system further includes:

[0073] Embedded display interface signal input interface 1 (eDP interface input) and integrated circuit built-in audio bus signal input interface (I2S digital audio input) 2.

[0074] One end of the embedded display interface signal input interface 1 is connected to the embedded display interface signal source, and the other end is connected to the signal receiving module 51 , so as to transmit the embedded display interface signal into the conversion chip 5 .

[0075] One end of the integrated circuit built-in audio bus signal input interface 2 is connected to the integrated circuit built-in audio bus signal source, and the other end is connected to the audio clock regeneration module 54 for transmitting the integrated circuit built-in audio bus signal into the conversion chip 5 .

[0076] In the embodiment of the present application, the embedded display interface signal input interface 1 can be connected to any device that supports eDP signal output, and is connected through eDP wires or PCB (Printed Circuit Board) wiring to transmit the eDP signal into the conversion chip 5. Optionally, the embedded display interface signal input interface and the signal receiving module are connected through 4 pairs of differential signal lines, and the differential signal lines are used to transmit the video signal eDP signal emitted by the eDP signal source, and send the eDP signal to the signal receiving module 51 of the ASIC.

[0077] Optionally, the auxiliary signal processing module 56 is connected to the embedded display interface signal source via the embedded display interface signal input interface 1 .

[0078] The audio bus signal input interface 2 built into the integrated circuit is connected to the conversion chip 5 through wires or PCB traces, and is input to the ACR module 54 of the conversion chip 5 .

[0079] In a possible implementation, the system further includes:

[0080] The power supply module 6 has one end connected to the power supply and the other end connected to the power module 57 of the conversion chip, which is used to convert the voltage output by the power supply into a voltage corresponding to the conversion chip 5, provide power for the entire system, and ensure the normal operation of the conversion chip 5. Specifically, the voltage corresponding to the conversion chip 5 can be 1.2V and 3.3V.

[0081] The embodiment of the present application provides a signal conversion system, characterized in that it includes: a conversion chip, the conversion chip includes: a signal receiving module, which is used to receive an embedded display interface signal, perform equalization processing, and transmit the embedded display interface signal after equalization processing to a data recovery module, one end of the data recovery module is connected to the signal receiving module, and the other end is connected to the signal conversion module, which is used to recover the clock and data from the embedded display interface signal after equalization processing, and transmit the clock and data to the signal conversion module, the signal conversion module is also connected to the signal sending module, which is used to convert the clock and data into a signal in a high-definition multimedia interface format, and transmit the signal in the high-definition multimedia interface format to the signal sending module. An audio clock regeneration module is connected to the signal sending module, which is used to calculate the clock frequency parameters and cycle timestamp values ​​of the audio sampling rate according to the audio bus signal built into the integrated circuit, and transmit the clock frequency parameters and cycle timestamp values ​​to the signal sending module. The signal sending module is used to package the clock frequency parameters and cycle timestamp values ​​into the audio clock regeneration package of the signal in the high-definition multimedia interface format as a packaged signal, and output the packaged signal. That is, one chip can be used to convert embedded display interface signals into high-definition multimedia interface format signals, and the integrated circuit's built-in audio bus signal can be embedded into the high-definition multimedia interface format signal through the audio clock regeneration module, thereby achieving synchronous output of audio and video while reducing power consumption and cost, effectively reducing the difficulty of design and debugging, and enhancing the stability and reliability of the solution.

[0082] Moreover, since the embodiment of the present application adopts a single-chip setting, there is no need for multi-stage conversion, which reduces the instability of the solution caused by multi-stage conversion. The HDMI signal output can achieve the best resolution output according to different HDMI display devices, with a resolution of up to 8K. Through the I2S digital audio signal input, the application pain point of no audio output when converting eDP to HDMI is solved.

[0083] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0084] The above is only a preferred implementation of the present application. Although the present application has been disclosed as a preferred embodiment, it is not intended to limit the present application. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present application without departing from the scope of the technical solution of the present application, or modify it into an equivalent embodiment of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still falls within the scope of protection of the technical solution of the present application.

Claims

1. A signal conversion system, characterized in that: include: Conversion chip; The conversion chip comprises: A signal receiving module, used for receiving an embedded display interface signal, performing equalization processing, and transmitting the embedded display interface signal after equalization processing to a data recovery module; One end of the data recovery module is connected to the signal receiving module, and the other end is connected to the signal conversion module, and is used to recover the clock and data from the embedded display interface signal after equalization processing, and transmit the clock and data to the signal conversion module; The signal conversion module is also connected to the signal sending module, and is used to convert the clock and data into a signal in a high-definition multimedia interface format, and transmit the signal in the high-definition multimedia interface format to the signal sending module; An audio clock regeneration module, connected to the signal sending module, for calculating a clock frequency parameter and a periodic timestamp value of an audio sampling rate according to a built-in audio bus signal of the integrated circuit, and transmitting the clock frequency parameter and the periodic timestamp value to the signal sending module; The signal sending module is used to pack the clock frequency parameter and the periodic timestamp value into the audio clock regeneration packet of the signal in the high-definition multimedia interface format as a packed signal, and output the packed signal; The signal sending module is connected to the display, and the conversion chip also includes: an auxiliary signal processing module, connected to the embedded display interface signal source and the signal sending module, for acquiring extended display identification data and display port configuration data, and sending the extended display identification data and the display port configuration data to the embedded display interface signal source; The embedded display interface signal source determines the resolution of the embedded display interface signal according to the extended display identification data; the embedded display interface signal source determines the rate and the number of signal lines used by the embedded display interface signal according to the display port configuration data; The system further comprises: Embedded display interface signal input interface and integrated circuit built-in audio bus signal input interface; One end of the embedded display interface signal input interface is connected to the embedded display interface signal source, and the other end is connected to the signal receiving module, for transmitting the embedded display interface signal into the conversion chip; One end of the integrated circuit built-in audio bus signal input interface is connected to the integrated circuit built-in audio bus signal source, and the other end is connected to the audio clock regeneration module, which is used to transmit the integrated circuit built-in audio bus signal into the conversion chip.

2. The system according to claim 1, characterized in that The system also includes a high-definition multimedia signal output interface, one end of which is connected to the signal sending module and the other end is used to connect to the display; Outputting the packaged signal includes: The packaged signal is output to the high-definition multimedia signal output interface through a minimized transmission differential signal.

3. The system according to claim 2, characterized in that The system also includes a display data channel, one end of which is connected to the signal sending module and the other end of which is connected to the high-definition multimedia signal output interface; The step of obtaining the extended display identification data includes: The extended display identification data is acquired through the display data channel.

4. The system according to claim 1, characterized in that The system further comprises: A power supply module, one end of which is connected to a power supply, and the other end of which is connected to the power supply module of the conversion chip, is used to convert the voltage output by the power supply into a voltage corresponding to the conversion chip.

5. The system according to claim 1, characterized in that The embedded display interface signal input interface and the signal receiving module are connected via four pairs of differential signal lines.

6. The system according to claim 2, characterized in that The minimized transition differential signal includes four pairs of differential signals.

7. The system according to claim 4, characterized in that The voltages corresponding to the conversion chip are 1.2V and 3.3V.

8. According to the system according to any one of claims 1 to 7, the conversion chip comprises an ASIC chip or a FPGA chip.

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