Drive circuit

Abstract

A driving circuit capable of improving a data transfer rate of an output signal is provided. The driving circuit according to the present disclosure includes a first driver disposed on a substrate, receiving a first power voltage and a second power voltage, and outputting the first power voltage or the second power voltage as a first signal according to an input signal; a resistive element connected to an output of the first driver; a first pad connected to the first driver via the resistive element and outputting the first signal from the first driver as an output signal via the resistive element; and a second pad disposed in a vicinity of the first pad and driven by a driving signal based on the input signal.

Description

Technical Field

[0001] This disclosure relates to a driving circuit. Background Technology

[0002] In communication devices such as smartphones, the amount of data transmitted has been increasing in recent years. Therefore, there is a need to improve the data transmission rate of these devices. To increase the data transmission rate, it is also necessary to increase the operating speed of the output driver circuitry used for the interface.

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2011-166260

[0006] Patent Document 2: Japanese Patent Application Publication No. 2006-135344 Summary of the Invention

[0007] The problem to be solved by the present invention

[0008] The output drive circuit has an electrostatic discharge (ESD) protection circuit and an output pad disposed on the same semiconductor chip. Additionally, the output drive circuit has an output resistor for matching the load impedance.

[0009] Therefore, the parasitic capacitance of the ESD protection circuit, the parasitic capacitance of the output pads, and the RC time constant caused by the output resistance delay the rise time Tr (Time up) and fall time Tf (Time fall) of the digital signal output from the output driver circuit. This delay in the rise time Tr and fall time Tf of the output signal hinders the increase of data transmission rate.

[0010] Therefore, this disclosure provides a drive circuit that can improve the data transmission rate of the output signal.

[0011] Solution to the problem

[0012] One aspect of this disclosure provides a driving circuit, comprising: a first driver disposed on a substrate, receiving a first power supply voltage and a second power supply voltage, and outputting the first power supply voltage or the second power supply voltage as a first signal according to an input signal; a resistor element connected to the output of the first driver; a first pad connected to the first driver via the resistor element and outputting the first signal from the first driver as an output signal via the resistor element; and a second pad disposed near the first pad and driven by a driving signal based on the input signal.

[0013] The driving circuit may further include a second driver disposed on the substrate, which receives a third power supply voltage and a fourth power supply voltage, and outputs the third voltage or the fourth voltage to the second pad according to the input signal.

[0014] The output of the first driver can be connected to both the first pad and the second pad.

[0015] The second pad can be positioned between the first pad and the substrate.

[0016] It may also include a through electrode that penetrates the substrate, a first pad that may be disposed on the through electrode in a manner that contacts the through electrode, and a second pad that may be disposed above the first pad.

[0017] The first pad may include multiple first conductor layers stacked on top of the substrate.

[0018] It may further include a second conductor layer disposed on the outer periphery of the first pad, electrically isolated from the first pad and electrically connected to the second pad.

[0019] It may further include a plurality of second conductor layers disposed on the respective outer peripheries of the plurality of first conductor layers, electrically isolated from the plurality of first conductor layers, and electrically connected to the second pads.

[0020] Each of the plurality of second conductor layers can be disposed in the same layer as a corresponding one of the plurality of first conductor layers.

[0021] The drive signal can be in phase with the first signal.

[0022] The third and fourth power supply voltages can be between the first and second power supply voltages, and

[0023] The difference between the third power supply voltage and the fourth power supply voltage can be less than the difference between the first power supply voltage and the second power supply voltage.

[0024] The difference between the third and fourth power supply voltages can be approximately half the difference between the first and second power supply voltages.

[0025] The third and fourth power supply voltages can be adjusted to correct the waveform of the output signal.

[0026] The rise or fall timing of the drive signal can be adjusted to correct the waveform of the output signal.

[0027] It may further include an ESD protection circuit disposed between the substrate and the node between the resistive element and the first pad. Attached Figure Description

[0028] Figure 1This is a schematic diagram illustrating an example configuration of a portable electronic device including a drive circuit according to the present disclosure.

[0029] Figure 2 This is a block diagram illustrating an example configuration of the drive circuit according to the first embodiment.

[0030] Figure 3 This is a timing diagram illustrating an example of the operation of the drive circuit according to the first embodiment.

[0031] Figure 4A This is a plan view showing an example configuration of pads and virtual pads.

[0032] Figure 4B This is a cross-sectional view showing an example configuration of pads and virtual pads.

[0033] Figure 5A This is a plan view showing another configuration example of pads and virtual pads.

[0034] Figure 5B This is a cross-sectional view showing another configuration example of pads and virtual pads.

[0035] Figure 6A This is a plan view showing yet another configuration example of pads and virtual pads.

[0036] Figure 6B This is a cross-sectional view showing another configuration example of pads and virtual pads.

[0037] Figure 7 This is a plan view showing yet another configuration example of pads and virtual pads.

[0038] Figure 8 This is a plan view showing yet another configuration example of pads and virtual pads.

[0039] Figure 9 This is a plan view showing yet another configuration example of pads and virtual pads.

[0040] Figure 10 This is a block diagram illustrating an example configuration of a differential transmission circuit using a drive circuit according to the second embodiment.

[0041] Figure 11 This is a block diagram illustrating an example configuration of the drive circuit according to the third embodiment.

[0042] Figure 12 This is a timing diagram illustrating an example of the operation of the drive circuit according to the third embodiment.

[0043] Figure 13A This is a timing diagram showing an example of the operation of the drive circuit according to the fourth embodiment.

[0044] Figure 13B This is a timing diagram showing an example of the operation of the drive circuit according to the fourth embodiment.

[0045] Figure 14 This is a timing diagram showing an example of the operation of the drive circuit according to the fifth embodiment. Detailed Implementation

[0046] Specific embodiments of the application of this technology will now be described in detail with reference to the accompanying drawings. The drawings are schematic or conceptual, and the scale of the parts may not necessarily be the same as actual parts. In the specification and drawings, elements similar to those described above with reference to the drawings are indicated by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0047] (First Embodiment)

[0048] Figure 1 This is a schematic diagram illustrating an example configuration of a portable electronic device including the driving circuit according to the present disclosure. The portable electronic device (hereinafter referred to as electronic device 1) is, for example, an electronic device such as a smartphone. Electronic device 1 includes, for example, a CMOS image sensor (CIS) 2, an application processor 3, a timing controller 4, a column driver 5, and a liquid crystal display (LCD) 6. The CIS 2 captures images via an optical lens and sends image data to the application processor 3. The application processor 3 processes the image data and sends the processed image data to the timing controller 4. The timing controller 4 receives the image data and controls the column driver 5 to display the image on the LCD 6. As in this example, data is exchanged between various internal devices within electronic device 1. Each internal device has a transmission circuit Tx and a receiving circuit Rx for transmitting and receiving data. With the recent dramatic increase in data capacity, there is an increasing need for the data transmission rate of the interface circuit consisting of the transmission circuit Tx and the receiving circuit. The interface circuit uses a driving circuit to amplify the digital signal for the output of the transmission circuit Tx. Note that the driving circuit 10 of this disclosure can be applied to any other electronic device.

[0049] Figure 2 This is a block diagram illustrating an example configuration of the drive circuit 10 according to the first embodiment. The drive circuit 10 includes a substrate 11, a driver 20, a dummy driver 30, a resistive element 40, a pad 50, a dummy pad 60, first to fourth power supplies 71 to 74, and an ESD protection circuit 80.

[0050] The drive circuit 10 is provided in each internal device that outputs data, receives digital data as input signals, and outputs output signals according to the logic of the input signals. The drive circuit 10 can be built into any of the semiconductor chips constituting the aforementioned internal devices, or it can be configured as a single semiconductor chip. Furthermore, the drive circuit 10 can be a module composed of multiple semiconductor chips. Hereinafter, the drive circuit 10 will be described as being composed of a single semiconductor chip.

[0051] The substrate 11 is, for example, a semiconductor substrate such as a silicon substrate, on which the constituent elements of the driving circuit 10 are formed. The substrate 11 is connected to ground GND and has a ground potential.

[0052] Driver 20, serving as the first driver, is disposed on substrate 11 and receives voltage Vdd as a first power supply voltage from first power supply 71 and voltage Vss as a second power supply voltage from second power supply 72. Driver 20 outputs either voltage Vdd or voltage Vss as a first signal S1 according to the logic of the input signal. Voltage Vdd is higher than voltage Vss. For example, when the voltage Vin of the input signal indicates a high level, driver 20 outputs voltage Vdd as the first signal S1. When the voltage Vin of the input signal indicates a low level, driver 20 outputs voltage Vss as the first signal S1. The voltage amplitude of the first signal S1 is greater than the voltage amplitude of the input signal, and driver 20 amplifies and outputs the input signal. Alternatively, the voltage amplitude of the first signal S1 may be less than the voltage amplitude of the input signal, and driver 20 may weaken and output the input signal.

[0053] A resistor element 40 is disposed on the substrate 11 and connected to the output terminal of the driver 20. The resistor element 40 is configured to perform impedance matching with the input impedance connected to the load side of the pad 50. For example, the resistance value R0 of the resistor element 40 is set in the range of 30 ohms to 100 ohms depending on the input impedance of the load. The first signal S1 passes through the resistor element 40, is transmitted to the pad 50, and is output from the pad 50 as the output signal Sout.

[0054] The pad 50, serving as the first pad, is connected to the driver 20 via a resistor 40. The pad 50 outputs a first signal S1 from the driver 20 via the resistor 40 as an output signal Sout. A conductive metal such as aluminum is used for the pad 50. The pad 50 is disposed above the substrate 11, separated from the substrate 11 by an insulating film such as a silicon oxide film and a dummy pad 60. Consequently, a parasitic capacitance Cpad1 exists between the pad 50 and the dummy pad 60, and a parasitic capacitance Cpad2 exists between the dummy pad 60 and the substrate 11.

[0055] A virtual driver 30, serving as a second driver, is disposed on the substrate 11 and receives voltage Vdd_dum as the third power supply voltage from the third power supply 73 and voltage Vss_dum as the fourth power supply voltage from the fourth power supply 74. The virtual driver 30 receives the same input signal as the input signal received by the driver 20. Then, the virtual driver 30 outputs either voltage Vdd_dum or voltage Vss_dum as a drive signal according to the logic of the input signal. Voltage Vdd_dum is higher than voltage Vss_dum and lower than voltage Vdd. Voltage Vss_dum is higher than voltage Vss. Therefore, in this disclosure, voltages Vdd_dum and Vss_dum are between voltages Vdd and Vss, and the difference between voltages Vdd_dum and Vss_dum (Vdd_dum - Vss_dum) is less than the difference between voltages Vdd and Vss (Vdd - Vss). The output terminal of the virtual driver 30 is connected to a virtual pad 60. The resistance between the output of the virtual driver 30 and the virtual pad 60 is much smaller than the resistance R0 of the resistor element 40. Therefore, the drive signal output from the virtual driver 30 and driving the virtual pad 60 is an in-phase signal that is basically synchronized with the first signal S1.

[0056] The virtual pad 60, serving as the second pad, is positioned near the pad 50, for example, directly below the pad 50. That is, the virtual pad 60 is positioned between the pad 50 and the substrate 11. For example, an insulating film such as a silicon oxide film is disposed between the virtual pad 60 and the pad 50, and the virtual pad 60 and the pad 50 are capacitively coupled. Therefore, the virtual driver 30 can influence the voltage of the pad 50 by driving the voltage of the virtual pad 60. In other words, the capacitive coupling between the pad 50 and the virtual pad 60 can be used to correct the output signal Sout using the drive signal Sd.

[0057] Furthermore, the virtual pad 60 is connected to the output of the virtual driver 30 and is driven by a drive signal Sd from the virtual driver 30 based on the input signal. As mentioned above, the drive signal Sd is an in-phase signal that is substantially synchronized with the first signal S1. Therefore, the drive signal Sd rises and falls substantially simultaneously with the first signal S1. However, since the resistor element 40 and the ESD protection circuit 80 are connected between the driver 20 and the pad 50, the output signal Sout is delayed by an RC time constant in both rise and fall times compared to the first signal S1 and the drive signal Sd. (See below for further details.) Figure 3 Describe the RC delay.

[0058] ESD protection circuit 80 is connected between node N1 and substrate 11 (i.e., ground GND). Node N1 is the connection node between resistive element 40 and pad 50. ESD protection circuit 80 is constructed, for example, by a diode, capacitor, or transistor. This allows ESD protection circuit 80 to protect drive circuit 10 and other internal components from ESD from pad 50, etc. ESD protection circuit 80 has parasitic capacitance Cesd between node N1 and substrate 11.

[0059] Next, the operation of the drive circuit 10 will be described.

[0060] Figure 3 This is a timing diagram illustrating an example of the operation of the drive circuit 10 according to the first embodiment. The driver 20 receives an input signal and outputs a first signal S1 corresponding to the input signal. At this time, according to the logic of the input signal, the first signal S1 is a rectangular pulse signal. The amplitude of the first signal S1 corresponds to the difference between voltage Vdd and voltage Vss.

[0061] The virtual driver 30 outputs an in-phase signal synchronized with the first signal S1 as a drive signal Sd. Therefore, similar to the first signal S1, the drive signal Sd is a rectangular pulse signal according to the logic of the input signals. The amplitude of the drive signal Sd corresponds to the difference between voltage Vdd_dum and voltage Vss_dum. For example, the amplitude of the drive signal Sd can be approximately half the amplitude of the first signal S1.

[0062] Both the first signal S1 and the driving signal Sd rise at times t1 and t3 and fall at times t2 and t4. It should be noted that although at... Figure 3 Only two pulse signals are shown in the diagram; the first signal S1 and the drive signal Sd also include a large number of pulse signals.

[0063] Here, as Figure 2 As shown, the output of driver 20 is connected to pad 50 via resistor element 40, and node N1 is connected to ESD protection circuit 80. Therefore, due to the parasitic capacitance Cesd of resistor element 40, ESD protection circuit 80, and parasitic capacitances Cpad1 and Cpad2 between pad 50 and substrate 11, the output of driver 20 has an RC time constant.

[0064] Without setting virtual pad 60, or without virtual driver 30 driving virtual pad 60, the rise time Tr0 and fall time Tf0 of the output signal Sout become longer due to the RC time constant. That is, as Figure 3As shown by the dashed line in the diagram, the output signal Sout has an RC delay relative to the square wave of the first signal S1, and is rounded on both the rise and fall. This is because time is required to charge and discharge the parasitic capacitances Cesd, Cpad1, and Cpad2. Consequently, the output signal Sout deteriorates, making it difficult to increase the data transmission rate.

[0065] On the other hand, the drive circuit 10 according to this disclosure has a virtual driver 30 and a virtual pad 60, and the output of the virtual driver 30 is directly wired and connected to the virtual pad 60 without any resistors or the like. That is, the resistance of node N2 between the output of the virtual driver 30 and the virtual pad 60 is essentially zero, and there is no resistor corresponding to the resistor element 40, which allows the voltage of node N2 to respond quickly according to the output of the virtual driver 30. Therefore, the drive signal Sd from the virtual driver 30 is transmitted to the virtual pad 60 without delay, thereby causing the virtual pad 60 to rise or fall rapidly. That is, with Figure 3 The driving signal Sd shown in the diagram drives the voltage of the virtual pad 60 in a roughly similar manner. The driving signal Sd is an in-phase signal synchronized with the first signal S1. Therefore, the voltage of the virtual pad 60 can be driven by the driving signal Sd with almost no delay relative to the first signal S1.

[0066] As described above, the output signal Sout is driven by the drive signal Sd through capacitive coupling between pad 50 and dummy pad 60. For example, in Figure 3 At times t1 and t3, due to the rise of the drive signal Sd at virtual pad 60, the rise of the output signal Sout at pad 50 becomes sharp, and the rise time becomes Tr1. The rise time Tr1 is shorter than the rise time Tr0. Furthermore, at times t2 and t4, the fall of the output signal Sout at pad 50 becomes steep due to the fall of the drive signal Sd at virtual pad 60, and the fall time becomes Tf1. The fall time Tf1 is shorter than the fall time Tf0. As described above, because virtual pad 60 is charged and discharged synchronously with the output signal Sout by the drive signal Sd, the output signal Sout rises sharply with... Figure 2 The parasitic capacitance Cpad1 in the matrix becomes smaller or disappears. Therefore, as... Figure 3 As shown by the solid line representing Sout, the output signal Sout becomes steep at both its rise and fall points, and thus becomes a signal with a small delay relative to the first signal S1. By using an output signal Sout with less degradation as described above, the data transmission rate can be improved.

[0067] (Configuration example for virtual pad 60)

[0068] Figure 4A and Figure 4BThese are plan and cross-sectional views showing an example configuration of pad 50 and dummy pad 60. (See attached diagram.) Figure 4B As shown, a virtual pad 60 is disposed between the pad 50 and the substrate 11, and is formed in the metal layer MT5 directly below the metal layer MT6 of the pad 50. It should be noted that in this example, the first metal layers MT1 to the sixth metal layers MT6 are disposed on the substrate 11. The pad 50 is formed in the sixth metal layer (topmost layer) MT6, and the virtual pad 60 is formed in the fifth metal layer MT5. An interlayer insulating film 90 is disposed between each adjacent metal layer from the first metal layer MT1 to the sixth metal layer MT6. Between the virtual pad 60 and the substrate 11, the first to fourth metal layers MT1 to MT4 are removed, and the interlayer insulating film 90 is disposed.

[0069] As described above, the virtual pad 60 is formed in the metal layer MT5 of the metal layer MT6 immediately adjacent to the pad 50. This improves the capacitive coupling between the pad 50 and the virtual pad 60, allowing the output signal Sout of the pad 50 to be easily controlled via the drive signal Sd of the virtual pad 60. Note that it is sufficient if the parasitic capacitance Cpad1 is made electrically smaller. The capacitive coupling between the pad 50 and the virtual pad 60 is optional and does not necessarily need to be increased.

[0070] If the dimensions of pad 50 and virtual pad 60 are... Figure 4A The dimensions shown are approximately the same, which is sufficient. Pad 50 and dummy pad 60 are configured to overlap each other when viewed from above the surface of substrate 11. This allows for a reduction in parasitic capacitance between pad 50 and substrate 11.

[0071] Although not shown, the virtual pad 60 may be larger than the pad 50. In this case, the outer edge of the virtual pad 60 is preferably positioned outside the outer edge of the pad 50 when viewed from above the surface of the substrate 11. This allows for further reduction of the parasitic capacitance between the pad 50 and the substrate 11, and the output signal Sout of the pad 50 can be more easily controlled by the drive signal Sd of the virtual pad 60.

[0072] (First variation)

[0073] Figure 5A and Figure 5B This is a plan view and a cross-sectional view showing another construction example of pad 50 and dummy pad 60. (See attached image.) Figure 5B As shown, the virtual pad 60 is disposed between the pad 50 and the substrate 11, and is formed in the third metal layer MT3 below the pad 50 in the sixth metal layer.

[0074] In addition, such as Figure 5AAs shown, the driving circuit 10 further includes a conductor layer 100_6, serving as a second conductor layer, disposed on the outer periphery of the pad 50. An interlayer insulating film 90 is disposed between the conductor layer 100_6 and the pad 50, and the conductor layer 100_6 is electrically isolated from the pad 50. Figure 5B As shown, conductor layers 100_4 and 100_5, having the same planar layout as conductor layer 100_6, are disposed below conductor layer 100_6. Similar to conductor layer 100_6, conductor layers 100_4 and 100_5 are electrically isolated from pad 50. For conductor layers 100_4 to 100_6, a conductive metal such as aluminum is used, similar to pad 50 and dummy pad 60.

[0075] like Figure 5B As shown, conductor layers 100_4 to 100_6 are disposed in the fourth metal layers MT4 to the sixth metal layers MT6, and each of conductor layers 100_4 to 100_6 is electrically connected to the virtual pad 60 via a via 110. Using this configuration, conductor layers 100_4 to 100_6 are driven to the same voltage as the virtual pad 60. A virtual pad 60 larger than the pad 50 is formed to obtain electrical connection with conductor layers 100_4 to 100_6. Thus, the outer edge of the virtual pad 60 is located outside the outer edge of the pad 50.

[0076] Conductor layer 100_6 is disposed in the same sixth metal layer MT6 as pad 50, and extends along the outer edge of pad 50 to the edge EG of the semiconductor chip. As described above, although with Figure 4B Compared to the virtual pad 60, the virtual pad 60 is separate from the pad 50, but the conductor layer 100_6 is disposed near the pad 50. Furthermore, because the conductor layer 100_6 is disposed along the side surface of the pad 50 to face the side surface, the virtual pad 60 and conductor layers 100_4 to 100_6 cover the bottom and side surfaces of the pad 50. This allows for a further reduction in the parasitic capacitance between the pad 50 and the substrate 11.

[0077] In the first variation, such as Figure 5B As shown, the virtual pad 60 is disposed in the third metal layer MT3. However, the virtual pad 60 can be disposed in any of the first metal layers MT1 to the fifth metal layer MT5. It should be noted that in order to increase the coupling capacitance between the pad 50 and the virtual pad 60 itself, it is preferable to dispose of the virtual pad 60 in a metal layer close to the sixth metal layer MT6.

[0078] (Second variation)

[0079] Figure 6A and Figure 6B This is a plan view and a cross-sectional view showing another configuration example of pad 50 and dummy pad 60. (See attached image.) Figure 6BAs shown, the pad 50 is composed of multiple pad portions (first conductor layers) 50_4 to 50_6 stacked on the substrate 11. The pad portions 50_4 to 50_6 are disposed in multiple metal layers MT4 to MT6. The pad portions 50_4 to 50_6 are electrically connected via vias 120 and integrated into the pad 50.

[0080] Multiple conductor layers (second conductor layers) 100_4 to 100_6 are respectively disposed on the outer periphery of pad portions 50_4 to 50_6. Conductor layers 100_4 to 100_6 are disposed in the same layer as pad portions 50_4 to 50_6, but are electrically isolated from pad portions 50_4 to 50_6. On the other hand, conductor layers 100_4 to 100_6 are electrically connected to the virtual pad 60 via via 110. Other components in the second variation may be similar to the corresponding components in the first variation.

[0081] As described above, the pad 50 can be composed of pad portions 50_4 to 50_6 in multiple metal layers MT4 to MT6. This allows the pad 50 to withstand the impact of wire bonding. Furthermore, conductor layers 100_4 to 100_6 are respectively disposed along the side surfaces of the pad portions 50_4 to 50_6 to face the side surfaces. This allows for a further reduction in parasitic capacitance between the pad 50 and the substrate 11.

[0082] Furthermore, in the second variation, the virtual pad 60 can be disposed in any one of the first metal layers MT1 to the third metal layer MT3. It should be noted that, in order to increase the coupling capacitance between the pad 50 and the virtual pad 60 itself, it is preferable to dispose of the virtual pad 60 in a metal layer close to the sixth metal layer MT6.

[0083] (Variation Example 3)

[0084] Figure 7 This is a plan view showing another configuration example of pad 50 and dummy pad 60. (See diagram below.) Figure 7 As shown, a conductor layer 100 can be disposed on substantially the entire outer periphery of the pad 50. In this case, the conductor layer 100 appears at the edge EG of the semiconductor chip. As described above, the conductor layer 100 is disposed on the entire outer periphery of the pad 50, and this allows for a further reduction in the parasitic capacitance between the pad 50 and the substrate 11. A third modification can be applied to either the first or the second modification.

[0085] (Variation Example 4)

[0086] Figure 8This is a plan view showing another configuration example of pad 50 and dummy pad 60. In a fourth variation, a through electrode 130 is provided through the substrate 11. The through electrode 130 is electrically connected to pad 50 on the front surface side of the substrate 11 and to another portion provided on the rear surface side of the substrate 11. This allows the through electrode 130 to electrically connect pad 50 and other portions.

[0087] Pad 50 is disposed on and in contact with through electrode 130. Virtual pad 60 is disposed near and above pad 50. In this case, since virtual pad 60 cannot be disposed between pad 50 and substrate 11, the effect of reducing parasitic capacitance between substrate 11 and pad 50 is small. However, the output signal Sout of pad 50 can be easily controlled by the drive signal Sd of virtual pad 60.

[0088] (Variation Example 5)

[0089] Figure 9 This is a plan view illustrating yet another configuration example of pad 50 and dummy pad 60. A fifth variation further includes a conductor layer 100 disposed on the outer periphery of pad 50. Conductor layer 100 is electrically isolated from pad 50 but electrically connected to dummy pad 60 via via 110. With this configuration, conductor layer 100 is driven to the same voltage as dummy pad 60.

[0090] A virtual pad 60 is disposed above the pad 50. A conductor layer 100 is disposed along the outer periphery of the pad 50 to face the outer periphery, and this allows for a reduction in parasitic capacitance between the pad 50 and the substrate 11.

[0091] The other elements of the fifth variation can be similar to the corresponding elements of the fourth variation. Therefore, the fifth variation can also have the same effect as the fourth variation.

[0092] (Second Embodiment)

[0093] Figure 10 This is a block diagram illustrating an example configuration of a differential transmission circuit using a drive circuit 10 according to a second embodiment. The differential transmission circuit includes drive circuits 10n and 10p that output output signals Sout_n and Sout_p with opposite phases to each other. Drive circuits 10n and 10p may both have the same configuration as drive circuit 10 in the first embodiment.

[0094] For example, driver circuit 10P receives the input signal Vin_p. Driver circuit 20_p outputs a first signal S1_p based on the input signal Vin_p. The first signal S1_p outputs an output signal Sout_p from pad 50_p via resistor element 40_p. Virtual driver 30_p outputs a drive signal Sd_p based on the input signal Vin_p. Virtual pad 60_p is driven by drive signal Sd_p and can cause the rise and fall of the output signal Sout_p to become steep.

[0095] The driver circuit 10N receives an input signal Vin_n that is inverted compared to the input signal Vin_p. The driver circuit 20_n outputs a first signal S1_n based on the input signal Vin_n. The first signal S1_n is output as an output signal Sout_n from the pad 50 via the resistor element 40. The virtual driver 30_n outputs a drive signal Sd_n based on the input signal Vin_n. The virtual pad 60_n is driven by the drive signal Sd_n and can cause the rise and fall of the output signal Sout_n to become steeper.

[0096] Because the input signals Vin_p and Vin_n operate in opposite phases, the output signals Sout_p and Sout_n also become signals with opposite phases.

[0097] Each of the two input terminals on the Rx side of the receiving circuit has an input impedance of R0, which is essentially equal to the resistance value R0 of the resistive element 40. That is, the drive circuits 10P and 10N are impedance matched to the receiving circuit Rx.

[0098] In this scenario, for example, assume that driver circuit 10P outputs a logic high as the output signal Sout_p, and driver circuit 10N outputs a logic low as the output signal Sout_n. At this time, the first signal S1_p is essentially equal to the voltage Vdd, and the first signal S1_n is essentially equal to the voltage Vss. The voltage difference Vdd-Vss is divided by resistive elements 40_p and 40_n and the two input impedances R0 of the receiving circuit Rx. Therefore, the voltage Vout_p of the output signal Sout_p is 3 / 4 × Vdd + 1 / 4 × Vss, and the voltage Vout_n of the output signal Sout_n is 1 / 4 × Vdd + 3 / 4 × Vss. Then, the voltage at the internal node Nr of the receiving circuit Rx is 1 / 2 × Vdd + 1 / 2 × Vss.

[0099] Here, when the voltage Vdd_dum of power supply 73 is set to 3 / 4×Vdd+1 / 4×Vss, the voltage of the drive signal Sd_p becomes 3 / 4×Vdd+1 / 4×Vss, and the virtual pad 60_p is driven to a voltage substantially the same as that of pad 50_p. Furthermore, when the voltage Vss_dum of power supply 74 is set to 1 / 4×Vdd+3 / 4×Vss, the voltage of the drive signal Sd_n becomes 1 / 4×Vdd+3 / 4×Vss, and the virtual pad 60_n is driven to a voltage substantially the same as that of pad 50_n.

[0100] On the other hand, when the driver circuit 10P outputs logic low as the output signal Sout_p and the driver circuit 10N outputs logic high as the output signal Sout_n, the voltage Vout_n of the output signal Sout_n is 3 / 4 × Vdd + 1 / 4 × Vss. The voltage Vout_p of the output signal Sout_p is 1 / 4 × Vdd + 3 / 4 × Vss. Then, the voltage at the internal node Nr of the receiving circuit Rx is 1 / 2 × Vdd + 1 / 2 × Vss.

[0101] Here, as described above, it is assumed that the voltage Vdd_dum of power supply 73 is set to 3 / 4 × Vdd + 1 / 4 × Vss, and the voltage Vss_dum of power supply 74 is set to 1 / 4 × Vdd + 3 / 4 × Vss. In this case, the voltage of the drive signal Sd_n becomes 3 / 4 × Vdd + 1 / 4 × Vss, and the virtual pad 60_n is driven to a voltage substantially the same as that of pad 50_n. Furthermore, the voltage of the drive signal Sd_p becomes 1 / 4 × Vdd + 3 / 4 × Vss, and the virtual pad 60_p is driven to a voltage substantially the same as that of pad 50_p.

[0102] This allows the amplitudes of the drive signals Sd_n and Sd_p to be substantially equal to the amplitudes of the output signals Sout_n and Sout_p, and the parasitic capacitance Cpad1 appears nonexistent when viewed from pads 50_p and 50_n. Therefore, the drive signals Sd_n and Sd_p make the rise and fall times of the output signals Sout_n and Sout_p closer to the first signals S1_n and S1_p. Consequently, the rise time Tr and fall time Tf of the output signals Sout_n and Sout_p can be shortened, and the data transmission rate can be increased.

[0103] The drive circuit 10 according to this disclosure can be applied not only to differential transmission circuits, but also to single transmission circuits.

[0104] Furthermore, the voltage Vdd_dum of power supplies 73 and 74 can be set higher than the logic high voltage of pads 50_p and 50_n by 3 / 4 × Vdd + 1 / 4 × Vss, and the voltage Vss_dum of power supplies 73 and 74 can be set lower than the logic low voltage of pads 50_p and 50_n by 1 / 4 × Vdd + 3 / 4 × Vss. This allows the output signals Sout_n and Sout_p to form waveforms with overshoot at the rise and fall points. It should be noted that the function of correcting the output signals Sout_n and Sout_p will be described later.

[0105] (Third Embodiment)

[0106] Figure 11 This is a block diagram illustrating an example configuration of the drive circuit 10 according to a third embodiment. The drive circuit 10 according to the third embodiment does not include a virtual driver 30. A virtual pad 60 is connected to the output of driver 20 and receives a first signal S1 from driver 20. That is, the output of driver 20 is connected to both pad 50 and virtual pad 60. However, pad 50 is connected to the output of driver 20 via a resistor element 40, and virtual pad 60 is directly wired and connected to the output of driver 20 without a resistor element 40 in between. Furthermore, the ESD protection circuit 80 is connected only to node N1 and not to node N2. Therefore, the first signal S1 from driver 20 is transmitted to virtual pad 60 without RC delay and is also used as a drive signal Sd. Other elements in the third embodiment may be similar to their counterparts in the first embodiment.

[0107] In the third embodiment, as Figure 12 As shown, the amplitude of the drive signal Sd of the virtual pad 60 corresponds to the difference between voltage Vdd and voltage Vss, and is consistent with the amplitude of the first signal S1. Because the logic high of the output signal Sout is lower than the voltage Vdd, the output signal Sout has overshoot and undershoot at its rise. As described above, in cases where shortening the rise time Tr and fall time Tf is emphasized even with overshoot and undershoot, the driver 20 can be shared with the pad 50 and the virtual pad 60. This also allows for a reduction in the circuit size and layout area of ​​the drive circuit 10.

[0108] (Fourth Embodiment)

[0109] Figure 13A and Figure 13B This is a timing diagram illustrating an example of operation of the drive circuit according to the fourth embodiment. In the fourth embodiment, the waveform of the output signal Sout is corrected by changing the amplitudes of the third power supply voltage Vdd_dum and the fourth power supply voltage Vss_dum (i.e., the amplitude of the drive signal Sd).

[0110] For example, in order to prevent in Figure 13A Overshoot and undershoot occur in the waveform of the output signal Sout, causing the third power supply voltage Vdd_dum to be lower than the logic high voltage of the output signal Sout, and the fourth power supply voltage Vss_dum to be higher than the logic low voltage of the output signal Sout. With this configuration, the amplitude of the drive signal Sd falls within the range of the amplitude of the output signal Sout. Therefore, the rise time Tr and fall time Tf of the output signal Sout can be shortened, while suppressing overshoot and undershoot in the output signal Sout. This corresponds to the first embodiment.

[0111] For example, in order to make overshoot OSH and undershoot USH appear in the waveform of the output signal Sout, such as Figure 13B As shown, the third power supply voltage Vdd_dum is higher than the logic high voltage of the output signal Sout, and the fourth power supply voltage Vss_dum is lower than the logic low voltage of the output signal Sout. With this configuration, the amplitude of the drive signal Sd becomes greater than the amplitude of the output signal Sout, and overshoot OSH and undershoot USH occur in the output signal Sout. Furthermore, in this case, the rise time Tr and fall time Tf of the output signal Sout can be significantly shortened.

[0112] Although not shown, the third power supply voltage Vdd_dum can be made higher than the logic high voltage of the output signal Sout, and the fourth power supply voltage Vss_dum can be set higher than the logic low voltage of the output signal Sout. In this case, the output signal Sout has overshoot OSH but not undershoot USH.

[0113] Furthermore, the third power supply voltage Vdd_dum can be set below the logic high voltage of the output signal Sout, and the fourth power supply voltage Vss_dum can be set below the logic low voltage of the output signal Sout. In this case, the output signal Sout does not have overshoot OSH, but rather undershoot USH.

[0114] Furthermore, according to this disclosure, the magnitudes of the third power supply voltage Vdd_dum and the fourth power supply voltage Vss_dum can be adjusted by controlling the magnitudes of overshoot and undershoot. As described above, in the drive circuit 10 according to the fourth embodiment, the third power supply voltage Vdd_dum and the fourth power supply voltage Vss_dum can be adjusted in a way that corrects the waveform of the output signal Sout.

[0115] (Fifth Embodiment)

[0116] Figure 14 This is a timing diagram illustrating an operational example of the drive circuit according to the fifth embodiment. In the fifth embodiment, the waveform of the output signal Sout is corrected by changing the rise and fall timings of the drive signal Sd.

[0117] For example, such as Figure 14 As shown, the rise and fall timings of the drive signal Sd are advanced by Δt. Using this configuration, the rise time Tr and fall time Tf of the output signal Sout can be further shortened. The rise timing of the output signal Sout can be adjusted to match t1 and t3, and the fall timing of the output signal Sout can be adjusted to match t2 and t4.

[0118] In the fifth embodiment, for example, the waveform of the output signal Sout can be corrected by changing the rise and fall timing of the drive signal Sd.

[0119] The fourth and fifth embodiments can be applied to any of the first to third embodiments and the first to fifth modifications described above.

[0120] It should be noted that this disclosure is not limited to the embodiments described above, and modifications can be made in various ways within the scope of this disclosure. Furthermore, the effects described herein are illustrative only and not intended to be limiting, and other effects may be obtained.

[0121] This technology may also have the following configurations.

[0122] (1) A driving circuit, comprising:

[0123] A first driver is disposed on a substrate, receives a first power supply voltage and a second power supply voltage, and outputs the first power supply voltage or the second power supply voltage as a first signal according to the input signal;

[0124] A resistive element is connected to the output of the first driver;

[0125] A first pad is connected to the first driver via the resistive element and outputs the first signal from the first driver as an output signal via the resistive element; and

[0126] The second pad is located near the first pad and is driven by a drive signal based on the input signal.

[0127] (2) The driving circuit according to (1) further includes a second driver, which is disposed on the substrate, receives a third power supply voltage and a fourth power supply voltage, and outputs the third voltage or the fourth voltage to the second pad according to the input signal.

[0128] (3) According to the driving circuit of (1), the output of the first driver is connected to both the first pad and the second pad.

[0129] (4) The driving circuit according to any one of (1) to (3), wherein the second pad is disposed between the first pad and the substrate.

[0130] (5) The driving circuit according to any one of (1) to (4) further comprises:

[0131] Through electrode penetrating the substrate.

[0132] The first pad is disposed on the through electrode in a manner that contacts the through electrode, and

[0133] The second pad is positioned above the first pad.

[0134] (6) The driving circuit according to any one of (1) to (5), wherein the first pad includes a plurality of first conductor layers stacked on the substrate.

[0135] (7) The driving circuit according to any one of (1) to (6) further includes a second conductor layer disposed on the outer periphery of the first pad, electrically isolated from the first pad, and electrically connected to the second pad.

[0136] (8) The driving circuit according to (6) further includes a plurality of second conductor layers disposed on the respective outer peripheries of the plurality of first conductor layers, electrically isolated from the plurality of first conductor layers, and electrically connected to the second pad.

[0137] (9) According to the driving circuit of (8), each of the plurality of second conductor layers is disposed in the same layer as the corresponding one of the plurality of first conductor layers.

[0138] (10) The driving circuit according to any one of (1) to (9), wherein the driving signal is in phase with the first signal.

[0139] (11) According to the driving circuit of (2), where,

[0140] The third power supply voltage and the fourth power supply voltage are between the first power supply voltage and the second power supply voltage, and

[0141] The difference between the third power supply voltage and the fourth power supply voltage is less than the difference between the first power supply voltage and the second power supply voltage.

[0142] (12) According to the driving circuit of (11), the difference between the third power supply voltage and the fourth power supply voltage is substantially half of the difference between the first power supply voltage and the second power supply voltage.

[0143] (13) The driving circuit according to any one of (2) and (4) to (11), wherein the third power supply voltage and the fourth power supply voltage are adjusted in a manner that corrects the waveform of the output signal.

[0144] (14) The driving circuit according to any one of (1), (2) and (4) to (11), wherein the rise timing or fall timing of the driving signal is adjusted in a manner that corrects the waveform of the output signal.

[0145] (15) The driving circuit according to any one of (1) to (14) further includes an ESD protection circuit disposed between the substrate and the node between the resistive element and the first pad.

Claims

1. A driving circuit, comprising: A first driver is disposed on a substrate, receives a first power supply voltage and a second power supply voltage, and outputs the first power supply voltage or the second power supply voltage as a first signal according to the input signal; A resistive element is connected to the output of the first driver; The first pad is connected to the first driver via the resistor element and outputs the first signal from the first driver as an output signal via the resistor element; as well as A second pad is disposed near the first pad and driven by a drive signal based on the input signal and capacitively coupled to the first pad, wherein the drive signal is a co-directional signal synchronized with the first signal, and wherein the drive signal drives the output signal through capacitive coupling, such that the second pad is charged and discharged synchronously with the output signal by the drive signal to reduce the rise time or fall time of the output signal.

2. The driving circuit according to claim 1, further comprising: The second driver, disposed on the substrate, receives a third power supply voltage and a fourth power supply voltage, and outputs the third power supply voltage or the fourth power supply voltage to the second pad according to the input signal.

3. The driving circuit according to claim 1, wherein, The output of the first driver is connected to both the first pad and the second pad.

4. The driving circuit according to claim 1, wherein, The second pad is disposed between the first pad and the substrate.

5. The driving circuit according to claim 1, further comprising: Through electrode penetrating the substrate. The first pad is disposed on the through electrode in a manner that contacts the through electrode, and The second pad is positioned above the first pad.

6. The driving circuit according to claim 1, wherein, The first pad includes a plurality of first conductor layers stacked on the substrate.

7. The driving circuit according to claim 1, further comprising: A second conductor layer is disposed on the outer periphery of the first pad, electrically isolated from the first pad, and electrically connected to the second pad.

8. The driving circuit according to claim 6, further comprising: A plurality of second conductor layers are disposed on the respective outer peripheries of the plurality of first conductor layers, electrically isolated from the plurality of first conductor layers, and electrically connected to the second pads.

9. The driving circuit according to claim 8, wherein, Each of the plurality of second conductor layers is disposed in the same layer as a corresponding one of the plurality of first conductor layers.

10. The driving circuit according to claim 1, wherein, The driving signal is in phase with the first signal.

11. The driving circuit according to claim 2, wherein, The third power supply voltage and the fourth power supply voltage are between the first power supply voltage and the second power supply voltage, and The difference between the third power supply voltage and the fourth power supply voltage is less than the difference between the first power supply voltage and the second power supply voltage.

12. The driving circuit according to claim 11, wherein, The difference between the third power supply voltage and the fourth power supply voltage is half the difference between the first power supply voltage and the second power supply voltage.

13. The driving circuit according to claim 2, wherein, The third power supply voltage and the fourth power supply voltage are adjusted in a manner that corrects the waveform of the output signal.

14. The driving circuit according to claim 1, wherein, The rise timing or fall timing of the drive signal is adjusted in a manner that corrects the waveform of the output signal.

15. The driving circuit according to claim 1, further comprising: An ESD protection circuit is disposed between the substrate and the node between the resistive element and the first pad.

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