Preparation method of gallium oxide schottky diode and gallium oxide schottky diode

Abstract

The application provides a gallium oxide Schottky diode preparation method and a gallium oxide Schottky diode. The method comprises the following steps: epitaxially growing an n-type gallium oxide channel layer on the upper surface of a substrate; preparing a mask layer on the gallium oxide channel layer; performing etching treatment on a first preset region of the mask layer to expose the gallium oxide channel layer; performing annealing treatment on the exposed gallium oxide channel layer at multiple preset temperatures in an oxygen atmosphere to obtain an oxide layer; preparing a first photolithography pattern on the oxide layer; growing a P-type dielectric layer on the first photolithography pattern and removing the mask layer; preparing a cathode electrode on the lower surface of the substrate and preparing an anode electrode on the side of the P-type dielectric layer and the gallium oxide channel layer away from the substrate; and preparing the gallium oxide Schottky diode through the method of first thermal oxidation and then P-type dielectric deposition, so that the diode can inject stable P-type dielectric, effectively inhibit the inrush current of a high-power device, and increase the breakdown voltage and reliability of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor device manufacturing, and particularly relates to a gallium oxide Schottky diode preparation method and a gallium oxide Schottky diode. BACKGROUND

[0002] Surge current is an important reason affecting the performance and reliability of power semiconductor devices.

[0003] In the prior art, silicon and silicon carbide Schottky diodes generally adopt ion implantation of P-type impurities to form an MPS structure (Merged PiN Schottky Diode) to inhibit surge current and improve device performance and reliability. However, since a gallium oxide Schottky diode does not have stable P-type impurities, it is difficult to reduce surge current and has low reliability. SUMMARY

[0004] Therefore, the application provides a gallium oxide Schottky diode preparation method and a gallium oxide Schottky diode, aiming to solve the problem of low reliability of the prior art gallium oxide Schottky diode.

[0005] A first aspect of the embodiment of the application provides a gallium oxide Schottky diode preparation method, comprising:

[0006] Epitaxially growing an n-type gallium oxide channel layer on an upper surface of a substrate;

[0007] Preparing a mask layer on the gallium oxide channel layer;

[0008] Performing etching treatment on a first preset region of the mask layer to expose the gallium oxide channel layer;

[0009] Performing annealing treatment on the exposed gallium oxide channel layer at a plurality of preset temperatures in an oxygen atmosphere to obtain an oxidation layer;

[0010] Preparing a first photolithography pattern on the oxidation layer;

[0011] Growing a P-type dielectric layer on the first photolithography pattern and removing the mask layer;

[0012] Preparing a cathode electrode on a lower surface of the substrate and preparing an anode electrode on a side of the P-type dielectric layer and the gallium oxide channel layer away from the substrate.

[0013] In some possible implementation manners, the mask layer comprises a first dielectric mask layer; and the etching treatment on the first preset region of the mask layer to expose the gallium oxide channel layer comprises:

[0014] Performing etching treatment on a first preset region of the first dielectric mask layer to expose the gallium oxide channel layer.

[0015] In some possible implementation manners, the mask layer comprises a second dielectric mask layer and a metal mask layer; and the method of manufacturing the mask layer on the gallium oxide channel layer comprises:

[0016] manufacturing a second dielectric mask layer on the gallium oxide channel layer;

[0017] manufacturing a second photoetching pattern on the second dielectric mask layer except for a first preset area;

[0018] manufacturing the metal mask layer on the second photoetching pattern;

[0019] the etching treatment on the first preset area of the mask layer comprises:

[0020] the etching treatment on the first preset area of the second dielectric mask layer.

[0021] In some possible implementation manners, after the etching treatment on the first preset area of the second dielectric mask layer exposes the gallium oxide channel layer, the method further comprises:

[0022] performing the etching treatment on the exposed gallium oxide channel layer to a preset depth to form a groove;

[0023] the annealing treatment on the exposed gallium oxide channel layer at a plurality of preset temperatures comprises:

[0024] the annealing treatment on the gallium oxide channel layer at the bottom of the groove at a plurality of preset temperatures.

[0025] In some possible implementation manners, the region where the mask layer is located comprises a W region and two S regions; the two S regions are symmetrically arranged on two sides of the W region, and the W region is also symmetric about the symmetry line of the two S regions;

[0026] before the etching treatment on the first preset area of the mask layer, the method further comprises:

[0027] selecting a plurality of second preset areas in the two S regions according to a preset interval and a preset size;

[0028] setting the plurality of second preset areas and the W region as the first preset area.

[0029] In some possible implementation manners, the preset temperature is between 200°C and 900°C;

[0030] the annealing treatment time at each preset temperature is between 10 seconds and 10 minutes.

[0031] In some possible implementation manners, the etching treatment is dry etching and / or wet etching.

[0032] In some possible implementation manners, the gallium oxide channel layer is an n-type gallium oxide channel layer; and the doping concentration is between 1.0*10 15 cm -3 and 1.0*10 20 cm -3 .

[0033] In some possible implementation manners, the thickness of the gallium oxide channel layer is between 10 nm and 1000 nm; and the thickness of the mask layer is between 50 nm and 3000 nm.

[0034] The second aspect of the embodiment of the present application provides a gallium oxide Schottky diode, which is prepared by the gallium oxide Schottky diode preparation method as described in the first aspect.

[0035] The gallium oxide Schottky diode preparation method and the gallium oxide Schottky diode provided by the embodiment of the present application include the following steps: epitaxially growing an n-type gallium oxide channel layer on an upper surface of a substrate; preparing a mask layer on the gallium oxide channel layer; performing etching treatment on a first preset region of the mask layer to expose the gallium oxide channel layer; performing annealing treatment on the exposed gallium oxide channel layer at a plurality of preset temperatures in an oxygen atmosphere to obtain an oxidation layer; preparing a first photolithography pattern on the oxidation layer; growing a P-type dielectric layer on the first photolithography pattern, and removing the mask layer; preparing a cathode electrode on a lower surface of the substrate and a anode electrode on a side of the P-type dielectric layer and the gallium oxide channel layer away from the substrate, and preparing the gallium oxide Schottky diode by the method of first thermal oxidation and then deposition of the P-type dielectric layer, so that the diode can inject stable P-type dielectric, effectively suppress the inrush current of a high-power device, and increase the breakdown voltage and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative labor.

[0037] Figure 1 is the implementation flowchart of the gallium oxide Schottky diode preparation method provided by the embodiment of the present application;

[0038] Figure 2 is the size schematic diagram of the gallium oxide Schottky diode provided by the embodiment of the present application;

[0039] Figure 3 is the implementation flowchart of the gallium oxide Schottky diode preparation method provided by the embodiment of the present application;

[0040] Figure 4 is a flow chart of a method for preparing a gallium oxide Schottky diode according to another embodiment of the present application;

[0041] Figure 5 is a structural schematic diagram of a gallium oxide Schottky diode according to an embodiment of the present application;

[0042] Figure 6 is a structural schematic diagram of a gallium oxide Schottky diode according to another embodiment of the present application. DETAILED DESCRIPTION

[0043] In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular sequences of steps, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, and circuits are omitted so as not to obscure the description of the present application with unnecessary detail.

[0044] Power electronic devices are mainly used for power conversion and circuit control of power equipment, and are the core devices for power processing. Silicon-based semiconductor devices are the most commonly used power devices in the current power system, and their performance has been quite perfect and close to the theoretical limit determined by their material properties, making the growth of their power density saturated.

[0045] In recent years, super-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices, and are expected to replace traditional Si-based power devices in certain specific fields. As a new semiconductor material, super-wide bandgap gallium oxide has outstanding advantages in breakdown field strength, Baliga figure of merit, and cost. The Baliga figure of merit (Eb3) is commonly used internationally to represent the degree to which a material is suitable for a power device. The Baliga figure of merit of β-Ga2O3 material is 4 times that of GaN material, 10 times that of SiC material, and 3444 times that of Si material. Under the same voltage resistance as GaN and SiC devices, β-Ga2O3 power devices have lower on-resistance, smaller power consumption, and can greatly reduce the electrical energy loss during device operation.

[0046] Inrush current refers to the peak current flowing into a power supply device at the moment of power-on. Inrush current in silicon and Schottky high-power diodes is a significant factor affecting device performance and reliability. Silicon and silicon carbide Schottky diodes typically employ ion implantation of P-type impurities to form an MPS (Merged PiN Schottky Diode) structure to suppress inrush current and improve device performance and reliability. However, gallium oxide Schottky diodes, lacking stable P-type impurities, present a significant challenge in reducing inrush current.

[0047] This invention proposes a method for fabricating MPS structure gallium oxide Schottky diodes by thermal oxidation and deposition of P-type dielectric, which suppresses surge current in high-power devices and can effectively increase device breakdown voltage and reliability.

[0048] Figure 1 This is a flowchart illustrating the implementation of the gallium oxide Schottky diode fabrication method provided in this embodiment of the invention. Figure 1 As shown, in some embodiments, the method for fabricating a gallium oxide Schottky diode includes:

[0049] S101, an n-type gallium oxide channel layer is epitaxially grown on the upper surface of the substrate.

[0050] In this embodiment, the substrate can be a high-resistivity gallium oxide substrate, or a semi-insulating SiC (silicon carbide) substrate, magnesium oxide substrate, sapphire substrate, etc., and is not limited thereto. An undoped gallium oxide layer is also grown between the n-type gallium oxide channel layer and the substrate. The epitaxial growth of the n-type gallium oxide channel layer can be achieved by doping with Si or Sn, etc.

[0051] S102, a mask layer is prepared on the gallium oxide channel layer.

[0052] In this embodiment, the mask layer can be a dielectric mask layer or a metal mask layer, and is not limited thereto. The prepared mask layer can be a single layer or multiple layers, and is not limited thereto. The preparation method can be chemical vapor deposition, evaporation, sputtering, etc., and is not limited thereto.

[0053] S103, etch the first preset area of ​​the mask layer to expose the gallium oxide channel layer.

[0054] In this embodiment, the first preset area is the area where P-type medium needs to be injected.

[0055] S104, in an oxygen atmosphere, the exposed gallium oxide channel layer is annealed at multiple preset temperatures to obtain an oxide layer.

[0056] In this embodiment, a method of annealing at low temperature followed by high temperature can be used, or a method of annealing at high temperature followed by low temperature can be used to form a low concentration area in the exposed area, and the concentration decreases sequentially from the in vivo to the surface.

[0057] S105, preparing a first photoetching pattern on the oxidation layer.

[0058] S106, growing a P-type dielectric layer on the first photoetching pattern, and removing the mask layer.

[0059] In the embodiment, the method for growing the P-type dielectric layer can be magnetron sputtering, electron beam evaporation metal high-temperature oxidation, atomic layer deposition (ALD), pulsed laser deposition (PLD), etc., which are not limited herein. The P-type dielectric can include, but is not limited to, at least one of NiO, CuMO2, Cu2O, SnO, ZnM2O4, CuAlO2, Mn2O3, Mn3O4, Fe2O3, Fe3O4, CoO, Cr2O3. The way of removing the mask layer can be dry etching or wet etching, which are not limited herein. In the embodiment, the oxidation layer can be grown first, and then the mask layer is removed; or the mask layer can be removed first, and then the oxidation layer is grown. The order of the two steps does not affect the preparation process, which is not limited herein.

[0060] S107, preparing a cathode electrode on the lower surface of the substrate and preparing an anode electrode on the side of the P-type dielectric layer and the gallium oxide channel layer away from the substrate.

[0061] In the embodiment, the cathode electrode can be a rapid thermal annealing alloy to form an ohmic contact resistance, and the alloy can be Ti / Au or Ti / Pt / Au. The anode electrode can be a rapid thermal annealing alloy, and the alloy can be Ni / Au, Ni / Al, Ni / Cu, Pt / Au, Pt / Al or Ni / Pt / Au.

[0062] In the embodiment, the method for preparing the gallium oxide Schottky diode includes epitaxially growing an n-type gallium oxide channel layer on the upper surface of the substrate; preparing a mask layer on the gallium oxide channel layer; performing etching treatment on a first preset area of the mask layer to expose the gallium oxide channel layer; performing annealing treatment on the exposed gallium oxide channel layer at a plurality of preset temperatures in an oxygen atmosphere to obtain an oxidation layer; preparing a first photoetching pattern on the oxidation layer; growing a P-type dielectric layer on the first photoetching pattern, and removing the mask layer; preparing a cathode electrode on the lower surface of the substrate and preparing an anode electrode on the side of the P-type dielectric layer and the gallium oxide channel layer away from the substrate. The method for preparing the gallium oxide Schottky diode by first thermal oxidation and then depositing the P-type dielectric can inject a stable P-type dielectric into the diode, effectively suppress the inrush current of a high-power device, and increase the breakdown voltage and reliability of the device.

[0063] In some embodiments, the mask layer includes a first dielectric mask layer.

[0064] S103 can include:

[0065] The first preset region of the first dielectric mask layer is etched to expose the gallium oxide channel layer.

[0066] In the embodiment, the first dielectric mask layer can be SiO2 or SiN, and can be prepared by PECVD (plasma enhanced chemical vapor deposition) or sputtering.

[0067] In some embodiments, the mask layer includes a second dielectric mask layer and a metal mask layer.

[0068] S102 can include:

[0069] The second dielectric mask layer is prepared on the gallium oxide channel layer;

[0070] The second lithography pattern is prepared on the region of the second dielectric mask layer except the first preset region;

[0071] The metal mask layer is prepared on the second lithography pattern;

[0072] S103 can include:

[0073] The first preset region of the second dielectric mask layer is etched.

[0074] In the embodiment, the second dielectric mask layer can be SiO2 or SiN, and can be prepared by PECVD or sputtering. The metal mask layer can be metal such as Ni, or alloy such as Ti / Ni, which is not limited herein. The second lithography pattern is prepared by photolithography on the first mask layer, and then evaporated and peeled to form the metal mask layer.

[0075] In some embodiments, after the first preset region of the second dielectric mask layer is etched to expose the gallium oxide channel layer, the method further includes:

[0076] The exposed gallium oxide channel layer is etched to a preset depth to form a groove;

[0077] The exposed gallium oxide channel layer is annealed at a plurality of preset temperatures, including:

[0078] The gallium oxide channel layer at the bottom of the groove is annealed at a plurality of preset temperatures.

[0079] In the embodiment, the second dielectric mask layer and the N-low-concentration gallium oxide epitaxial layer of a preset thickness which are not covered by the metal mask layer can be dry etched to form a groove on the N-low-concentration gallium oxide epitaxial layer. Then the metal mask layer is removed, the groove is wet processed to repair etching damage, and the groove is thermally oxidized and deposited with a P-type dielectric layer.

[0080] In the embodiment, under the action of the second dielectric mask and the metal mask, on the one hand, the second dielectric mask and the P-type dielectric layer are etched and evaporated to be the same mask, the width and the interval of the P-type dielectric layer can be accurately controlled, and zero alignment error is achieved. On the other hand, after the groove is formed by dry etching, the groove is treated by wet etching by taking advantage of the characteristic that the dielectric mask is not corroded by the wet etching liquid, the damage caused by the dry etching is repaired, and the heterostructure evaporation separation mask is not damaged, so that the effect of improving the breakdown voltage and accurate alignment is achieved.

[0081] Figure 2 is a size schematic diagram of a gallium oxide Schottky diode provided by the embodiment of the present application. As shown in Figure 2 , in some embodiments, the region where the mask layer is located includes a W region and two S regions; the two S regions are symmetrically arranged on the two sides of the W region, and the W region is also symmetric about the symmetry line of the two S regions;

[0082] Before the etching treatment of the first preset region of the mask layer, the method further includes:

[0083] A plurality of second preset regions are selected in the two S regions respectively according to a preset interval and a preset size;

[0084] The plurality of second preset regions and the W region are set as the first preset region.

[0085] Since the gallium oxide Schottky diode is a symmetric structure, therefore Figure 2 only the structure of one side of the symmetry line is shown in

[0086] In the embodiment, the S region has a plurality of JBS (Junction barrier Schottky, junction barrier Schottky) regions, the size of the W region is 5-50 um (i.e. Figure 2 W / 2 in is (5-50) / 2 um), the size of the JBS region S is 10-50 um (i.e. Figure 2 S / 2 in is (10-50) / 2 um), the size P of P+ (i.e. the first preset region) in each JBS region ranges from 0.1 um to 5 um, and the interval N of the P+ region in the JBS region ranges from 0.1 um to 5 um. The size of the JBS region, the PiN region, the P-type dielectric region in the JBS, and the interval of the P-type dielectric region in the JBS has an influence on the breakdown voltage, the on-resistance, and other device characteristics and reliability performance of the device.

[0087] In some embodiments, the preset temperature is between 200℃ and 900℃;

[0088] The annealing treatment time at each preset temperature is between 10 seconds and 10 minutes.

[0089] In this embodiment, the low-temperature annealing followed by high-temperature annealing can be used, or the high-temperature annealing followed by low-temperature annealing can be used, to form a low-concentration region in the exposed region, and the concentration decreases from the bulk to the surface.

[0090] In some embodiments, the etching process is dry etching and / or wet etching.

[0091] In some embodiments, the gallium oxide channel layer is an n-type gallium oxide channel layer, and the doping concentration is between 1.0*10 15 cm -3 and 1.0*10 20 cm -3 .

[0092] In some embodiments, the thickness of the gallium oxide channel layer is between 10 nm and 1000 nm, and the thickness of the mask layer is between 50 nm and 3000 nm.

[0093] The preparation method of the gallium oxide Schottky diode of the present application will be described below by means of several implementation examples, but is not limited thereto.

[0094] Figure 3 is the implementation flowchart of the preparation method of the gallium oxide Schottky diode provided by the implementation example of the present application. As shown in the figure, in this implementation example, the steps of the preparation method of the gallium oxide Schottky diode are as follows: Figure 3

[0095] Step a: epitaxially growing an n-type gallium oxide channel layer 31 on a substrate 32.

[0096] Step b: growing a SiO2 dielectric layer (i.e., a first dielectric mask layer 33) on the surface of the sample, and using dry / wet etching to etch the oxidation region (i.e., a first preset region).

[0097] Step c: after cleaning the sample, performing high-temperature annealing treatment on the sample in an oxygen atmosphere at different temperatures, with the temperature range being 200-900°C and the time range being 10 seconds-10 minutes.

[0098] Step d: removing the SiO2 dielectric layer by wet etching, preparing a first photoetching pattern on the oxide layer 34, and growing a P-type dielectric layer on the pattern.

[0099] Step e: preparing a cathode electrode 36 and an anode electrode 37.

[0100] Figure 4 is the implementation flowchart of the preparation method of the gallium oxide Schottky diode provided by another implementation example of the present application. As shown in the figure, in this implementation example, the steps of the preparation method of the gallium oxide Schottky diode are as follows: Figure 4

[0101] ​​Step A: epitaxially growing n-type gallium oxide channel layer 31 on substrate 32.

[0102] Step B: preparing metal mask layer 41 by photolithography of second dielectric mask layer 42 deposited on n-low concentration gallium oxide epitaxial layer.

[0103] Step C: dry etching second dielectric mask layer 42 and N-low concentration gallium oxide epitaxial layer of a preset thickness to form a groove on the N-low concentration gallium oxide epitaxial layer, wet processing the groove to repair etching damage, and then thermally oxidizing and depositing oxide layer 34 on the groove. In this step, the wet processing liquid for repairing etching damage is concentrated sulfuric acid, hydrogen peroxide, or alkaline liquid.

[0104] Step D: wet removing metal mask layer 41. In this step, the wet processing liquid for removing metal mask is FeCl3 or hydrochloric acid. The sample is placed in an oxygen atmosphere for high-temperature annealing treatment at different temperatures ranging from 200 to 900 °C for 10 seconds to 10 minutes.

[0105] Step E: preparing first photolithography pattern on oxide layer 34 and growing P-type dielectric on the pattern.

[0106] Step F: removing dielectric mask layer by wet method, removing part of P-type dielectric on the dielectric mask layer, and preparing cathode electrode 36 and anode electrode 37. In this step, the wet processing liquid is BOE (Buffered Oxide Etch) or hydrochloric acid.

[0107] The beneficial effects of the present application are as follows:

[0108] The present application designs a MPS (Merged PiN Schottky Diodes) structure gallium oxide Schottky diode. The MPS structure gallium oxide Schottky diode is prepared by the method of thermal oxidation and deposition of P-type dielectric, which suppresses the inrush current of high-power devices and increases the breakdown voltage and reliability of the device.

[0109] The oxide layer of the present application can reduce the electron concentration of the surface drift region, form a lateral concentration difference below the anode junction, reduce the peak electric field at the anode junction, and improve the breakdown voltage, while also considering low on-resistance.

[0110] The present application can improve the breakdown voltage of the device and maintain a small on-resistance by preparing P-type dielectric layers and MPS type P-type dielectric layers arranged at intervals in the n-low concentration gallium oxide epitaxial layer or the dry etched groove.

[0111] It should be understood that the size of the serial number of each step in the above embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the application.

[0112] In some embodiments, the gallium oxide Schottky diode is prepared by the gallium oxide Schottky diode preparation method shown in any one of the above embodiments.

[0113] Figure 5 is a structural schematic diagram of the gallium oxide Schottky diode provided by the embodiments of the application. Figure 6 is a structural schematic diagram of the gallium oxide Schottky diode provided by another embodiment of the application. As shown in Figure 5 and Figure 6 In some embodiments, the gallium oxide Schottky diode is sequentially arranged from top to bottom as the cathode electrode 36, the substrate 32, the gallium oxide channel layer 31, the oxide layer 34, the P-type dielectric layer 35, and the anode electrode 37.

[0114] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be realized in the form of hardware or software function unit. In addition, the specific name of each functional unit and module is only for easy distinction, and does not limit the protection scope of the application. The specific working process of the unit and module in the above-mentioned system can be referred to the corresponding process in the foregoing method embodiments, which will not be described here.

[0115] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0116] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application.

[0117] In the embodiments of the present application, it should be understood that the disclosed apparatus / terminal and method can be implemented in other manners. For example, the apparatus / terminal embodiments described above are merely schematic, and the division of the modules or units can be different, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0118] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments.

[0119] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can be a physically independent unit, or two or more units can be integrated into a unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0120] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, all or part of the flow of the above-mentioned embodiment methods can be implemented by a computer program instructing related hardware to complete, and the computer program can be stored in a computer readable storage medium, and when the processor executes the computer program, the steps of each method embodiment described above can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable file or some intermediate form. The computer readable medium can include any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal and software distribution medium, etc.

[0121] The above examples are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing examples, those ordinarily skilled in the art should understand: the technical solutions recorded in the foregoing examples can still be modified, or some technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for fabricating a gallium oxide Schottky diode, characterized in that, The method comprises the following steps: epitaxially growing an n-type gallium oxide channel layer on an upper surface of a substrate; preparing a mask layer on the gallium oxide channel layer; performing etching treatment on a first preset region of the mask layer to expose the gallium oxide channel layer; performing annealing treatment on the exposed gallium oxide channel layer at multiple preset temperatures in an oxygen atmosphere to obtain an oxide layer; the preset temperature is between 200 DEG C and 900 DEG C; the concentration of the exposed region of the oxide layer decreases from the inside to the surface; preparing a first photolithography pattern on the oxide layer; growing a P-type dielectric layer on the first photolithography pattern and removing the mask layer; preparing a cathode electrode on a lower surface of the substrate and preparing an anode electrode on a side of the P-type dielectric layer and the gallium oxide channel layer away from the substrate; the mask layer comprises a first dielectric mask layer; the etching treatment on the first preset region of the mask layer to expose the gallium oxide channel layer comprises: the etching treatment on the first preset region of the first dielectric mask layer to expose the gallium oxide channel layer.

2. A method of fabricating a gallium oxide Schottky diode, comprising: The method comprises the following steps: epitaxially growing an n-type gallium oxide channel layer on an upper surface of a substrate; preparing a mask layer on the gallium oxide channel layer; performing etching treatment on a first preset region of the mask layer to expose the gallium oxide channel layer; performing annealing treatment on the exposed gallium oxide channel layer at multiple preset temperatures in an oxygen atmosphere to obtain an oxide layer; the preset temperature is between 200 DEG C and 900 DEG C; the concentration of the exposed region of the oxide layer decreases from the inside to the surface; preparing a first photolithography pattern on the oxide layer; growing a P-type dielectric layer on the first photolithography pattern and removing the mask layer; preparing a cathode electrode on a lower surface of the substrate and preparing an anode electrode on a side of the P-type dielectric layer and the gallium oxide channel layer away from the substrate; the mask layer comprises a second dielectric mask layer and a metal mask layer; the step of preparing the mask layer on the gallium oxide channel layer comprises: preparing a second dielectric mask layer on the gallium oxide channel layer; preparing a second photolithography pattern on a region of the second dielectric mask layer except the first preset region; preparing the metal mask layer on the second photolithography pattern; the etching treatment on the first preset region of the mask layer comprises: performing etching treatment on the first preset region of the second dielectric mask layer; after the etching treatment on the first preset region of the second dielectric mask layer to expose the gallium oxide channel layer, the method further comprises: performing etching treatment on the exposed gallium oxide channel layer to a preset depth to form a groove; the annealing treatment on the exposed gallium oxide channel layer at multiple preset temperatures comprises: performing annealing treatment on the gallium oxide channel layer at the bottom of the groove at multiple preset temperatures.

3. The method of claim 1 or 2, wherein the gallium oxide Schottky diode is prepared by the steps of: forming a gallium oxide layer on a substrate; forming a metal layer on the gallium oxide layer; and forming a metal oxide layer on the metal layer. the region where the mask layer is located comprises a W region and two S regions; the two S regions are symmetrically arranged on two sides of the W region, and the W region is also symmetric about the symmetry line of the two S regions; before the etching treatment on the first preset region of the mask layer, the method further comprises: selecting multiple second preset regions in the two S regions according to a preset interval and a preset size respectively; The second preset regions and the W region are set as the first preset region.

4. The method of claim 1 or 2, wherein the gallium oxide Schottky diode is prepared by the steps of: forming a gallium oxide layer on a substrate; forming a metal layer on the gallium oxide layer; and forming a metal layer on the gallium oxide layer. The annealing treatment time at each preset temperature is between 10 seconds and 10 minutes.

5. The method of claim 1 or 2, wherein the gallium oxide Schottky diode is prepared by the steps of: forming a gallium oxide layer on a substrate; forming a metal layer on the gallium oxide layer; and forming a metal oxide layer on the metal layer. The etching treatment is dry etching and / or wet etching.

6. The method of claim 1 or 2, wherein the gallium oxide Schottky diode is prepared by the steps of: forming a gallium oxide layer on a substrate; forming a metal layer on the gallium oxide layer; and forming a metal oxide layer on the metal layer. The gallium oxide channel layer is an n-type gallium oxide channel layer; the doping concentration is between 1.0×10 15 cm -3 and 1.0×10 20 cm -3 .

7. The method of claim 6, wherein the gallium oxide Schottky diode is prepared by the steps of: forming a gallium oxide layer on a substrate; forming a metal layer on the gallium oxide layer; and forming a metal oxide layer on the metal layer. The thickness of the gallium oxide channel layer is between 10 nm and 1000 nm; and the thickness of the mask layer is between 50 nm and 3000 nm.

8. A gallium oxide Schottky diode, characterized by, The gallium oxide Schottky diode is prepared by the method of any one of claims 1-7.

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