A novel packaging structure and its manufacturing method

Abstract

This invention relates to a novel packaging structure and its manufacturing method, comprising a chip, the outer surface of which is covered by an outer packaging layer. The outer packaging layer includes a top packaging layer disposed on the top surface of the chip and a side packaging layer disposed on the side surface of the chip. The key feature is that the bottom surface of the side packaging layer is higher than the bottom surface of the chip. The advantage of this invention is that, since the bottom surface of the side packaging layer located on the side surface of the chip is 2μm higher than the bottom surface of the chip, during chip soldering, the molten solder paste can better bond the substrate and the chip because there is no other material around the bottom surface of the chip. The push-pull force after soldering is not affected, and the chip is less likely to detach.

Description

Technical Field

[0001] This invention relates to an LED packaging structure, and more particularly to a novel packaging structure with high push-pull force after soldering, and also to a method for manufacturing the packaging structure. Background Technology

[0002] Chip-scale packaging (CSP) is a packaging method that has emerged in recent years based on the development of flip-chip technology, and commercial mass production began after 2015. For details on the development of packaging technology, please refer to: Wang Jietian, Current Status and Development of LED Packaging Technology [J], Science and Technology Innovation and Application, 2017(12):42.

[0003] CSP (Chip-on-Package) light sources refer to a type of LED device that uses CSP packaging technology. The core of CSP is that it uses phosphor or phosphor colloid film to encapsulate a flip-chip structure, eliminating most of the packaging steps and structures of traditional LED light sources, reducing the package size to 1 / 5 to 1 / 10 of the original. However, conventional CSP technology often involves dicing the wafer, sorting and rearranging the light-emitting chips, and then performing subsequent processes such as phosphor or phosphor colloid lamination and spraying. The bottom edge of the resulting CSP outer packaging layer is on the same plane as the bottom surface of the chip's electrodes. This packaging structure leads to a decrease in soldering push-pull force during subsequent CSP package mounting, severely affecting the operational reliability of the CSP packaged device. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a novel packaging structure with high push-pull force after welding, and also to provide a method for manufacturing the novel packaging structure.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: a novel packaging structure, including a chip, the outer surface of which is covered with an outer packaging layer, the outer packaging layer including a top packaging layer disposed on the top surface of the chip and a side packaging layer disposed on the side surface of the chip, the innovation of which is that the bottom surface of the side packaging layer on at least one side of the chip is 2μm higher than the bottom surface of the chip and not higher than half the height of the chip.

[0006] Preferably, the bottom surface of the chip is provided with an electrode that protrudes downwards from the bottom surface, and the bottom surface and side surface of the outer encapsulation layer as well as the bottom surface of the bottom surface and side surface of the chip are covered with a reflective layer, and the bottom center of the reflective layer has two electrode channels with exposed electrodes.

[0007] Preferably, a sacrificial layer is provided on the bottom periphery of the chip, which is closely attached to the chip sidewall, and the height of the sacrificial layer is not higher than half the height of the chip; the side encapsulation layer of the outer encapsulation layer is provided on the upper surface of the sacrificial layer.

[0008] Preferably, the thickness of the sacrificial layer gradually decreases from the center of the chip outwards.

[0009] A method for fabricating the above-mentioned novel packaging structure is also provided, the innovation of which lies in: the method is as follows:

[0010] S1: First, the wafer for chip fabrication is diced and split, and then expanded to split the wafer into several independent chips with a gap between adjacent chips.

[0011] S2: Then, the wafer is cast, and the chips are arranged at intervals on a substrate to form a chip array;

[0012] S3: Fill the gaps between adjacent chips in the chip array with a sacrificial layer that is close to the side of the chip by spraying, dispensing or printing, and then dry it. Control the thickness of the sacrificial layer after drying to be no less than 2μm and no more than half the height of the chip.

[0013] S4: Then, spray the entire chip array surface with encapsulation material, so that the encapsulation material fills the space between adjacent chips on the upper surface of the sacrificial layer and on the upper surface of the chips, and cure the encapsulation material to form an outer encapsulation layer.

[0014] S5: Perform the casting process again so that the surface of the outer packaging layer is attached to another substrate, exposing the sacrificial layer at the bottom of the chip array, and remove the sacrificial layer by chemical cleaning.

[0015] S6: The chip array is cut to obtain a package structure with an outer packaging layer covering the upper middle part and the top of the outer side wall of the chip.

[0016] Furthermore, the material of the sacrificial layer is silicone or polyimide.

[0017] Furthermore, the sacrificial layer is located on two sides of the chip, or on all four sides of the chip.

[0018] Furthermore, the manufacturing method also includes

[0019] S7: The bottom surface of the chip has downward protruding electrodes, and at least one chip is soldered onto the substrate as a chip unit, so that there is a filling gap between the bottom surface of the chip and the substrate and between the bottom surface of the outer packaging layer and the substrate.

[0020] S8: Fill the gaps and the outer periphery of the outer encapsulation layer with reflective material and cure it to obtain an encapsulation structure with a reflective layer.

[0021] The advantages of this invention are:

[0022] In conventional technologies, the bottom surface of the side encapsulation layer located on the side of the chip in the outer packaging layer is on the same plane as the bottom surface of the chip. This packaging structure causes the solder paste directly below the chip electrodes to be squeezed outwards to the bottom surface of the side encapsulation layer on the side of the chip during subsequent package mounting. This significantly reduces the soldering push-pull force of the chip package, lowering the reliability of the device. The technical solution of this invention, however, involves a side encapsulation layer on the side of the chip in the outer packaging layer that is higher than the bottom surface of the chip. During chip soldering, since there is no other material around the bottom surface of the chip, the molten solder paste can better bond the substrate and the chip, and the push-pull force after soldering is not affected, making the chip less prone to detachment. Furthermore, the manufacturing method using the packaging structure of this invention is simple, low-cost, and suitable for large-scale mass production. Attached Figure Description

[0023] Figure 1 This is a novel packaging structure according to Embodiment 1 of the present invention.

[0024] Figure 2 This is a novel packaging structure according to Embodiment 2 of the present invention.

[0025] Figure 3 This is a novel packaging structure according to Embodiment 3 of the present invention.

[0026] Figure 4 This is a schematic diagram of step S1 in embodiment four of the present invention.

[0027] Figure 5 This is a front view of step S3 of embodiment four of the present invention, which involves filling the sacrificial layer.

[0028] Figure 6 This is a top view schematic diagram of the first method of filling the sacrificial layer in Embodiment 4 of the present invention.

[0029] Figure 7 This is a top view schematic diagram of the second method of filling the sacrificial layer in Embodiment 4 of the present invention.

[0030] Figure 8 This is a schematic diagram of step S4 in Embodiment 4 of the present invention, showing the fabrication of the outer encapsulation layer.

[0031] Figure 9 This is a schematic diagram of step S5, removing the sacrificial layer, in Embodiment 4 of the present invention. Figure 1 .

[0032] Figure 10 This is a schematic diagram of step S5, removing the sacrificial layer, in Embodiment 4 of the present invention. Figure 2 .

[0033] Figure 11 This is a schematic diagram of step S6 cutting in Embodiment 4 of the present invention.

[0034] Figure 12 This is a schematic diagram of step S7 in Embodiment 5 of the present invention.

[0035] Figure 13 This is a schematic diagram of step S8 of embodiment five of the present invention, which involves filling the reflective material. Detailed Implementation

[0036] Example 1

[0037] like Figure 1 As shown, the novel packaging structure of the present invention includes a chip 1, which can be a conventional chip or a flip chip. An outer packaging layer 2 is covered on the outer surface of the chip 1. The outer packaging layer 2 includes a top packaging layer disposed on the top surface of the chip 1 and a side packaging layer disposed on the side surface of the chip. The bottom surface 2a of at least one side packaging layer is 2 μm higher than the bottom surface of the chip 1 and not higher than half the height of the chip 1.

[0038] The following is a comparison between the packaging structure in Embodiment 1 of this invention and a traditional packaging structure soldered onto the substrate:

[0039] Traditional CSP packaging structure: The chip dimensions are 760μm long, 330μm wide, and 150μm high. The top packaging layer of the outer packaging layer is 230μm thick, and the side packaging layer is 120μm thick.

[0040] Sample 1 of the present invention: The chip used has a length of 760μm, a width of 330μm, a height of 150μm, a top encapsulation layer thickness of 230μm, a side encapsulation layer thickness of 20μm, and the bottom surface 2a of the side encapsulation layer on all four sides of the chip is 2μm higher than the bottom surface of chip 1.

[0041] Sample 2 of the present invention: The chip used has a length of 760μm, a width of 330μm, a height of 150μm, a top encapsulation layer thickness of 230μm, a side encapsulation layer thickness of 120μm, and the bottom surface 2a of the side encapsulation layer on all four sides of the chip is 60μm higher than the bottom surface of chip 1.

[0042] Solder paste was selected as the solder.

[0043]

[0044] Example 2

[0045] Figure 2 Another structure of the packaging structure of the present invention is shown, which includes a chip 1. A sacrificial layer 3 is disposed on the bottom periphery of the chip 1, closely attached to the sidewall of the chip 1. The height of the sacrificial layer 3 is not higher than half the height of the chip, and the bottom surface of the sacrificial layer 3 is flush with or lower than the bottom surface of the chip 1. As a more specific implementation of this embodiment, the thickness of the sacrificial layer 3 is not limited to being uniform, and it can gradually decrease from the center of the chip 1 to the outside.

[0046] An outer encapsulation layer 2 covering the outer surface of chip 1 is provided on the upper surface of the sacrificial layer 3. The outer encapsulation layer 2 includes a top encapsulation layer provided on the top surface of chip 1 and a side encapsulation layer provided on the side surface of chip 1. The side encapsulation layer extends downward to the upper surface of the sacrificial layer.

[0047] Example 3

[0048] like Figure 3 As shown, in this embodiment, a chip 1 is included, and an outer packaging layer 2 is covered on the outer surface of the chip 1. The outer packaging layer 2 includes a top packaging layer disposed on the top surface of the chip 1 and a side packaging layer disposed on the side surface of the chip. The bottom surface 2a of the side packaging layer is not lower than the bottom surface of the chip 1 by 2μm and not higher than half the height of the chip 1.

[0049] In this embodiment, the bottom surface of chip 1 is provided with an electrode 4 protruding downwards. The bottom and side surfaces of the outer encapsulation layer 2, as well as the bottom surface of the chip and the bottom of its side surfaces, are all covered with a reflective layer 5. The bottom center of the reflective layer 5 has two electrode channels with exposed electrodes. The upper surface of the reflective layer is not higher than the upper surface of the outer encapsulation layer 2, and not lower than the bottom surface 2a of the side encapsulation layer.

[0050] Performance parameters of the packaging structure in Embodiment 3 of this invention compared with those of a traditional packaging structure:

[0051] Traditional CSP packaging structure: The chip dimensions are 760μm long, 330μm wide, and 150μm high. The top packaging layer of the outer packaging layer is 230μm thick, and the side packaging layer is 120μm thick.

[0052] Sample 4 of this invention: The chip used has a length of 760μm, a width of 330μm, a height of 150μm, a top encapsulation layer thickness of 230μm, and a side encapsulation layer thickness of 120μm. The bottom surface 2a of the side encapsulation layers on all four sides of the chip is 60μm higher than the bottom surface of chip 1. The height of the reflective layer 5 is flush with the upper surface of the chip.

[0053] Example 4

[0054] This embodiment discloses a method for fabricating a novel packaging structure according to the embodiment. The specific method is as follows:

[0055] S1: First, the wafer for fabricating chip 1 is diced and split, then film expansion is performed, such as... Figure 4 As shown, this causes the wafer to split into several independent chips 1, with a gap between adjacent chips 1.

[0056] S2: Then, the molding process is performed, and each chip 1 is arranged at intervals on a substrate to form a chip array;

[0057] S3: By spraying, dispensing, or printing, such as Figure 5 As shown, a sacrificial layer 3, which is close to the side of the chip, is filled in the gap between each adjacent chip 1 in the chip array and then dried. The thickness of the sacrificial layer after drying is controlled to be no less than 2μm and no more than half the height of the chip. In this embodiment, the material of the sacrificial layer 3 is silicone or polyimide.

[0058] It is important to emphasize that the sacrificial layer filling the gaps can be located on all four sides of the chip periphery, or only on two symmetrical sides of the chip, or even only on one side. See [link to relevant documentation]. Figure 6 , 7 .

[0059] S4: As Figure 8 As shown, encapsulation material is then sprayed onto the entire surface of the chip array, so that the encapsulation material fills the space between adjacent chips 1 on the upper surface of the sacrificial layer 3 and the upper surface of chip 1, and the encapsulation material is cured to form the outer encapsulation layer 2.

[0060] S5: As Figure 9 , 10 As shown, the film is flipped again so that the surface of the outer packaging layer 2 is attached to another substrate, exposing the sacrificial layer 3 at the bottom of the chip array, and the sacrificial layer 3 is removed by chemical cleaning.

[0061] S6: As Figure 11 As shown, the chip array is cut to obtain a package structure in which the upper middle part and top of the outer side wall of chip 1 are covered with an outer packaging layer 2. Since film expansion is required after cutting, it is necessary to perform film casting before or after cutting, which is a well-known technology in the field and will not be described in detail here.

[0062] Example 5

[0063] As a further implementation of the manufacturing method in Embodiment 4, when the packaging structure manufactured using the method in Embodiment 4 is applied, for example in an automotive headlight module, a chip structure with downwardly protruding electrodes on the bottom surface can be used, and after step S6, the following manufacturing process is performed:

[0064] S7: As Figure 12 As shown, several chips 1 with downward protruding electrode structures on the bottom surface are soldered onto the substrate 6 as chip units, so that there is a filling gap between the bottom surface of the chip 1 and the substrate 6 and between the bottom surface of the outer encapsulation layer 2 and the substrate 1.

[0065] S8: As Figure 13 As shown, reflective material is filled into the gaps and the outer periphery of the outer encapsulation layer 2, and then cured to obtain an overall encapsulation structure with a reflective layer 5.

Claims

1. A novel packaging structure, comprising a chip, wherein the outer surface of the chip is covered by an outer packaging layer, the outer packaging layer comprising a top packaging layer disposed on the top surface of the chip and a side packaging layer disposed on the side surface of the chip, characterized in that: The bottom surface of the side encapsulation layer on at least one side of the chip is 2 μm higher than the bottom surface of the chip, but not higher than half the height of the chip; the method for fabricating the novel encapsulation structure is as follows: S1: First, the wafer for chip fabrication is diced and split, and then expanded to split the wafer into several independent chips with a gap between adjacent chips. S2: Then, the wafer is cast, and the chips are arranged at intervals on a substrate to form a chip array; S3: Fill the gaps between adjacent chips in the chip array with a sacrificial layer that is close to the side of the chip by spraying, dispensing or printing, and then dry it. Control the thickness of the sacrificial layer after drying to be no less than 2μm and no more than half the height of the chip. S4: Then, spray the entire chip array surface with encapsulation material, so that the encapsulation material fills the space between adjacent chips on the upper surface of the sacrificial layer and on the upper surface of the chips, and cure the encapsulation material to form an outer encapsulation layer. S5: Perform the casting process again so that the surface of the outer packaging layer is attached to another substrate, exposing the sacrificial layer at the bottom of the chip array, and remove the sacrificial layer by chemical cleaning. S6: The chip array is cut to obtain a packaged structure with an outer packaging layer covering the upper middle part and top of the outer side wall of the chip. The packaged structure is then soldered to the substrate using solder.

2. The novel packaging structure according to claim 1, characterized in that: The sacrificial layer is made of silicone or polyimide.

3. The novel packaging structure according to claim 1, characterized in that: The sacrificial layer is located on two sides of the chip, or on all four sides of the chip.

4. The novel packaging structure according to claim 1, characterized in that: The manufacturing method also includes S7: The bottom surface of the chip has downward protruding electrodes, and at least one chip is soldered onto the substrate as a chip unit, so that there is a filling gap between the bottom surface of the chip and the substrate and between the bottom surface of the outer packaging layer and the substrate. S8: Fill the gaps and the outer periphery of the outer encapsulation layer with reflective material and cure it to obtain an encapsulation structure with a reflective layer.

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