A silicon carbide MCT device, its manufacturing method and application

Abstract

A silicon carbide MCT device, which sequentially includes an n-type silicon carbide substrate (1), an n-type silicon carbide buffer layer (2), a p-type drift layer (3), and an n-type base region (4) from bottom to top; a first p-type channel region (5), a p-type anode region (7), and a second p-type channel region (5') are sequentially arranged from left to right on the upper part of the n-type base region. The first p-type channel region (5) and the second p-type channel region (5') are respectively wrapped with a first n-type anode region (6) and a second n-type anode region (6'); a groove is arranged on one side of the top of the n-type base region (4), the side wall of the groove is covered with a groove gate oxide layer (8), and the inside of the groove is filled with a first gate electrode (9) to form a trench gate structure; the other side of the top of the n-type base region (4) is covered with a planar gate oxide layer (8'), and a second gate electrode (9) is filled on the upper part of the planar gate oxide layer (8') to form a planar gate structure. The device of the present invention has good conduction performance and is suitable as a basic component in the field of high-voltage and high-power power electronics.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a silicon carbide MOS-gated thyristor (MOS-Controlled Thyristor, MCT) device, a manufacturing method thereof, and an application thereof. Background Art

[0002] MCT is a new type of bipolar composite device. It integrates a MOS switch in an ordinary thyristor, and controls the turn-on and turn-off of the thyristor by the on-off of the MOS switch. Therefore, the MCT device has both good blocking and on-state characteristics of the thyristor, and also has the advantages of high input impedance, low drive power, and fast switching speed of the MOS field effect transistor. The MCT device overcomes the disadvantages of slow speed, inability to self-turn-off of the thyristor, and large on-state voltage drop of the high-voltage MOS field effect transistor. When a positive pulse voltage is applied to the gate, the drain current of the MCT turns on the internal NPN transistor. At the same time, the collector current of the NPN transistor turns on the internal PNP transistor, and the collector current of the PNP transistor promotes the conduction of the NPN transistor. Such positive feedback makes the MCT quickly turn from cut-off to conduction and enter the latching state; when a negative pulse voltage is applied to the gate relative to the cathode, the base-emitter of the PNP transistor is short-circuited, turning off the PNP transistor, thereby destroying the latching condition of the transistor and turning off the MCT. The conduction ability of the MCT is better than that of another common bipolar composite device, the IGBT (Insulated Gate Bipolar Transistor), but its control difficulty is more difficult than that of the IGBT, and the manufacturing process is more complex. However, in the fields of traction and high-voltage DC conversion, the urgent need for large-capacity, high-input-impedance power electronic devices motivates the research on MCT.

[0003] At present, the process of silicon-based MCT devices has gradually matured, while silicon carbide MCT devices are still in the preliminary research stage abroad and no products have emerged yet. Summary of the Invention

[0004] The main purpose of the present invention is to overcome the defects of the above background art, and provide a silicon carbide MCT device, a manufacturing method thereof, and an application thereof.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A silicon carbide MCT device, the silicon carbide MCT device sequentially includes an n-type silicon carbide substrate, an n-type silicon carbide buffer layer, a p-type drift layer, and an n-type base region from bottom to top; a first p-type channel region, a p-type anode region, and a second p-type channel region are sequentially arranged on the upper part of the n-type base region from left to right, and the first p-type channel region and the second p-type channel region are respectively wrapped with a first n-type anode region and a second n-type anode region; a trench is arranged on one side of the top of the n-type base region, a trench gate oxide layer is covered on the side wall of the trench, and a first gate electrode is filled in the trench to form a trench gate structure; a planar gate oxide layer is covered on the other side of the top of the n-type base region, and a second gate electrode is filled on the upper part of the planar gate oxide layer to form a planar gate structure.

[0007] Preferably, a dielectric layer is covered above both the trench gate structure and the planar gate structure, an anode metal is arranged on the top of the dielectric layer, and a cathode metal is arranged on the back of the n-type silicon carbide substrate.

[0008] Preferably, the trench depth is 2.5 μm to 3.5 μm; the trench depth is greater than the depth of the n-type base region and less than the depth of the p-type drift layer.

[0009] Preferably, the doping concentration of the n-type base region is 1E16 cm -3 to 2E17 cm -3 , and the doping concentrations of both the first p-type channel region and the second p-type channel region are 1E16 cm -3 to 2E17 cm -3 .

[0010] Preferably, the depth of the p-type anode region is 0.4 μm to 1.2 μm, the depths of the first p-type channel region and the second p-type channel region are 0.5 μm to 1 μm, the depth of the n-type base region is 1.5 μm to 3 μm, the depth of the p-type anode region is greater than the depths of the first p-type channel region and the second p-type channel region, and less than the depth of the n-type base region.

[0011] Preferably, the thicknesses of both the trench gate oxide layer and the planar gate oxide layer are 30 nm to 60 nm, and the thickness of the trench gate oxide layer is the same as that of the planar gate oxide layer; the thicknesses of the first gate electrode and the second gate electrode are 0.6 μm to 1 μm.

[0012] Preferably, the thickness of the dielectric layer is 0.6 μm to 2 μm; the anode metal is divided into three layers, and the layers in contact with the silicon carbide material from bottom to top are 100 nm Ni, 50 nm Ti, and 4 μm Al.

[0013] A manufacturing method of the silicon carbide MCT device includes:

[0014] S1. Epitaxially grow an n-type silicon carbide buffer layer, a p-type drift layer, and an n-type base region on an n-type silicon carbide substrate in sequence;

[0015] S2. Ion implant at the top of the n-type base region to form a first p-type channel region, a first n-type anode region, a p-type anode region, a second p-type channel region, and a second n-type anode region, and activate the implanted ions;

[0016] S3. Etch a groove on one side of the top of the n-type base region;

[0017] S4. Oxidize to form a trench gate oxide layer and a planar gate oxide layer;

[0018] S5. Deposit, planarize the surface, and etch to form a first gate electrode and a second gate electrode.

[0019] Preferably, it further includes:

[0020] S6. Deposit, planarize the surface, and etch to form a dielectric layer;

[0021] S7. Prepare an anode metal for ohmic contact and a back cathode metal.

[0022] An application of the silicon carbide MCT device in the field of high voltage and high current.

[0023] The present invention has the following beneficial effects: The silicon carbide MCT device of the present invention combines a planar gate structure and a trench gate structure. Compared with the traditional silicon-based MCT structure, by using an etching process instead of multiple ion implantations, two photolithographies are reduced, the process difficulty of the device is greatly reduced, the yield of the device product is improved, it is more suitable for the silicon carbide device process, and the overall process complexity is greatly reduced; compared with the silicon carbide-based IGBT device, the silicon carbide MCT device of the present invention has a larger conduction current, solves the problem of too small conduction current of high-voltage devices, and is particularly suitable for high-voltage and high-current application fields such as the energy Internet. Therefore, the present invention has the characteristics of a simple preparation method and good conduction performance of the silicon carbide MCT device, and is suitable as a basic component in the field of high-voltage and high-power power electronics. Description of the Drawings

[0024] Figure 1 It is a schematic structural diagram of the silicon carbide MCT device in the preferred embodiment of the present invention;

[0025] Figure 2 It is a flowchart of the manufacturing method of the silicon carbide MCT device in the preferred embodiment of the present invention;

[0026] Figures 3 to 8 It is a schematic diagram of the device structure obtained by different steps of the manufacturing method of the silicon carbide MCT device in the preferred embodiment of the present invention. Detailed Embodiments

[0027] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the convenience of description, only the parts related to the present invention rather than all the structures are shown in the drawings.

[0028] Referring to Figure 1 , an embodiment of the present invention provides a silicon carbide MCT device, which sequentially includes an n-type silicon carbide substrate 1, an n-type silicon carbide buffer layer 2, a p-type drift layer 3, and an n-type base region 4 from bottom to top; on the upper part of the n-type base region 4, a first p-type channel region 5, a p-type anode region 7, and a second p-type channel region 5' are sequentially arranged from left to right. The first p-type channel region 5 and the second p-type channel region 5' are respectively wrapped with a first n-type anode region 6 and a second n-type anode region 6' (that is, the first p-type channel region 5 wraps the first n-type anode region 6, and the second p-type channel region 5' wraps the second n-type anode region 6'); on one side of the top of the n-type base region 4, a trench is provided, the side wall of the trench is covered with a trench gate oxide layer 8, and the inside of the trench is filled with a first gate electrode 9 to form a trench gate structure; on the other side of the top of the n-type base region 4, a planar gate oxide layer 8' is covered, and a second gate electrode 9' is filled on the upper part of the planar gate oxide layer 8' to form a planar gate structure.

[0029] In a preferred embodiment, referring to Figure 1 , a dielectric layer 10 is covered above both the trench gate structure and the planar gate structure, an anode metal 11 is provided on the top of the dielectric layer 10, and a cathode metal 12 is provided on the back of the n-type silicon carbide substrate 1.

[0030] In a preferred embodiment, the depth of the trench is 2.5 μm to 3.5 μm; the depth of the trench is greater than the depth of the n-type base region 4 and less than the depth of the p-type drift layer 3.

[0031] In a preferred embodiment, the doping concentration of the n-type base region 4 is 1E16 cm -3 to 2E17 cm -3 , and the doping concentrations of both the first p-type channel region 5 and the second p-type channel region 5' are 1E16 cm -3 to 2E17 cm -3 . Through such a doping concentration design, it can be ensured that within the normal gate electrode control range, the OFF-FET and ON-FET can be turned on and off respectively.

[0032] In a preferred embodiment, the depth of the p-type anode region 7 is from 0.4 μm to 1.2 μm, the depths of the first p-type channel region 5 and the second p-type channel region 5' are both from 0.5 μm to 1 μm, the depth of the n-type base region 4 is from 1.5 μm to 3 μm, the depth of the p-type anode region 7 is greater than the depths of the first p-type channel region 5 and the second p-type channel region 5', and less than the depth of the n-type base region 4.

[0033] In a preferred embodiment, the thicknesses of the trench gate oxide layer 8 and the planar gate oxide layer 8' are both from 30 nm to 60 nm, and the thickness of the trench gate oxide layer 8 is the same as that of the planar gate oxide layer 8'; the thicknesses of the first gate electrode 9 and the second gate electrode 9' are both from 0.6 μm to 1 μm.

[0034] In a preferred embodiment, the thickness of the dielectric layer 10 is from 0.6 μm to 2 μm; the anode metal 11 is divided into three layers, which are in contact with the silicon carbide material from bottom to top as 100 nm Ni, 50 nm Ti, and 4 μm Al. That is, the layer in contact with the silicon carbide material in the anode metal 11 is the Ni layer, the Ti layer is on the Ni layer, and the Al layer is on the Ti layer.

[0035] In a specific example, the n-type silicon carbide substrate 1 in the silicon carbide MCT device is a 4°-tilted n-type silicon carbide substrate; the thickness of the n-type silicon carbide buffer layer 2 above the n-type silicon carbide substrate 1 is 1 μm, and the doping concentration is 1E18 cm -3 ; the doping concentration of the p-type drift layer 3 above the n-type silicon carbide buffer layer 2 is 1.5E14 cm -3 to 1E15 cm -3 , the thickness is from 60 μm to 300 μm, the doping concentration of the n-type base region 4 above the p-type drift layer 3 is 1E16 cm -3 to 2E17 cm -3 , the depth is from 1.5 μm to 3 μm; the upper part of the n-type base region 4 is successively provided with a first p-type channel region 5 (depth from 0.5 μm to 1 μm, doping concentration from 1E16 cm -3 to 2E17 cm -3 ), a p-type anode region 7 (doping concentration above 1E19 cm -3 high doping), and a second p-type channel region 5' (depth from 0.5 μm to 1 μm, doping 1E16 cm -3 to 2E17 cm -3 ), the first p-type channel region 5 and the second p-type channel region 5' are respectively wrapped with a first n-type anode region 6 (doping concentration above 1E19 cm -3 high doping) and a second n-type anode region 6' (doping concentration above 1E19 cm -3Above highly doped), the p-type anode region 7 is located in the center of the silicon carbide MCT device. The depth of the trench on the top side of the n-type base region 4 is 2.5 μm to 3.5 μm, which is greater than the depth of the n-type base region 4. The side wall of the trench is covered with a trench gate oxide layer 8 (with a thickness of 30 nm to 60 nm), and the inside of the trench is filled with a first gate electrode 9 (polycrystalline silicon electrode) to form a trench gate structure; the other side of the top of the n-type base region 4 is covered with a planar gate oxide layer 8' (with a thickness of 30 nm to 60 nm), and a second gate electrode 9' (polycrystalline silicon electrode) is filled on the upper part of the planar gate oxide layer 8' to form a planar gate structure. A dielectric layer 10 is covered above both the trench gate structure and the planar gate structure, and an anode metal 11 is provided on the top of the dielectric layer 10. Among them, the anode metal 11 is divided into three layers, and the layers in contact with the silicon carbide material from bottom to top are 100 nm Ni, 50 nm Ti, and 4 μm Al. A cathode metal 12 is provided on the back of the n-type silicon carbide substrate 1.

[0036] Referring to Figure 2 , the embodiment of the present invention also provides a manufacturing method of a silicon carbide MCT device, including the following steps:

[0037] S1. Epitaxially grow an n-type silicon carbide buffer layer 2, a p-type drift layer 3, and an n-type base region 4 on the n-type silicon carbide substrate 1 in sequence to form a structure as Figure 3 shown;

[0038] S2. Ion implant on the top of the n-type base region 4 to form a first p-type channel region 5, a first n-type anode region 6, a p-type anode region 7, a second p-type channel region 5', and a second n-type anode region 6', and perform implanted ion activation; specifically, implant Al ions in the p-type region, implant N ions in the n-type region, and perform implanted ion activation at 1700 °C for 20 min to form a structure as Figure 4 shown;

[0039] S3. Etch a trench on one side of the top of the n-type base region 4 to form a structure as Figure 5 shown; specifically, the etching gas can be selected as SF6, O2, and HBr with a volume ratio of 5:1:6;

[0040] S4. Oxidize to form a trench gate oxide layer 8 and a planar gate oxide layer 8'; specifically, perform dry oxygen oxidation under high temperature conditions of 1450 °C, so that the trench gate oxide layer 8 on the side wall of the trench and the planar gate oxide layer 8' have the same oxidation rate to form a trench oxide layer and a planar trench gate oxide layer 8', both with a thickness of 50 nm, and then perform NO annealing to form a structure as Figure 6 shown.

[0041] S5. Deposit, planarize the surface and etch to form the first gate electrode 9 and the second gate electrode 9'; specifically, use LPCVD (low pressure chemical vapor deposition) to deposit p-type doped polysilicon with a thickness of 0.6 μm to 1 μm, and then use CMP to planarize the surface and etch the polysilicon to form the first gate electrode 9 and the second gate electrode 9', forming a structure as shown in Figure 7 shown.

[0042] In a preferred embodiment, the manufacturing method of the silicon carbide MCT device further includes the following steps:

[0043] S6. Deposit, planarize the surface and etch to form the dielectric layer 10; specifically, use LPCVD to deposit an interlayer dielectric layer SiO2 with a thickness of 0.6 μm to 2 μm, and after planarizing the surface with CMP, etch to form the dielectric layer 10, forming a structure as shown in Figure 8 shown.

[0044] S7. Prepare the anode metal 11 and the back cathode metal 12 for ohmic contact to obtain the silicon carbide MCT device as shown in Figure 1 shown; specifically, sputter 100 nm of metal Ni on the front side, perform rapid thermal annealing at 1000 °C for 2 min, then wet-etch to remove the unreacted Ni, sputter 50 nm of metal Ti and evaporate 4 μm of metal Al, etch the metal to form a pad structure, sputter 100 nm of metal Ni on the back side of the n-type silicon carbide substrate 1, and then perform laser annealing to form an ohmic contact, finally forming the silicon carbide MCT device as shown in Figure 1 shown.

[0045] The embodiment of the present invention also provides an application of the described silicon carbide MCT device in the field of high voltage and large current.

[0046] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A silicon carbide MCT device, characterized in that, The silicon carbide MCT device includes an n-type silicon carbide substrate (1), an n-type silicon carbide buffer layer (2), a p-type drift layer (3), and an n-type base region (4) from bottom to top in sequence; on the upper part of the n-type base region, a first p-type channel region (5), a p-type anode region (7), and a second p-type channel region (5') are arranged in sequence from left to right, and the first p-type channel region (5) and the second p-type channel region (5') are respectively wrapped with a first n-type anode region (6) and a second n-type anode region (6'); a trench is provided on one side of the top of the n-type base region (4), the side wall of the trench is covered with a trench gate oxide layer (8), and a first gate electrode (9) is filled in the trench to form a trench gate structure; on the other side of the top of the n-type base region (4), a planar gate oxide layer (8') is covered, and a second gate electrode (9') is filled on the upper part of the planar gate oxide layer (8') to form a planar gate structure; a dielectric layer (10) is covered above both the trench gate structure and the planar gate structure, an anode metal (11) is provided on the top of the dielectric layer (10), and a cathode metal (12) is provided on the back of the n-type silicon carbide substrate (1); the depth of the trench is greater than the depth of the n-type base region (4) and less than the depth of the p-type drift layer (3); the depth of the p-type anode region (7) is greater than the depths of the first p-type channel region (5) and the second p-type channel region (5') and less than the depth of the n-type base region (4).

2. The silicon carbide MCT device according to claim 1, characterized in that: The depth of the trench is 2.5 μm to 3.5 μm.

3. The silicon carbide MCT device according to claim 1, characterized in that: The doping concentration of the n-type base region (4) is 1E16 cm -3 to 2E17 cm -3 , and the doping concentrations of the first p-type channel region (5) and the second p-type channel region (5') are both 1E16 cm -3 to 2E17 cm -3 .

4. The silicon carbide MCT device according to claim 1, characterized in that: The depth of the p-type anode region (7) is 0.4 μm to 1.2 μm, the depths of the first p-type channel region (5) and the second p-type channel region (5') are 0.5 μm to 1 μm, and the depth of the n-type base region (4) is 1.5 μm to 3 μm.

5. The silicon carbide MCT device according to claim 1, characterized in that: The thicknesses of both the trench gate oxide layer (8) and the planar gate oxide layer (8') are 30 nm to 60 nm, and the thickness of the trench gate oxide layer (8) is the same as that of the planar gate oxide layer (8'); the thicknesses of both the first gate electrode (9) and the second gate electrode (9') are 0.6 μm to 1 μm.

6. The silicon carbide MCT device according to claim 1, characterized in that: The thickness of the dielectric layer (10) is 0.6 μm to 2 μm; the anode metal (11) is divided into three layers, and the layers in contact with the silicon carbide material from bottom to top are 100 nm Ni, 50 nm Ti, and 4 μm Al respectively.

7. A manufacturing method of the silicon carbide MCT device according to any one of claims 1-6, characterized in that: Including: S1. Epitaxially grow an n-type silicon carbide buffer layer (2), a p-type drift layer (3), and an n-type base region (4) on an n-type silicon carbide substrate (1) in sequence; S2. Ion implant to form a first p-type channel region (5), a first n-type anode region (6), a p-type anode region (7), a second p-type channel region (5'), and a second n-type anode region (6') on the top of the n-type base region (4), and activate the implanted ions; the depth of the p-type anode region (7) is greater than the depths of the first p-type channel region (5) and the second p-type channel region (5') and less than the depth of the n-type base region (4); S3. Etch a trench on one side of the top of the n-type base region (4); the depth of the trench is greater than the depth of the n-type base region (4) and less than the depth of the p-type drift layer (3); S4. Oxidize to form a trench gate oxide layer (8) and a planar gate oxide layer (8'); S5. Deposit, planarize the surface and etch to form a first gate electrode (9) and a second gate electrode (9'); S6. Deposit, planarize the surface and etch to form a dielectric layer (10); S7. Prepare an anode metal (11) for ohmic contact and a back cathode metal (12).

8. An application of the silicon carbide MCT device according to any one of claims 1-6 in the field of high voltage and large current.

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