A manufacturing method of an integrated JBS trench SiC transistor

Abstract

The application provides a manufacturing method of an integrated JBS trench SiC transistor, which comprises the following steps: forming a drift layer on a silicon carbide substrate; forming a blocking layer on the drift layer; etching and ion implanting the blocking layer to form a mask layer; re-forming the blocking layer on the drift layer and etching the blocking layer and the drift layer to form a gate region; oxidizing and etching the gate region to form a gate insulating layer; depositing a gate on the gate insulating layer; re-forming the blocking layer, etching and depositing a Schottky metal layer on the blocking layer; depositing a SiC material with the same concentration as the source region on the Schottky metal layer; re-forming the blocking layer, etching and ion implanting the blocking layer to form a source region, and implanting to form the source region; forming a source metal layer on the source region; re-forming the blocking layer, etching and depositing a gate metal layer to form the gate metal layer, and removing the blocking layer; and depositing a drain metal layer on the silicon carbide substrate, so that the on-resistance of the body diode is reduced without sacrificing the voltage resistance characteristic.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a trench SiC transistor with integrated JBS. Background Technology

[0002] Silicon carbide (SiC) materials have attracted widespread attention and research due to their superior physical properties. Its high-temperature, high-power electronic devices possess advantages such as high input impedance, fast switching speed, high operating frequency, and resistance to high temperatures and pressures, leading to their widespread application in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] However, due to the exceptionally high critical breakdown field strength of SiC and its poor gate oxide quality, the gate oxide in trench-gate SiC MOSFETs is easily broken down, especially at the trench corners where the electric field is concentrated and extremely strong. Therefore, it is necessary to address the problem of excessive electric field strength at the trench corners. Furthermore, in practical applications, the body diode often exhibits freewheeling current, and traditional devices, due to the characteristics of SiC material, have excessively high turn-on voltages for the body diode, resulting in significant losses. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a trench SiC transistor with integrated JBS, which adopts a JBS structure, which has both the low turn-on voltage of gold-semiconductor contacts and the high breakdown voltage of PN junctions, and reduces the conduction loss of the body diode without sacrificing the breakdown voltage characteristics.

[0005] This invention is achieved as follows: a method for manufacturing a trench-type SiC transistor with integrated JBS, comprising the following steps:

[0006] Step 1: A drift layer is formed on a silicon carbide substrate, then a barrier layer is formed on the drift layer, and a masking layer via is formed by etching the barrier layer. Ions are implanted into the drift layer through the via to form the masking layer.

[0007] Step 2: Re-form the barrier layer on the drift layer, and etch the barrier layer and drift layer to form the gate region;

[0008] Step 3: Oxidize the gate region and etch it to form a gate insulating layer;

[0009] Step 4: Deposit the gate on the gate insulating layer;

[0010] Step 5: Reform the barrier layer and etch the barrier layer to form the Schottky metal region deposition window;

[0011] Step 6: Deposit a Schottky metal layer;

[0012] Step 7: Deposit SiC material with the same concentration as the source region on the Schottky metal layer;

[0013] Step 8: Reform the barrier layer and etch the barrier layer to form the source region by ion implantation;

[0014] Step 9: Deposit source region metal on the source region to form a source metal layer;

[0015] Step 10: Reform the barrier layer, etch the gate metal deposition area of ​​the barrier layer, deposit the gate metal layer, and remove the barrier layer;

[0016] Step 11: Deposit a drain metal layer on a silicon carbide substrate.

[0017] Furthermore, the masking layer is P+ type, and the cross-section of the masking layer is L type.

[0018] The advantages of this invention are:

[0019] 1. The trench-type SiC MOSFET device has a masking layer at the trench corner below the gate. This masking layer is located at the gate oxide trench corner, which is where the gate oxide electric field strength is the highest. This masking layer can effectively reduce the electric field strength at the trench corner and improve the gate oxide reliability.

[0020] Second, a metal-semiconductor base was constructed above the masking layer to form a Schottky junction, which can reduce the on-state voltage drop during the conduction of the MOS diode and reduce the power consumption of the body diode.

[0021] Third, the basically parasitic pn junction diode of this device also participates in conduction and can maintain reverse breakdown voltage;

[0022] Fourth, the Schottky junction, together with the pn junction present in the original device structure, constitutes a JBS diode, and the formation of this diode eliminates the bipolar degradation effect. Attached Figure Description

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 1 .

[0025] Figure 2 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 2 .

[0026] Figure 3 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 3 .

[0027] Figure 4This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 4 .

[0028] Figure 5 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 5 .

[0029] Figure 6 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 6 .

[0030] Figure 7 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 7 .

[0031] Figure 8 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 8 .

[0032] Figure 9 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 9 .

[0033] Figure 10 This invention relates to a manufacturing process for a trench SiC transistor with integrated JBS. Figure 10 .

[0034] Figure 11 This is a schematic diagram of the structure of a trench-type SiC transistor with integrated JBS according to the present invention. Detailed Implementation

[0035] like Figures 1 to 10 As shown, the present invention discloses a method for manufacturing a trench-type SiC transistor with integrated JBS, comprising the following steps:

[0036] Step 1: A drift layer 2 is formed on a silicon carbide substrate 1. Then, a barrier layer 24 is formed on the drift layer 2, and a masking layer via is formed by etching the barrier layer 24. Ion implantation is performed on the drift layer through the via to form a masking layer 21.

[0037] Step 2: Re-form the barrier layer 24 on the drift layer 2, and etch the barrier layer 24 and the drift layer 2 to form the gate region 25;

[0038] Step 3: Oxidize the gate region 25 and etch it to form the gate insulating layer 23;

[0039] Step 4: Deposit gate 3 on gate insulating layer 23;

[0040] Step 5: Reform the barrier layer 24 and etch the barrier layer 24 to form the Schottky metal region deposition window;

[0041] Step 6: Deposit Schottky metal layer 22;

[0042] Step 7: Deposit SiC material with the same concentration as the source region on the Schottky metal layer 22;

[0043] Step 8: Reform the barrier layer 24, and etch the barrier layer to form the source region ion implantation, implantation to form the source region 4;

[0044] Step 9: Deposit source metal on source region 4 to form source metal layer 5;

[0045] Step 10: Reform the barrier layer 24, etch the gate metal deposition area of ​​the barrier layer, deposit the gate metal layer 6, and remove the barrier layer;

[0046] Step 11: Deposit a drain metal layer 7 on the silicon carbide substrate 1.

[0047] The masking layer 21 is P+ type, and the cross-section of the masking layer 21 is L type.

[0048] like Figure 11 As shown, the transistor obtained by the above manufacturing method includes:

[0049] A silicon carbide substrate 1,

[0050] A drift layer 2 is disposed on the upper surface of the silicon carbide substrate 1; a masking layer 21, a Schottky metal layer 22, and a gate insulating layer 23 are disposed on the drift layer 2; the top of the masking layer 21 is connected to the bottom of the Schottky metal layer 22, and the masking layer 21 is connected to the gate insulating layer 23; the masking layer 21 is P+ type, and the cross-section of the masking layer 21 is L type; the top surface of the Schottky metal layer 22 is flush with the top surface of the drift layer 3.

[0051] A gate 3 is disposed within the gate insulating layer 23;

[0052] A source region 4, the bottom of which is connected to the drift layer 2 and the Schottky metal layer 22 respectively, and the side of the source region 4 is connected to the gate insulating layer 23;

[0053] A source metal layer 5 is connected to the source region 4;

[0054] A gate metal layer 6 is connected to the gate 3;

[0055] And a drain metal layer 7, which is connected to the lower end face of the silicon carbide substrate 1.

[0056] A masking layer 21 surrounds P+ at both sides of the gate insulating layer 23 (typically an oxide layer, SiO2). This masking layer 21 reduces the electric field strength at the gate dielectric trench corners and improves the reliability of the gate insulating layer 23.

[0057] A Schottky metal layer 22 is made above the masking layer 21. The Schottky metal 22 is in contact with the masking layer 21 below and with the source region 4 above, forming a gold-semiconductor contact with the masking layer 21, thus forming a Schottky diode (i.e., SBD).

[0058] A pn junction diode is formed between source region 4 and drift layer 2, which together with SBD constitutes a parasitic JBS.

[0059] The masking layer 21 surrounds the slot corner of the gate insulating layer 23, effectively reducing the electric field strength of the gate oxide and improving gate oxide reliability. A Schottky metal layer 22 is deposited between the source region 4 and the masking layer 21. This Schottky metal layer 22 forms an ohmic contact with the source region 4 and a gold-semiconductor contact with the masking layer 21, constituting a low turn-on voltage Schottky diode. It can conduct through the JBS before the transistor is turned on, reducing the conduction loss of the body diode. At the same time, the reverse breakdown voltage characteristic of the pn junction has no loss, and high breakdown voltage characteristics can still be achieved.

[0060] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a trench-type SiC transistor with integrated JBS, characterized in that, Includes the following steps: Step 1: A drift layer is formed on a silicon carbide substrate, then a barrier layer is formed on the drift layer, and a masking layer via is formed by etching the barrier layer. Ions are implanted into the drift layer through the via to form the masking layer. Step 2: Re-form the barrier layer on the drift layer, and etch the barrier layer and drift layer to form the gate region; Step 3: Oxidize the gate region and etch it to form a gate insulating layer; Step 4: Deposit the gate on the gate insulating layer; Step 5: Reform the barrier layer and etch the barrier layer to form the Schottky metal region deposition window; Step 6: Deposit a Schottky metal layer; Step 7: Deposit SiC material with the same concentration as the source region on the Schottky metal layer; Step 8: Reform the barrier layer and etch the barrier layer to form the source region by ion implantation; Step 9: Deposit source region metal on the source region to form a source metal layer; Step 10: Reform the barrier layer, etch the gate metal deposition area of ​​the barrier layer, deposit the gate metal layer, and remove the barrier layer; Step 11: Deposit a drain metal layer on a silicon carbide substrate; The drift layer is disposed on the upper surface of the silicon carbide substrate; a masking layer, a Schottky metal layer, and a gate insulating layer are disposed on the drift layer; the top of the masking layer is connected to the bottom of the Schottky metal layer, the masking layer is connected to the gate insulating layer, the masking layer is P+ type, and the cross-section of the masking layer is L type; The gate is disposed within the gate insulating layer; the bottom of the source region is connected to the top of the drift layer and the Schottky metal layer respectively, and the side of the source region is connected to the gate insulating layer; the source metal layer is connected to the source region; and the gate metal layer is connected to the gate.

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