Signal transceiver circuit, method for operating a transmission circuit, and method for setting a delay circuit

Abstract

The present invention discloses a signal transceiver circuit, a method for operating a signal transmission circuit, and a method for setting a delay circuit. The signal transceiver circuit is used to send an output signal and receive an input signal, and includes: a delay circuit, used to delay a first clock to generate a second clock; a first digital-to-analog converter, used to convert a first digital signal into the output signal according to the first clock; a second digital-to-analog converter, used to convert the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit, used to receive the input signal and the echo cancellation signal and generate an analog signal; and an analog-to-digital converter, used to convert the analog signal into a second digital signal.

Description

Technical Field

[0001] The present invention relates to a signal transceiver circuit, and more particularly to reducing or eliminating hybrid echo in the signal transceiver circuit. Background Art

[0002] In conventional signal transceiver circuits, the signal receiving end often receives unwanted echoes. These echoes originate from the signal transmitting end and are closely related to the output signal sent by the signal transmitting end. The signal receiving end typically implements an echo cancellation circuit to cancel the echo. This echo cancellation circuit cancels the echo based on an echo cancellation signal provided by the signal transmitting end. Generally speaking, in actual circuits, there is a physical distance (i.e., a first physical distance) between the circuit generating the output signal and the signal receiving end, and another physical distance (i.e., a second physical distance) between the circuit generating the echo cancellation signal and the signal receiving end. Unfortunately, because the first physical distance is not exactly equal to the second physical distance, a phase difference exists between the echo and the echo cancellation signal, resulting in a mixed echo at the signal receiving end. Excessive mixed echo can degrade the performance of the signal transceiver circuit or the system utilizing the signal transceiver circuit, or even cause unexpected errors. Therefore, a circuit or method is needed to reduce or eliminate mixed echoes. Summary of the Invention

[0003] In view of the deficiencies of the prior art, an object of the present invention is to provide a signal transceiver circuit, a method for operating a signal transmitting circuit, and a method for setting a delay circuit to improve the deficiencies of the prior art.

[0004] The present invention discloses a signal transceiver circuit for transmitting an output signal and receiving an input signal. The circuit includes: a delay circuit for delaying a first clock to generate a second clock; a first digital-to-analog converter for converting a first digital signal into the output signal according to the first clock; a second digital-to-analog converter coupled to the delay circuit for converting the first digital signal into an echo cancellation signal according to the second clock; an analog front-end circuit for receiving the input signal and the echo cancellation signal and generating an analog signal; and an analog-to-digital converter coupled to the analog front-end circuit for converting the analog signal into a second digital signal.

[0005] The present invention also discloses a method for setting a delay circuit, wherein the delay circuit is applied to a signal transceiver circuit and delays a first clock according to a delay parameter to generate a second clock. The signal transceiver circuit includes a first digital-to-analog converter, a second digital-to-analog converter, and an analog-to-digital converter. The first digital-to-analog converter operates according to the first clock, the second digital-to-analog converter operates according to the second clock, and the analog-to-digital converter generates a digital signal. The method includes: (A) setting the delay parameter of the delay circuit; (B) measuring the power of the digital signal at multiple phases to be measured to generate multiple measured powers; (C) calculating the average power of the multiple measured powers, the average power corresponding to the delay parameter; (D) repeating steps (A) to (D) to generate multiple average powers; and (E) setting the delay circuit with the delay parameter corresponding to the minimum value of these average powers.

[0006] The present invention also discloses a method for operating a signal transmission circuit that transmits an output signal and includes a delay circuit, a first digital-to-analog converter, and a second digital-to-analog converter. The method includes: providing a first clock to the delay circuit and the first digital-to-analog converter; the first digital-to-analog converter converting a digital signal into the output signal based on the first clock; the delay circuit delaying the first clock to generate a second clock; providing the second clock to the second digital-to-analog converter; and the second digital-to-analog converter converting the digital signal into an echo cancellation signal based on the second clock.

[0007] The features, implementations and effects of the present invention will be described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a functional block diagram of an embodiment of a signal transceiver circuit of the present invention;

[0009] Figure 2 is a flow chart of an operating method of a signal transmission circuit of the present invention;

[0010] Figure 3 is a flow chart of a method for setting a delay circuit of the present invention; and

[0011] Figures 4A-4C FIG. 4 is a waveform diagram of the echo Vout′, the echo cancellation signal Vec, and the mixed echo. DETAILED DESCRIPTION

[0012] The technical terms used in the following descriptions refer to the customary terms in this technical field. If this specification provides explanations or definitions for some terms, the interpretation of these terms shall be based on the explanations or definitions in this specification.

[0013] The disclosure of the present invention includes a signal transceiver circuit, a method for operating the signal transmission circuit, and a method for setting a delay circuit. Because some components of the signal transceiver circuit of the present invention may be known components, the following description will omit details of known components without affecting the full disclosure and feasibility of the device invention. Furthermore, part or all of the process of the method for setting a delay circuit of the present invention may be in the form of software and / or hardware. Without affecting the full disclosure and feasibility of the method invention, the following description of the method invention will focus on the steps rather than the hardware.

[0014] Figure 1 This is a functional block diagram of an embodiment of a signal transceiver circuit according to the present invention. Signal transceiver circuit 100 is coupled to digital processing circuit 200. The digital output signal Dout generated by digital processing circuit 200 is converted by signal transceiver circuit 100 into an output signal Vout, which is then transmitted (e.g., via an antenna). Signal transceiver circuit 100 receives an external input signal Vin (e.g., via an antenna) and generates a digital input signal Din.

[0015] The signal transceiver circuit 100 includes a signal transmitting circuit 110 and a signal receiving circuit 120 . The signal transmitting circuit 110 includes a digital-to-analog converter 112 , a digital-to-analog converter 114 , and a delay circuit 116 . The signal receiving circuit 120 includes an analog front-end circuit 122 and an analog-to-digital converter 124 .

[0016] The digital-to-analog converter 112 operates according to a clock CLK to convert the digital output signal Dout generated by the digital processing circuit 200 into an output signal Vout. The echo Vout' of the output signal Vout is transmitted to the analog front-end circuit 122 of the signal receiving circuit 120 via the echo path 130. The digital-to-analog converter 114 operates according to the clock CLK' to convert the digital output signal Dout into an echo cancellation signal Vec. The analog front-end circuit 122 is used to process the input signal Vin (e.g., amplify, downconvert, etc.). Another purpose of the analog front-end circuit 122 is to use the echo cancellation signal Vec to cancel the echo Vout', thereby reducing the interference of the echo Vout' on the input signal Vin (i.e., the goal is to make the analog signal Sin not include the echo Vout'). The analog-to-digital converter 124 is used to convert the analog signal Sin into a digital input signal Din.

[0017] Delay circuit 116 is used to delay clock CLK to generate clock CLK'. Digital processing circuit 200 controls the delay parameter of delay circuit 116 using control signal SC. For example, delay circuit 116 includes a capacitor array and multiple switches (the switches are controlled by control signal SC). The on / off status of the switches determines the number of capacitors connected in series or parallel (i.e., determines the equivalent capacitance of the capacitor array). The equivalent capacitance of the capacitor array (i.e., the delay parameter of delay circuit 116) is related to the delay amount of delay circuit 116.

[0018] In some cases, the DAC 114 is physically located closer to the analog front-end circuit 122 than the DAC 112, resulting in a phase difference between the echo Vout' and the echo cancellation signal Vec (i.e., causing a mixed echo in the signal receiving circuit 120). To address this issue, the delay circuit 116 delays the clock CLK, causing the clock CLK' to lag behind the clock CLK (i.e., the phase of the clock CLK' is later than the phase of the clock CLK). "Making the phase of the clock CLK' later than the phase of the clock CLK" is equivalent to "making the echo cancellation signal Vec of the DAC 114 start later than the output signal Vout of the DAC 112." This reduces the phase difference between the echo Vout' and the echo cancellation signal Vec in the signal receiving circuit 120 (compared to when the DACs 112 and 114 use the same clock), thereby effectively reducing the mixed echo.

[0019] Those skilled in the art are familiar with the details of delay circuit 116 and will not be described in detail here. In some embodiments, delay circuit 116 can be implemented using a phase interpolator, which performs phase interpolation on clock CLK (i.e., performs phase interpolation based on clock CLK) to generate clock CLK'. In other words, the phase interpolator delays clock CLK through phase interpolation. Controlling a phase interpolator using a digital control signal SC is well known to those skilled in the art and will not be described here in detail here (see: http: / / iram.cs.berkeley.edu / serialio / cs254 / interpolator / interp.html).

[0020] Please refer to Figure 2 , Figure 2 It is a flow chart of the operating method of the signal sending circuit of the present invention, which includes the following steps.

[0021] Step S210 : Provide the clock CLK to the delay circuit 116 and the DAC 112 (ie, the first DAC).

[0022] Step S220 : The DAC 112 converts the digital output signal Dout into an output signal Vout according to the clock CLK.

[0023] Step S230: The delay circuit 116 delays the clock CLK to generate the clock CLK'. For the phase interpolator, interpolating the clock CLK to generate the clock CLK' is equivalent to delaying the clock CLK to generate the clock CLK'.

[0024] Step S240 : Provide the clock CLK′ to the DAC 114 (ie, the second DAC).

[0025] Step S250 : The digital-to-analog converter 114 converts the digital output signal Dout into the echo cancellation signal Vec according to the clock CLK′.

[0026] The following discusses how to determine the delay parameters of the delay circuit 116. Figure 3 , Figure 3 The flowchart of the method for setting a delay circuit of the present invention includes the following steps.

[0027] Step S310: Set the delay parameters of delay circuit 116. For example, in this step, digital processing circuit 200 controls the equivalent capacitance value of delay circuit 116 via control signal SC. For another example, if delay circuit 116 is implemented as a phase interpolator, in this step, digital processing circuit 200 controls switches within the phase interpolator via control signal SC.

[0028] Step S320 : The digital processing circuit 200 determines the phase to be measured.

[0029] Step S330 : The digital processing circuit 200 measures the power of the digital input signal Din at the phase to be measured to generate a measured power corresponding to the phase to be measured.

[0030] Step S340: The digital processing circuit 200 determines whether there are still phases to be measured. In some embodiments, the digital processing circuit 200 measures the power of the digital input signal Din at multiple phases to be measured within a symbol duration of the digital input signal Din, where the symbol duration is the inverse of the symbol rate of the digital input signal Din. For example, if the digital processing circuit 200 is configured to measure the power of the digital input signal Din at N phases to be measured (N is a positive integer), the digital processing circuit 200 executes steps S320 and S330 N times and obtains N measured powers (one corresponding to each of the N phases to be measured). If there are no unprocessed phases to be measured (step S340 determines "no"), the digital processing circuit 200 executes step S350.

[0031] Step S350: The digital processing circuit 200 calculates the average of the N measured powers. The average power generated in this step corresponds to the delay parameter set in step S310. In other words, one delay parameter corresponds to one average power.

[0032] Step S360: Digital processing circuit 200 determines whether to continue setting the delay parameters of delay circuit 116. For example, if the physical distance difference between DAC 112 and DAC 114 is approximately equivalent to a range of 0 ps to 250 picoseconds (picoseconds), and the delay resolution of delay circuit 116 is 2.5 ps, digital processing circuit 200 sets delay circuit 116 using M delay parameters (M is an integer with 1≤M≤100, corresponding to delay times of 2.5 ps, 5.0 ps, ​​..., 247.5 ps, and 250 ps, ​​respectively). If all delay parameters have been used (i.e., digital processing circuit 200 does not select the next delay parameter, and step S360 determines "no"), digital processing circuit 200 executes step S370. Otherwise, digital processing circuit 200 executes step S310.

[0033] Step S370: The digital processing circuit 200 determines a final delay parameter for the delay circuit 116. More specifically, the digital processing circuit 200 finds the minimum value of the M average powers and uses the delay parameter corresponding to the minimum average power as the final delay parameter. The delay circuit 116 is then configured with the final delay parameter.

[0034] As mentioned above, Figure 3 The process can determine a better delay parameter for the delay circuit 116, so that the power of the digital input signal Din is relatively small (that is, the mixed echo contained therein is relatively small). In some embodiments, the digital processing circuit 200 is implemented as a finite state machine (FSM). Figure 3 In other embodiments, the digital processing circuit 200 is a circuit with program execution capability, which executes program code or program instructions (for example, stored in the storage circuit 210 of the digital processing circuit 200) to complete the process. Figure 3 process.

[0035] Please refer to Figures 4A-4C , Figures 4A-4C is a waveform diagram of the echo Vout', the echo cancellation signal Vec and the mixed echo (ie, Vout'-Vec). Figures 4A-4C corresponding to different delay parameters (i.e., Figures 4A-4C have their own average power). Figures 4A-4CThe "T" in represents the symbol duration of the digital input signal Din, and the time points t1, t2, ..., tk, ..., tN correspond to a phase to be measured (1≤k≤N). Figure 4B As shown, the amplitude of the mixed echo corresponding to time point t1 is 0, while the amplitude of the mixed echo corresponding to time point t2 is not 0. Therefore, if steps S320 and S330 are performed only once, a low sampling rate (possibly accompanied by aliasing) may result in misjudgment (i.e., if the power is measured at time point t1, a lower power will be obtained, leading to the mistaken impression that the mixed echo is relatively small). Figure 3 The purpose of the method is to find the delay parameters corresponding to the relatively small mixed echo. When the resolution of the delay circuit 116 is high enough, Figure 3 Ideally, the process can be found to make the echo Vout' and the echo cancellation signal Vec substantially aligned (ie, the phase difference between the two is substantially 0, such as Figure 4C The final delay parameters are shown).

[0036] In summary, the present invention overcomes or offsets the signal delay caused by signal path differences in the physical circuit by delaying the clock of the digital-to-analog converter, thereby achieving better echo cancellation (i.e., lower amplitude or power of the mixed sound). Therefore, the signal transceiver circuit of the present invention has better performance.

[0037] Since those skilled in the art can understand the implementation details and variations of the method invention of the present invention with the help of the disclosure of the device invention of the present invention, in order to avoid redundancy, repeated descriptions are omitted here without affecting the disclosure requirements and feasibility of the method invention. Please note that the shapes, sizes and proportions of the components in the previous figures are only for illustration and are for those skilled in the art to understand the present invention, and are not intended to limit the present invention. In addition, in some embodiments, the steps mentioned in the flowcharts disclosed above can be adjusted in order according to actual operations, and can even be executed simultaneously or partially simultaneously.

[0038] Although the embodiments of the present invention are described above, these embodiments are not intended to limit the present invention. Those skilled in the art may modify the technical features of the present invention based on the explicit or implicit content of the present invention. All such modifications may fall within the scope of the patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be subject to that defined in the claims of this specification.

[0039]

Explanation of symbols

[0040] 100: Signal transceiver circuit

[0041] 200: Digital processing circuit

[0042] Dout: digital output signal

[0043] Vout: output signal

[0044] Vin: input signal

[0045] Din: digital input signal

[0046] 110: Signal sending circuit

[0047] 120: Signal receiving circuit

[0048] 112, 114: Digital-to-analog converter

[0049] 116: Delay Circuit

[0050] 122: Analog Front-End Circuit

[0051] 124: Analog-to-digital converter

[0052] CLK, CLK': clock

[0053] Vout': echo

[0054] 130: Echo Path

[0055] Vec: echo cancellation signal

[0056] Sin: analog signal

[0057] SC: control signal

[0058] 210: Storage Circuit

[0059] t1, t2, tk, tN: time points

[0060] T: symbol duration

[0061] S210, S220, S230, S240, S250, S310, S320, S330, S340, S350, S360, S370: Steps

Claims

1. A method for setting a delay circuit, wherein the delay circuit is applied to a signal transceiver circuit and delays a first clock according to a delay parameter to generate a second clock, wherein the signal transceiver circuit comprises a first digital-to-analog converter, a second digital-to-analog converter and an analog-to-digital converter, wherein the first digital-to-analog converter operates according to the first clock, the second digital-to-analog converter operates according to the second clock, and the analog-to-digital converter generates a digital signal, wherein the method comprises: (A) setting the delay parameter of the delay circuit; (B) measuring the power of the digital signal at a plurality of phases to be measured to generate a plurality of measured powers; (C) calculating an average power of the plurality of measured powers, the average power corresponding to the delay parameter; (D) repeating steps (A) to (D) to generate a plurality of average powers; and (E) Setting the delay circuit with the delay parameter corresponding to the minimum value of the plurality of average powers. 2 . The method according to claim 1 , wherein the plurality of phases to be measured are a plurality of phases within a symbol duration of the digital signal. The method of claim 1 , wherein the delay circuit is a phase interpolator.

4. A signal transceiver circuit, used to send an output signal and receive an input signal, comprising: A delay circuit arranged according to the method according to any one of claims 1 to 3, for delaying a first clock to generate a second clock; A first digital-to-analog converter, configured to convert a first digital signal into the output signal according to the first clock; a second digital-to-analog converter, coupled to the delay circuit, for converting the first digital signal into an echo cancellation signal according to the second clock; An analog front-end circuit, used for receiving the input signal and the echo cancellation signal, and generating an analog signal; as well as The analog-to-digital converter is coupled to the analog front-end circuit and is used for converting the analog signal into a second digital signal. 5 . The signal transceiving circuit according to claim 4 , wherein the delay circuit is a phase interpolator.

6. A method for operating a signal transmission circuit, the signal transmission circuit transmitting an output signal and comprising the delay circuit according to claim 4 or 5, a first digital-to-analog converter and a second digital-to-analog converter, the method comprising: Providing a first clock to the delay circuit and the first digital-to-analog converter; The first digital-to-analog converter converts the digital signal into the output signal according to the first clock; The delay circuit delays the first clock to generate a second clock; providing the second clock to the second digital-to-analog converter; as well as The second digital-to-analog converter converts the digital signal into an echo cancellation signal according to the second clock. The method of claim 6 , wherein the delay circuit is a phase interpolator.

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