An environment-adaptive SLAM backend FPGA accelerator and design method

Abstract

The present invention discloses an environment-adaptive SLAM back-end FPGA accelerator structure and design method, the accelerator structure includes a configurable circuit module, an environment-adaptive parameter update module and a gated clock arranged at the SLAM back-end, wherein: visual information data is divided into two paths through the SLAM front-end: one path inputs visual information extracted from the environment to the configurable circuit module arranged at the SLAM back-end; the other path sends the number of landmark points to the environment-adaptive parameter update module arranged at the SLAM back-end; a gated clock circuit is used to control the number of configurable circuit modules turned on; and, according to the number of landmark points collected by the SLAM front-end, the configuration parameters that minimize the power consumption of the configurable circuit module in the current environment are solved, and the configuration parameters of the configurable circuit module are updated. Compared with the prior art, the present invention realizes dynamic adjustment of the architecture and can reduce power consumption during operation.

Description

Technical Field

[0001] The invention belongs to the technical field of FPGA devices, and in particular relates to a FPGA accelerator design for a SLAM backend. Background Art

[0002] SLAM (Simultaneous Localization And Mapping) is a key technology for drones and unmanned vehicles to determine their own motion trajectory without known map information. The SLAM system is divided into the front end and the back end. The front end calculates the initial motion trajectory based on the collected sensor data. Since the data collected by the sensor has noise, the accuracy of the initial trajectory cannot meet the actual requirements. The back end optimizes the initial trajectory calculated by the front end.

[0003] The SLAM backend usually uses nonlinear optimization methods to optimize the state. This method uses the error of sensor observation data to construct a cost function and obtains the motion state of the system by minimizing the cost function. Commonly used algorithms include Gauss-Newton method, Levenberg-Marquardt method, etc. However, the high computational complexity and data complexity of nonlinear algorithms limit the use of SLAM algorithms on mobile embedded devices.

[0004] Field Programmable Gate Array (FPGA) can realize large-scale parallel computing and has the advantage of reconfiguration. Implementing a hardware accelerator for the SLAM backend algorithm on FPGA can meet the real-time requirements of the SLAM backend algorithm in mobile scenarios. In practical applications, as the environment continues to change, the amount of data collected by the SLAM front end also changes, resulting in changes in the amount of calculation of the SLAM backend. In order to ensure the real-time nature of the calculation, the traditional SLAM backend hardware accelerator is designed for the case with the largest amount of calculation, and the hardware architecture is fixed during operation and cannot reduce power consumption according to changes in the environment. Summary of the invention

[0005] The purpose of the present invention is to propose an environment-adaptive SLAM back-end FPGA accelerator and design method, aiming at the circuit architecture in the SLAM back-end FPGA accelerator to adaptively adjust the circuit according to the change of the environment. In order to realize the environment-adaptive parameter update, the problem of solving the circuit configuration parameters is constructed with the minimum power consumption as the optimization goal and the calculation delay as the constraint condition.

[0006] The technical solutions adopted to achieve the purpose of the present invention are as follows:

[0007] An environment-adaptive SLAM back-end FPGA accelerator, the accelerator structure includes a configurable circuit module, an environment-adaptive parameter update module and a gated clock arranged at the SLAM back-end, wherein:

[0008] The visual information data is divided into two paths through the SLAM front end: one path inputs the visual information extracted from the environment to the configurable circuit module set in the SLAM back end; the other path sends the number of landmark points to the environment adaptive parameter update module set in the SLAM back end; the configurable circuit module is a group of parameterizable circuit modules for computing and storage resources of the FPGA accelerator, and each configurable circuit module corresponds to a configurable parameter; the gated clock is respectively connected to the configurable circuit module and the environment adaptive parameter update module, and the control is realized by means of the clock enable signal of the gated clock, specifically: the environment adaptive configuration parameter update module outputs the clock enable signal, and the gated clock circuit is used to control the number of configurable circuit modules turned on to realize dynamic adjustment of the architecture; and according to the number of landmark points collected by the SLAM front end, the configuration parameters that minimize the power consumption of the configurable circuit module in the current environment are solved, and the configuration parameters of the configurable circuit module are updated;

[0009] The configurable circuit module includes an input buffer, a Jacobi update module, a Schur elimination module, a storage unit, a Chokowski decomposition module, a state update module, a marginalization module and an output buffer connected in sequence; the configurable parameters are the number of multiplication and accumulation units n in the Schur elimination module d , the number of decomposition units in the Chokowski decomposition module s and the number of multiplication-accumulation units in the marginalization module n m ;

[0010] The input cache, the output cache and the storage unit realize the function of data storage, the Jacobi update module is used to calculate the partial derivatives of visual observations with respect to system optimization variables, the Schur elimination module processes the Jacobi matrix and performs Schur elimination operations, the Chokowski decomposition module decomposes the coefficient matrix of the linear equations obtained by the Schur elimination module into a triangular matrix, the state update module is used to solve the increment of the state vector and output the updated state vector, and the marginalization module is used to perform marginalization calculations and output the calculation results to the output cache.

[0011] The input buffer stores the observed values ​​output by the SLAM front end, the initial values ​​of the state variables and the prior information; the output buffer stores the updated system state and the marginalized calculation results; and the storage unit stores the linear equation group data obtained by Schur elimination.

[0012] The Jacobi update module is composed of a landmark point processing module, a key frame processing module and a visual observation processing module; the Schur elimination module is composed of a hardware matrix multiplier and a hardware vector multiplier; the Chockey decomposition module includes a cascade of multiple Chockey decomposition basic units; the state update module is composed of a triangular equation solving module and a matrix adder module; the marginalization module is composed of a hardware matrix multiplier and a matrix adder.

[0013] A design method for an environment-adaptive SLAM backend FPGA accelerator, the method comprising the following steps:

[0014] Step 1, design the hardware structure of the configurable circuit module: including the input buffer, Jacobi update module, Shure elimination module, storage unit, Chokowski decomposition module, state update module, marginalization module and output buffer connected in sequence. The configurable hardware modules are designed as Shure elimination module, Chokowski decomposition module and marginalization module. The configuration parameters are the number of multiplication and accumulation units n in the Shure elimination module. d , the number of decomposition unit modules in the Chokowski decomposition module s and the number of multiplication and accumulation units in the marginalization module n m ;

[0015] Step 2: Build a circuit model of the configurable circuit module to obtain the minimum power consumption circuit under the delay constraint: Model the delay and power consumption of the circuit. The delay model is obtained by calculating the delay of the critical path in each module of the FPGA accelerator. The delay model is a function of the configuration parameters, as shown in the following formula:

[0016]

[0017] Where m represents the number of landmarks; L Jac represents the computational delay of the Jacobian matrix update module;

[0018] L Schur (n d ) represents the computational delay of the Schur elimination, which is related to the configuration parameter n d Function of

[0019] L Cholesky (s) represents the delay of the Chokowski decomposition module, which is a function of the configuration parameter s;

[0020] L Sub The circuit delay of the state update module is independent of the circuit configuration parameters;

[0021] L Marg (n m ) represents the delay of the marginalization module, which is about the configuration parameter n m Function of

[0022] The power consumption model of the FPGA accelerator is shown in the following formula:

[0023] Power(n d ,n m ,s)=P0+n d ×P d +n m ×P m +s×P s

[0024] Among them, P0 represents a constant basic power consumption, P d , P m , P s Represents three power consumption weighting coefficients, n d 、n m , s represents three configuration parameters;

[0025] Step 3: Solve the configuration parameters that satisfy the minimum power consumption problem of the configurable circuit module, as shown in the following formula:

[0026]

[0027] Wherein, Latency(·) represents the delay model of the accelerator, Power(·) represents the power consumption model of the FPGA accelerator, min represents minimizing the circuit power consumption according to the circuit power consumption model, L* represents the maximum delay of the accelerator operation, and n d *、n m * and s* denote the initial circuit configuration of the accelerator;

[0028] Step 4, determine the configuration parameter update plan: determine whether to update the configuration according to the number of landmark points collected by the SLAM front end: first, run the SLAM algorithm, record the number of landmark points during the operation, and determine the distribution range of the number of landmark points during the operation; then, divide the number of landmark points into several intervals according to the distribution range of the number of landmark points, and when the number of landmark points changes to different intervals, update the configuration parameters of the environment adaptation;

[0029] Step 5: Implement dynamic architecture adjustment: According to the configuration parameter update result determined in step 4, a corresponding number of configurable circuit modules are turned on using a gated clock.

[0030] In step 5, the dynamic adjustment logic of the gated clock includes n d Using MAC unit to achieve, n m It is implemented using MAC units and s is implemented using Chokowski decomposition basic units.

[0031] Compared with the prior art, the environment-adaptive SLAM back-end accelerator and design method of the present invention realize dynamic architecture adjustment and can reduce power consumption during operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the structure of an environment-adaptive SLAM back-end accelerator of the present invention;

[0033] Figure 2 It is the hardware structure diagram of the configurable circuit module;

[0034] Figure 3 is a diagram of an implementation example of a dynamic adjustment logic of a gated clock;

[0035] Figure 4 It is a flow chart of an implementation of an environment-adaptive SLAM back-end accelerator of the present invention;

[0036] Reference numerals:

[0037] 10. Camera, 20. SLAM front end, 30. SLAM back end, 40. Configurable circuit module, 50. Environment adaptive parameter update module, 60. Gated clock, 401. Input buffer, 402. Jacobi update module, 403. Shure elimination module, 404. Storage unit, 405. Chokowski decomposition module, 406. State update module, 407. Output buffer. DETAILED DESCRIPTION

[0038] The specific implementation modes of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] like Figure 1As shown, it is a schematic diagram of the structure of an environment-adaptive SLAM backend FPGA accelerator of the present invention. It includes a configurable circuit module 40, an environment-adaptive parameter update module 50 and a gated clock 60 arranged at the SLAM backend 30. The visual information data obtained from the camera 10 is divided into two paths through the SLAM front end 20: one path inputs the visual information extracted from the environment to the configurable circuit module 40 arranged at the SLAM backend 30; the other path sends the number of landmark points to the environment-adaptive parameter update module 50 arranged at the SLAM backend 30. The configurable circuit module 40 is a group of parameterizable circuit modules for the calculation and storage resources of the FPGA accelerator, and each configurable circuit module corresponds to a configurable parameter. The gated clock 60 is connected to the configurable circuit module 40 and the environment-adaptive parameter update module 50 respectively, and the control is realized by means of the clock enable signal of the gated clock 6, specifically: the environment-adaptive configuration parameter update module outputs a clock enable signal, and the gated clock circuit is used to control the number of configurable circuit modules turned on, so as to realize dynamic adjustment of the architecture and reduce power consumption during operation. The relationship between the two underlined parts of the configurable circuit module and the environment adaptation is explained: the parameters of the environment adaptation are a set of configuration values ​​updated after the environment changes, and the configuration parameters are the configuration parameters before the environment changes.

[0040] According to the number of landmarks collected by the SLAM front end, 1) solve the configuration parameters that minimize the power consumption of the configurable circuit module in the current environment, and 2) update the configuration parameters of the configurable circuit module:

[0041] 1) Find the configuration parameters that minimize the power consumption of the configurable circuit module under the current environment:

[0042]

[0043] Among them, Latency(·) represents the delay model of the accelerator. At this time, the number of landmarks in the model is updated to the number of landmarks in the current environment. Power(·) represents the power consumption model of the FPGA accelerator. Min means minimizing the power consumption of the circuit according to the power consumption model of the circuit. L* represents the maximum delay of the accelerator operation. n d *、n m * and s* represent the initial circuit configuration of the accelerator. (The solution formula is the same as the solution formula in step 3, and the Latency function contains the parameter of the number of landmarks, which has changed)

[0044] 2) Update the configurable circuit module configuration parameters:

[0045] The configuration parameters of the configurable circuit module are updated to the solution result of the above formula, that is, the configuration parameters are updated to the configuration parameters that minimize the power consumption of the configurable circuit module under the current environment.

[0046] like Figure 2 , which is a hardware structure diagram of a configurable circuit module. The module includes an input buffer 401, a Jacobi update module 402, a Schur elimination module 403, a storage unit 404, a Chokowski decomposition module 405, a state update module 406, a marginalization module 407, and an output buffer 408, which are connected in sequence. The configurable parameters are the number of multiplication and accumulation units n in the Schur elimination module. d , the number of decomposition units in the Chokowski decomposition module s and the number of multiplication-accumulation units in the marginalization module n m . Among them, the input buffer 401, the output buffer 408 and the storage unit 404 realize the function of data storage, which is constructed by the on-chip storage resources of the FPGA. The input buffer 401 stores the observation values ​​output by the SLAM front end, the initial values ​​of the state variables and the prior information. The output buffer 408 stores the updated system state and the marginalization calculation results. The storage unit 404 stores the linear equation system data obtained by Schur elimination.

[0047] The Jacobi update module 402 is used to calculate the partial derivatives of the visual observation to the system optimization variables, that is, the Jacobi matrix. The module is composed of a landmark processing module, a key frame processing module and a visual observation processing module. The Schur elimination module 403 processes the Jacobi matrix and performs the Schur elimination operation. The module is composed of a hardware matrix multiplier and a hardware vector multiplier. The Chockey decomposition module 405 decomposes the coefficient matrix of the linear equations obtained by the Schur elimination module into a triangular matrix. The module contains a plurality of Chockey decomposition basic units cascaded. The state update module 406 is used to solve the increment of the state vector and output the updated state vector. The module is composed of a triangular equation solving module and a matrix adder module. The marginalization module 407 is used to perform marginalization calculations and output the calculation results to the output buffer. The module is composed of a hardware matrix multiplier and a matrix adder.

[0048] like Figure 4 As shown, it is a flow chart of a method for designing an environment-adaptive SLAM back-end accelerator of the present invention, and the process includes the following steps:

[0049] Step 1, designing the hardware structure of the configurable circuit module: including designing the configurable hardware modules as the Schur elimination module, the Chokowski decomposition module and the marginalization module, and the configuration parameters are the number of multiplication and accumulation units n in the Schur elimination module. d , the number of decomposition unit modules in the Chokowski decomposition module s and the number of multiplication and accumulation units in the marginalization module n m ;

[0050] Step 2: Build a circuit model: In order to obtain the minimum power consumption circuit under the delay constraint, it is necessary to model the delay and power consumption of the circuit. The delay model is obtained by calculating the delay of the key path in each module of the FPGA accelerator. The delay model is a function of the configuration parameters, as shown in the following formula:

[0051]

[0052] Where m represents the number of landmarks; L Jac represents the computational delay of the Jacobian matrix update module;

[0053] L Schur (n d ) represents the computational delay of the Schur elimination, which is related to the configuration parameter n d Function of

[0054] L Cholesky (s) represents the delay of the Chokowski decomposition module, which is a function of the configuration parameter s;

[0055] L Sub The circuit delay of the state update module is independent of the circuit configuration parameters;

[0056] L Marg (n m ) represents the delay of the marginalization module, which is about the configuration parameter n m function.

[0057] The power consumption model of the FPGA accelerator is shown in the following formula:

[0058] Power(n d ,n m ,s)=P0+n d ×P d +n m ×P m +s×P s

[0059] In the above formula, P0 is a constant basic power consumption, which is not affected by the configuration parameters. The power consumption affected by the configuration parameters is expressed as the configuration parameters and P d , P m , P s The weighted sum of P d , P m , P s These three power consumption weighting coefficients are respectively related to the configuration parameter n d 、n m , unit power consumption corresponding to s;

[0060] On a specific FPGA platform, the power consumption of accelerators with different configurations mainly depends on the size of the configuration parameters. The method of the present invention uses three power consumption coefficients to represent the unit power consumption of three circuit configuration parameters, uses a power consumption estimator to obtain the power consumption of accelerators under different configuration combinations, and uses a regression model to obtain the power consumption model of the accelerator.

[0061] Step 3: Solve the configuration parameters that satisfy the minimum power consumption problem of the configurable circuit module, as shown in the following formula:

[0062]

[0063] Among them, Latency(·) represents the delay model of the accelerator, Power(·) represents the power consumption model of the FPGA accelerator, and min represents minimizing the circuit power consumption according to the circuit power consumption model.

[0064] The constraints are the delay and the value of the configuration parameters. The delay needs to ensure the real-time performance of the accelerator, and L* represents the maximum delay of the accelerator operation. d *、n m * and s* represent the initial circuit configuration of the accelerator. In order to ensure that the existing resources can be used to implement the dynamic adjustment of the configuration parameters at runtime, the new configuration parameters obtained need to be no greater than the initial configuration parameters.

[0065] Step 4, determine the configuration parameter update plan: determine whether to update the configuration according to the number of landmark points collected by the SLAM front end: first, run the SLAM algorithm, the SLAM front end collects and processes the image data from the camera, extracts feature points from the collected image frames for image matching, these extracted feature points are called landmark points in the SLAM algorithm, record the number of landmark points during the operation, and determine the distribution range of the number of landmark points during the operation; then, according to the distribution range of the number of landmark points, divide the number of landmark points into several intervals, and when the number of landmark points changes to different intervals, update the configuration parameters of the environment adaptation; in step 4, the same solution formula as in step 3 is used to update the configuration parameters;

[0066] Step 5: Implement dynamic architecture adjustment: According to the configuration parameter update result determined in step 4, use the gated clock to start the corresponding number of configurable circuit modules. Figure 3 As shown in FIG. 1 , it is a diagram of an implementation example of the dynamic adjustment logic of the gated clock. d Taking the dynamically adjusted gated clock as an example, this configuration parameter corresponds to the number of multiply-accumulate (MAC) units configured in the Shure elimination module. dThe values ​​determined according to the environment are 4, 7, and 10 as an example. Since the number of enabled MAC units is at least 4, the clock signals of the 1st to 4th MAC units are always enabled. d To adjust from 4 to 7, you need to enable 3 more MAC units and use the same gated clock unit to control the clock signals of these 3 MAC units. When you need to enable 10 MAC units, you can enable both EN1 and EN2 signals at the same time. m Dynamic adjustment of the s and n parameters d The method used is the same. The difference is that n m The MAC unit is used, and s is the Chokowski decomposition basic unit. The dynamic adjustment of s changes the number of Chokowski decomposition basic units, adjusts the way the Chokowski decomposition basic unit uses the gated clock, and the control of the Chokowski decomposition basic unit is consistent with the control of the MAC). The gated clock is used to control the clock signal of the circuit module.

[0067] In summary, the SLAM back-end accelerator designed by the present invention adaptively adjusts the circuit architecture according to the changes in the environmental data collected by the front end, and opens different numbers of circuit modules according to the environmental changes to reduce the power consumption during operation. The accelerator has a group of modules with configurable circuit resources, and the resource usage, computing speed and power consumption of the circuit are changed by adjusting the configuration parameters. The configuration parameters of the circuit are determined according to the number of landmark points collected by the SLAM front end, and the circuit architecture is adaptively adjusted, and the number of configurable circuit modules turned on is controlled by using a gated clock.

[0068] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Those skilled in the art may make various modifications, equivalent substitutions or variations without departing from the spirit and scope of the present invention, and all modifications, equivalent substitutions or variations made within the spirit and principles of the present application fall within the protection scope of the present invention as defined by the appended claims.

Claims

1. An environment-adaptive SLAM backend FPGA accelerator, characterized in that: The accelerator structure includes a configurable circuit module, an environment adaptive parameter update module and a gated clock arranged at the back end of SLAM, wherein: The visual information data is divided into two paths through the SLAM front end: one path inputs the visual information extracted from the environment to the configurable circuit module set in the SLAM back end; the other path sends the number of landmark points to the environment adaptive parameter update module set in the SLAM back end; the configurable circuit module is a group of parameterizable circuit modules for computing and storage resources of the FPGA accelerator, and each configurable circuit module corresponds to a configurable parameter; the gated clock is respectively connected to the configurable circuit module and the environment adaptive parameter update module, and the control is realized by means of the clock enable signal of the gated clock, specifically: the environment adaptive configuration parameter update module outputs the clock enable signal, and the gated clock circuit is used to control the number of configurable circuit modules turned on to realize dynamic adjustment of the architecture; and according to the number of landmark points collected by the SLAM front end, the configuration parameters that minimize the power consumption of the configurable circuit module in the current environment are solved, and the configuration parameters of the configurable circuit module are updated; The configurable circuit module includes an input buffer, a Jacobi update module, a Schur elimination module, a storage unit, a Chokowski decomposition module, a state update module, a marginalization module and an output buffer connected in sequence; the configurable parameters are the number of multiplication and accumulation units n in the Schur elimination module d , the number of decomposition units in the Chokowski decomposition module s and the number of multiplication-accumulation units in the marginalization module n m ; The input cache, the output cache and the storage unit realize the function of data storage, the Jacobi update module is used to calculate the partial derivatives of visual observations with respect to system optimization variables, the Schur elimination module processes the Jacobi matrix and performs Schur elimination operations, the Chokowski decomposition module decomposes the coefficient matrix of the linear equations obtained by the Schur elimination module into a triangular matrix, the state update module is used to solve the increment of the state vector and output the updated state vector, and the marginalization module is used to perform marginalization calculations and output the calculation results to the output cache.

2. An environment-adaptive SLAM back-end FPGA accelerator as claimed in claim 1, characterized in that, The input buffer stores the observed values, initial values ​​of state variables and prior information output by the SLAM front end; the output buffer stores the updated system state and marginalized calculation results; The storage unit stores the linear equation group data obtained by Schur elimination.

3. An environment-adaptive SLAM back-end FPGA accelerator as claimed in claim 1, characterized in that, The Jacobi update module is composed of a landmark point processing module, a key frame processing module and a visual observation processing module; the Schur elimination module is composed of a hardware matrix multiplier and a hardware vector multiplier; the Chockey decomposition module includes a cascade of multiple Chockey decomposition basic units; the state update module is composed of a triangular equation solving module and a matrix adder module; the marginalization module is composed of a hardware matrix multiplier and a matrix adder.

4. The design method of a SLAM back-end FPGA accelerator of an environment adaptation as claimed in claim 1, characterized in that, The method comprises the following steps: Step 1, design the hardware structure of the configurable circuit module: including the input buffer, Jacobi update module, Shure elimination module, storage unit, Chokowski decomposition module, state update module, marginalization module and output buffer connected in sequence. The configurable hardware modules are designed as Shure elimination module, Chokowski decomposition module and marginalization module. The configuration parameters are the number of multiplication and accumulation units n in the Shure elimination module. d , the number of decomposition unit modules in the Chokowski decomposition module s and the number of multiplication and accumulation units in the marginalization module n m ; Step 2: Build a circuit model of the configurable circuit module to obtain the minimum power consumption circuit under the delay constraint: Model the delay and power consumption of the circuit. The delay model is obtained by calculating the delay of the critical path in each module of the FPGA accelerator. The delay model is a function of the configuration parameters, as shown in the following formula: Where m represents the number of landmarks; L Jac represents the computational delay of the Jacobian matrix update module; L Schur (n d ) represents the computational delay of the Schur elimination, which is related to the configuration parameter n d Function of L Cholesky (s) represents the delay of the Chokowski decomposition module, which is a function of the configuration parameter s; L Sub The circuit delay of the state update module is independent of the circuit configuration parameters; L Marg (n m ) represents the delay of the marginalization module, which is about the configuration parameter n m Function of The power consumption model of the FPGA accelerator is shown in the following formula: Power(n d ,n m ,s)=P0+n d ×P d +n m ×P m +s×P s Among them, P0 represents a constant basic power consumption, P d , P m , P s Represents three power consumption weighting coefficients, n d 、n m , s represents three configuration parameters; Step 3: Solve the configuration parameters that satisfy the minimum power consumption problem of the configurable circuit module, as shown in the following formula: Wherein, Latency(·) represents the delay model of the accelerator, Power(·) represents the power consumption model of the FPGA accelerator, min represents minimizing the circuit power consumption according to the circuit power consumption model, L* represents the maximum delay of the accelerator operation, and n d *、n m * and s* denote the initial circuit configuration of the accelerator; Step 4, determine the configuration parameter update plan: determine whether to update the configuration according to the number of landmark points collected by the SLAM front end: first, run the SLAM algorithm, record the number of landmark points during the operation, and determine the distribution range of the number of landmark points during the operation; then, divide the number of landmark points into several intervals according to the distribution range of the number of landmark points, and when the number of landmark points changes to different intervals, update the configuration parameters of the environment adaptation; Step 5: Implement dynamic architecture adjustment: According to the configuration parameter update result determined in step 4, a corresponding number of configurable circuit modules are turned on using a gated clock.

5. A method for designing an environment-adaptive SLAM back-end FPGA accelerator as claimed in claim 4, characterized in that, In step 5, the dynamic adjustment logic of the gated clock includes n d Using MAC unit to achieve, n m It is implemented using MAC units and s is implemented using Chokowski decomposition basic units.

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