Etching Method for Gate

Abstract

The present application discloses an etching method for a gate, comprising: providing a substrate, on which a first region and a second region are distributed, the first region is used to form a first type of MOS device, the second region is used to form a second type of MOS device, a gate dielectric layer is formed on the substrate, a polysilicon layer is formed on the gate dielectric layer, and a doping layer is formed in the polysilicon layer of the second region; performing a first etching until the doping layer in the target region is removed, and during the first etching process, the reaction gas introduced includes a fluorine-containing gas; performing a second etching until the polysilicon layer in the target region is removed, the remaining polysilicon layer in the first region forms the gate of the first type of MOS device, and the remaining doping layer and polysilicon layer in the second region form the gate of the second type of MOS device, and during the second etching process, the fluorine-containing gas in the reaction gas is reduced and the chlorine-containing gas in the reaction gas is increased.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and particularly relates to an etching method for a gate. Background Art

[0002] Reference Figure 1 , which shows a cross-sectional schematic diagram of a logic device etched by an etching method for a gate provided by the related art. As Figure 1 shown, a first region 101 and a second region 102 are distributed on a substrate 110 for an integrated logic device. The first region 101 is used to form a first type of metal-oxide-semiconductor field-effect transistor (MOSFET, simply referred to as "MOS" in the present application) device, and the second region 102 is used to form a second type of MOS device. After gate etching, a gate 131 of the first type of MOS device is formed on the first region 101, a gate 132 of the second type of MOS device is formed on the second region 102, and a gate dielectric layer 120 is formed between the gate and the substrate 110.

[0003] Since a doped layer 133 is formed in the gate 132 of the second type of MOS device, during the gate etching process, polysilicon layers of different materials (the doped layer and the undoped polysilicon layer) will generate different morphologies, resulting in poor uniformity of the edges of the etched gate (as Figure 1 shown by the dashed line in), reducing the reliability and yield of the device. Summary of the Invention

[0004] The present application provides an etching method for a gate, which can solve the problem that the uniformity of the edges of the gate is poor in the etching method for the gate provided by the related art. The method includes:

[0005] Providing a substrate, on which a first region and a second region are distributed. The first region is used to form a first type of MOS device, the second region is used to form a second type of MOS device, a gate dielectric layer is formed on the substrate, a polysilicon layer is formed on the gate dielectric layer, and a doped layer is formed in the polysilicon layer of the second region;

[0006] Performing a first etching until the doped layer in the target region is removed. During the first etching process, the reaction gas introduced includes a fluorine-containing gas;

[0007] Perform a second etching until the polysilicon layer in the target region is removed. The remaining polysilicon layer in the first region forms the gate of the MOS device of the first type, and the remaining doped layer and polysilicon layer in the second region form the gate of the MOS device of the second type. During the second etching process, reduce the fluorine-containing gas in the reaction gas and increase the chlorine-containing gas in the reaction gas.

[0008] In some embodiments, during the first etching process, the etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is greater than 1.

[0009] In some embodiments, during the second etching process, the etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is reduced from greater than 1 to less than 0.5.

[0010] In some embodiments, the fluorine-containing gas includes at least one of carbon tetrafluoride, trifluoromethane, difluoromethane, octafluorocyclobutane, and nitrogen trifluoride.

[0011] In some embodiments, the chlorine-containing gas includes chlorine gas.

[0012] In some embodiments, the MOS device of the first type is a PMOS device, and the MOS device of the second type is an NMOS device.

[0013] The technical solution of the present application has at least the following advantages:

[0014] During the manufacturing process of the logic device, when performing gate etching, the doped layer in the polysilicon layer is etched by a reaction gas including a fluorine-containing gas, and the fluorine-containing gas in the reaction gas is gradually reduced and the chlorine-containing gas is increased when etching the undoped polysilicon layer, improving the uniformity of the topography on both sides of the gate, and thus improving the reliability and yield of the device. Description of the Drawings

[0015] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 is a cross-sectional schematic diagram of a logic device etched by an etching method of a gate provided by the related art;

[0017] Figure 2 is a flowchart of an etching method of a gate provided by an exemplary embodiment of the present application;

[0018] Figure 3It is a schematic cross-sectional view of a logic device etched by the gate etching method provided by an exemplary embodiment of the present application. Detailed implementation manners

[0019] The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0020] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0021] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the internal connection of two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.

[0022] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0023] Refer to Figure 2 , which shows a flowchart of the gate etching method provided by an exemplary embodiment of the present application. As Figure 2 shown, the method includes:

[0024] Step S1: Provide a substrate, on which a first region and a second region are distributed. The first region is used to form a first type of MOS device, and the second region is used to form a second type of MOS device. A gate dielectric layer is formed on the substrate, a polysilicon layer is formed on the gate dielectric layer, and a doping layer is formed in the polysilicon layer of the second region.

[0025] Step S2, perform the first etching until the doped layer in the target area is removed. During the first etching process, the reaction gas introduced includes a fluorine-containing gas.

[0026] Among them, the fluorine-containing gas includes at least one of carbon tetrafluoride (CF 4 ), trifluoromethane (CHF 3 ), difluoromethane (CH 2 F 2 ), octafluorocyclobutane (C 4 F 8 ), and nitrogen trifluoride (NF 3 ); during the first etching process, the etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is greater than 1.

[0027] Step S3, perform the second etching until the polysilicon layer in the target area is removed. The remaining polysilicon layer in the first area forms the gate of the first type of MOS device, and the remaining doped layer and polysilicon layer in the second area form the gate of the second type of MOS device. During the second etching process, reduce the fluorine-containing gas in the reaction gas and increase the chlorine-containing gas in the reaction gas.

[0028] Among them, the chlorine-containing gas includes chlorine gas (Cl 2 ); during the second etching process, the etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is reduced from greater than 1 to less than 0.5. As Figure 3 shown, the first area 301 and the second area 302 are distributed on the substrate 310. The first area 301 is used to form the first type of MOS device, and the second area 302 is used to form the second type of MOS device. The first type of MOS device can be a PMOS device, and the second type of MOS device can be an NMOS device. After the second etching, the gate 331 of the PMOS device is formed in the first area 301, and the gate 332 of the NMOS device is formed in the second area 302. The gate dielectric layer 320 is between the gate and the substrate 310. The gates (the gate 331 of the PMOS device and the gate 332 of the NMOS device) formed by the gate etching method provided by the embodiments of the present application have better uniformity in the morphology on both sides (as Figure 3 shown by the dotted line).

[0029] In summary, in the embodiments of the present application, during the manufacturing process of logic devices, when performing gate etching, by using a reaction gas including a fluorine-containing gas to etch the doped layer in the polysilicon layer, and gradually reducing the fluorine-containing gas and increasing the chlorine-containing gas in the reaction gas when etching the undoped polysilicon layer, the uniformity of the morphology on both sides of the gate is improved, thereby improving the reliability and yield of the device.

[0030] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. An etching method for a gate, characterized in that, the method comprises: providing a substrate, on which a first region and a second region are distributed, the first region is used to form a first type of MOS device, the second region is used to form a second type of MOS device, a gate dielectric layer is formed on the substrate, a polysilicon layer is formed on the gate dielectric layer, and a doping layer is formed in the polysilicon layer of the second region; performing a first etching until the doping layer in the target region is removed. During the first etching, the reaction gas introduced includes a fluorine-containing gas. During the first etching, the etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is greater than 1. The fluorine-containing gas includes at least one of carbon tetrafluoride, trifluoromethane, difluoromethane, octafluorocyclobutane, and nitrogen trifluoride, and the chlorine-containing gas includes chlorine; performing a second etching until the polysilicon layer in the target region is removed. The remaining polysilicon layer in the first region forms the gate of the first type of MOS device, and the remaining doping layer and polysilicon layer in the second region form the gate of the second type of MOS device. During the second etching, the fluorine-containing gas in the reaction gas is reduced, and the chlorine-containing gas in the reaction gas is increased. During the second etching, the etching ratio of the fluorine-containing gas to the chlorine-containing gas in the reaction gas is reduced from greater than 1 to less than 0.

5.

2. The method according to claim 1, characterized in that, the first type of MOS device is a PMOS device, and the second type of MOS device is an NMOS device.

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